CN207354494U - A kind of image processing system - Google Patents
A kind of image processing system Download PDFInfo
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- CN207354494U CN207354494U CN201721406887.XU CN201721406887U CN207354494U CN 207354494 U CN207354494 U CN 207354494U CN 201721406887 U CN201721406887 U CN 201721406887U CN 207354494 U CN207354494 U CN 207354494U
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Abstract
The utility model belongs to technical field of image processing, there is provided a kind of image processing system.In the utility model,By using including imaging sensor,Fpga chip,Display,First memory,Second memory,The image processing system of power management chip and jtag interface,So that power management chip is powered to first memory,Jtag interface downloads the application program of fpga chip by exterior downloader,And application program is stored to first memory or second memory,Second memory is when image processing system starts,Application program is loaded onto fpga chip,Imaging sensor gathers image information,And image information is sent to fpga chip,Fpga chip carries out decoding process to generate image to image information,Image is zoomed in and out and splicing after send to first memory and cache,And read from first memory by scaling and the image after splicing,Shown with sending to display.The image processing system flexibility is strong, and versatility is high.
Description
Technical field
The utility model belongs to technical field of image processing, more particularly to a kind of image processing system.
Background technology
With developing rapidly for the markets such as unmanned plane, reverse image, machine vision, the importance of image processing techniques is not sayed
And explain.At present, traditional image processing techniques is the integrated circuit (Application for being based upon special purpose and designing
Specific Integrated Circuit, ASIC) realize.Wherein, ASIC refers to special application integrated circuit, it is led
If the logic IC of the special requirement specially designed for a certain fixed algorithm or application, and if algorithm fix and into
It is ripe, it is possible to carry out ASIC customizations so that product power consumption smaller, processing speed faster, reliability higher.
However, due to ASIC in practical applications, to customize the cycle long, of high cost, and changes and transplant after the completion of design
Property it is poor, therefore, based on ASIC realize image processing techniques, exist because the characteristics of ASIC flexibilities are low causes to be built with it
Image acquisition and processing system the problem of lacking enough versatilities.
Therefore, it is necessary to a kind of technical solution is provided, to solve above-mentioned technical problem.
Utility model content
The purpose of this utility model is to provide a kind of image processing system, it is intended to solves conventional images treatment technology and is deposited
Cause to lack asking for enough versatility with the image acquisition and processing system of its structure because of the characteristics of ASIC flexibilities are low
Topic.
The utility model is realized in this way a kind of image processing system, described image processing system includes：
Multiple images sensor, fpga chip, display, first memory, second memory, power management chip and
Jtag interface；
The output terminal of described image sensor is connected with the first input end of the fpga chip, the first memory
Output terminal is connected with the second input terminal of the fpga chip, and the of the output terminal of the second memory and the fpga chip
Three input terminals connect, and the output terminal of the fpga chip is connected with the input terminal of the display, and the of the first memory
One input terminal is connected with the output terminal of the power management chip, and the second input terminal and the JTAG of the first memory connect
The first output terminal connection of mouth, the second output terminal of the jtag interface is connected with the input terminal of the second memory, described
The input terminal of jtag interface is connected with exterior downloader；
The power management chip provides supply voltage for the first memory；The jtag interface passes through the outside
Downloader downloads the application program of the fpga chip, and the application program is stored to the first memory or described the
Two memories；The application program is loaded onto the FPGA by the second memory when described image processing system starts
Chip；Described image sensor gathers image information, and described image information is sent to the fpga chip；The FPGA cores
Piece carries out described image information decoding process to generate image, described image is zoomed in and out and splicing after send to institute
State first memory to be cached, and the image after scaling and splicing is read from the first memory, with hair
Send to the display and shown.
In the utility model, by using including imaging sensor, fpga chip, display, first memory, second
The image processing system of memory, power management chip and jtag interface so that power management chip provides for first memory
Supply voltage, jtag interface download the application program of fpga chip by exterior downloader, and application program is stored to first
Application program is loaded onto fpga chip by memory or second memory, second memory when image processing system starts, figure
As sensor collection image information, and image information is sent to fpga chip, fpga chip image information is carried out at decoding
Reason to generate image, image is zoomed in and out and splicing after send to first memory and cache, and from the first storage
The image after scaling and splicing is read in device, is shown with sending to display so that the utility model provides
Image processing system flexibility enhancing, versatility improve, and then solve present in conventional images treatment technology because of ASIC
The problem of the characteristics of flexibility is low causes to lack enough versatilities with the image acquisition and processing system of its structure.
Brief description of the drawings
Fig. 1 is the modular structure schematic diagram for the image processing system that one embodiment of the utility model is provided.
Embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, is further elaborated the utility model.It should be appreciated that specific embodiment described herein is only explaining
The utility model, is not used to limit the utility model.
It is described in detail below in conjunction with realization of the specific attached drawing to the utility model：
Fig. 1 shows the modular structure for the image processing system 10 that one embodiment of the utility model is provided, for the ease of
Illustrate, illustrate only part related to the present embodiment, details are as follows：
As shown in Figure 1, the image processing system 10 that the utility model embodiment is provided includes：Multiple images sensor
100 (being illustrated in figure exemplified by four), fpga chip 101, display 102, first memory 103, second memory
104th, power management chip 105 and jtag interface 106.
Wherein, the output terminal of imaging sensor 100 is connected with the first input end of fpga chip 101, first memory 103
Output terminal be connected with the second input terminal of fpga chip 101, the of the output terminal of second memory 104 and fpga chip 101
Three input terminals connect, and the output terminal of fpga chip 101 is connected with the input terminal of display 102, and the first of first memory 103 is defeated
The output terminal for entering end with power management chip 105 is connected, and the of the second input terminal of first memory 103 and jtag interface 106
One output terminal connects, and the second output terminal of jtag interface 106 is connected with the input terminal of second memory 104, jtag interface 106
Input terminal is connected with exterior downloader (not shown).
Specifically, power management chip 105 provides supply voltage for first memory 103；Jtag interface 106 passes through outside
Downloader downloads the application program of fpga chip 101, and application program is stored to first memory 103 or second memory
104；Application program is loaded onto fpga chip 101 by second memory 104 when image processing system 10 starts；Image sensing
Device 100 gathers image information, and image information is sent to fpga chip 101；Fpga chip 101 decodes image information
Processing to generate image, image is zoomed in and out and splicing after send to first memory 103 and cache, and from first
The image after scaling and splicing is read in memory 103, is shown with sending to display 102.
When it is implemented, between imaging sensor 100 and fpga chip 101, between fpga chip 101 and display 102
Connected using MIPI interface modes.That is, after imaging sensor 100 collects image information, imaging sensor 100
Image information is sent to fpga chip 101 by MIPI agreements, in order to which fpga chip 101 decodes the image information
Processing, to generate multiple image.
Further, after the image information that fpga chip 101 is sent according to imaging sensor 100 generates multiple image,
The embedded Digital Signal Processing (Digital Signal Processing, DSP) of fpga chip 101 carries out at computing image
Reason, the calculation process include but not limited to the one or more of the processing such as amplification, diminution, splicing.
After fpga chip 101 carries out calculation process to the multiple image of generation, fpga chip 101 is by after the calculation process
Image store into first memory 103, to be cached, and need the image after the calculation process is shown
When, the image after the calculation process is read from first memory 103, and by MIPI agreements by the figure after the calculation process
As sending to display 102, in order to which display 102 shows the image after the calculation process.
It should be noted that in the utility model embodiment, it is aobvious in image processing system 10 provided in this embodiment
Show that device 102 can be realized by a large screen display, can also be spliced by multiple small screen displays and realized, in Fig. 1 only
It is to be illustrated exemplified by one, herein and is not particularly limited；In addition, jtag interface 106 can use standard interface to realize, its
It is connected directly with the downloader at PC ends, is deposited by the application program needed for the downloader download fpga chip 101 at PC ends to first
While reservoir 103 or second memory 104, artificial debugging function is also supported.
Further, as one preferred embodiment of the utility model, the model GW2A-18k of fpga chip 101.
Wherein, in the utility model embodiment, fpga chip 101 refers to field programmable gate array (Field-
Programmable Gate Array, FPGA) chip, and the field programmable gate array chip preferentially uses model
The chip of GW2A-18k is realized.
In the present embodiment, since 101 operational capability of fpga chip of model GW2A-18k is strong, real-time is good, and holds
Amount is big, and therefore, the image processing system 100 for carrying out image procossing using the fpga chip 101 has real-time, disposal ability
Height, and the advantages that acp chip production domesticization；In addition, the fpga chip 101 of model GW2A-18k is because it uses BGA256 to encapsulate,
Input/output interface quantity is more, and the advantages of support multichannel input and output so that using the image procossing system of the fpga chip 101
System 10 has the scalability, using flexible, circuit stability and it is integrated simple the features such as, while reduce the image processing system
10 cost, shortens the design cycle of image processing system 10, so that the image processing system 10 can be widely applied to
In the fields such as unmanned plane, reverse image, automobile data recorder.
Further, as one preferred embodiment of the utility model, first memory 103 is DDR3 memory chips.
Wherein, in the utility model embodiment, first memory 103 refers to first memory for DDR3 memory chips
103 can use existing DDR3 main memory circuits to realize, which includes DDR3 memory grains and peripheral components, this is outer
Peripheral device includes but not limited to resistance, capacitance etc., and the concrete structure of the DDR3 main memory circuits refers to the prior art, herein not
Repeat again.
In the present embodiment, it can effectively improve the utility model as first memory 103 using DDR3 memory chips and carry
The versatility of the image processing system 10 of confession, and reduce the power consumption of the image processing system 10.
Further, as one preferred embodiment of the utility model, the model of DDR3 memory chips
MT41J128M16。
It should be noted that in the utility model embodiment, the DDR3 memory chips as first memory 103 can be adopted
The DDR3 memory chips for being MT41J128M16 with magnesium light company model realize that the capacity of the DDR3 memory chips is 2Gbit, should
Interim storage of the DDR3 memory chips of MT41J128M16 as image processing system 10, in image operation, processing and display
It can effectively realize information cache.
In the present embodiment, it is real-time as the progress image of fpga chip 101 using the DDR3 memory chips of MT41J128M16
The caching of processing, may be such that fpga chip 101 reliably preserves data in image processing process, can also improve
Speed of the fpga chip 101 in image processing process.
Further, as one preferred embodiment of the utility model, second memory 104 is solid-state memory and animation
Editing machine chip.Preferably, the model W25Q64DW of the solid-state memory and Animation Editors chip.
Wherein, in the utility model embodiment, second memory 104 refers to for solid-state memory with Animation Editors chip
Be second memory 104 can use existing Flash storage circuits realize, the Flash storage circuits include Flash chip and
Peripheral components, which includes but not limited to capacitance, resistive element etc., and the concrete structure of the Flash storage circuits can
With reference to the prior art, details are not described herein again.
Further, when it is implemented, the solid-state memory can use model W25Q64DW with Animation Editors chip
Flash chip realize, the Flash chip capacity of model W25Q64DW is 64Mbit, can store fpga chip 101 and work
Required application program, and when image processing system 10 starts, which is loaded into fpga chip 101.
In the present embodiment, using the Flash chip of model W25Q64DW as second memory 103 so that should
Flash chip can store application program required when fpga chip 101 works, and be deposited into without increasing in fpga chip 101
Reservoir, to store the application program, effectively reduces the design difficulty of fpga chip 101, and can reduce the body of fpga chip 101
Product.
Further, as one preferred embodiment of the utility model, imaging sensor 100 is the figure of model OV5640
As sensor module.
Wherein, in the utility model embodiment, the imaging sensor module highest of model OV5640 supports 5,000,000
Camera function and 720P, 30fps high definition video recording of pixel, the i.e. resolution ratio of the imaging sensor module of model OV5640 are
1280*720, and 30 frame picture per second.
Further, as one preferred embodiment of the utility model, the model TXD550 of display 102.
Wherein, in the utility model embodiment, the display of model TXD550 supports 1080p to show, its conduct
The image output unit of image processing system 10, can carry out real-time display to the image handled by fpga chip 101.
Further, as one preferred embodiment of the utility model, it is characterised in that the type of power management chip 105
Number it is TPS51200DRCR.
Wherein, in the utility model embodiment, using the chip of model TPS51200DRCR as power management core
Piece is referred in specific implementation process, can use the power management chip and peripheral device for including model TPS51200DRCR
The memory power supply management circuit of part realizes that the peripheral components include but not limited to the components such as resistance, capacitance, and memory electricity
The concrete structure of power management circuits refers to the prior art, and details are not described herein again.
Specifically, the power management chip of model TPS51200DRCR can produce the termination voltage of 0.75V and with reference to electricity
Pressure, to power for first memory 103 and implement to manage.
In the present embodiment, powered using the power management chip of TPS51200DRCR to first memory 103, it is ensured that
103 reliably working of first memory, in order to which first memory 103 carries out the slow of view synthesis as fpga chip 101
Deposit, so as to improve the real-time of image processing system 10.
In the utility model, by using including imaging sensor, fpga chip, display, first memory, second
The image processing system of memory, power management chip and jtag interface so that power management chip provides for first memory
Supply voltage, jtag interface download the application program of fpga chip by exterior downloader, and application program is stored to first
Application program is loaded onto fpga chip by memory or second memory, second memory when image processing system starts, figure
As sensor collection image information, and image information is sent to fpga chip, fpga chip image information is carried out at decoding
Reason to generate image, image is zoomed in and out and splicing after send to first memory and cache, and from the first storage
The image after scaling and splicing is read in device, is shown with sending to display so that the utility model provides
Image processing system flexibility enhancing, versatility improve, and then solve present in conventional images treatment technology because of ASIC
The problem of the characteristics of flexibility is low causes to lack enough versatilities with the image acquisition and processing system of its structure.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
All any modification, equivalent and improvement made within the spirit and principle of utility model etc., should be included in the utility model
Protection domain within.
Claims (9)
1. a kind of image processing system, it is characterised in that described image processing system includes：
Multiple images sensor, fpga chip, display, first memory, second memory, power management chip and JTAG
Interface；
The output terminal of described image sensor is connected with the first input end of the fpga chip, the output of the first memory
End is connected with the second input terminal of the fpga chip, and the 3rd of the output terminal of the second memory and the fpga chip is defeated
Enter end connection, the output terminal of the fpga chip is connected with the input terminal of the display, and the first of the first memory is defeated
Enter end to be connected with the output terminal of the power management chip, the second input terminal and the jtag interface of the first memory
First output terminal connects, and the second output terminal of the jtag interface is connected with the input terminal of the second memory, the JTAG
The input terminal of interface is connected with exterior downloader；
The power management chip provides supply voltage for the first memory；The jtag interface passes through the exterior download
Device downloads the application program of the fpga chip, and the application program is stored to the first memory or described second and is deposited
Reservoir；The application program is loaded onto the fpga chip by the second memory when described image processing system starts；
Described image sensor gathers image information, and described image information is sent to the fpga chip；The fpga chip pair
Described image information carries out decoding process to generate image, described image is zoomed in and out and splicing after send to described the
One memory is cached, and the image after scaling and splicing is read from the first memory, to send extremely
The display is shown.
2. image processing system according to claim 1, it is characterised in that the model GW2A- of the fpga chip
18k。
3. image processing system according to claim 1, it is characterised in that the first memory is DDR3 memory cores
Piece.
4. image processing system according to claim 3, it is characterised in that the model of the DDR3 memory chips
MT41J128M16。
5. image processing system according to claim 1, it is characterised in that the second memory for solid-state memory with
Animation Editors chip.
6. image processing system according to claim 5, it is characterised in that the solid-state memory and Animation Editors core
The model W25Q64DW of piece.
7. image processing system according to claim 1, it is characterised in that described image sensor is model OV5640
Imaging sensor module.
8. image processing system according to claim 1, it is characterised in that the model TXD550 of the display.
9. according to claim 1 to 8 any one of them image processing system, it is characterised in that the power management chip
Model TPS51200DRCR.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721406887.XU CN207354494U (en) | 2017-10-27 | 2017-10-27 | A kind of image processing system |
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| CN201721406887.XU CN207354494U (en) | 2017-10-27 | 2017-10-27 | A kind of image processing system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110758291A (en) * | 2019-11-13 | 2020-02-07 | 合肥杰发科技有限公司 | Control method, controller, system and storage medium of reversing image system |
| CN115209024A (en) * | 2022-07-18 | 2022-10-18 | 湖南华南光电(集团)有限责任公司 | FPGA (field programmable Gate array) electronic zoom preposed DDR (double data Rate) based camera system |
-
2017
- 2017-10-27 CN CN201721406887.XU patent/CN207354494U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110758291A (en) * | 2019-11-13 | 2020-02-07 | 合肥杰发科技有限公司 | Control method, controller, system and storage medium of reversing image system |
| CN110758291B (en) * | 2019-11-13 | 2021-04-27 | 合肥杰发科技有限公司 | Control method, controller, system and storage medium of reversing image system |
| CN115209024A (en) * | 2022-07-18 | 2022-10-18 | 湖南华南光电(集团)有限责任公司 | FPGA (field programmable Gate array) electronic zoom preposed DDR (double data Rate) based camera system |
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