CN113438474B

CN113438474B - Camera module testing device and control method thereof

Info

Publication number: CN113438474B
Application number: CN202110722518.6A
Authority: CN
Inventors: 邬刚; 胡立峰
Original assignee: Hangzhou Acceleration Technology Co ltd
Current assignee: Hangzhou Acceleration Technology Co ltd
Priority date: 2021-06-28
Filing date: 2021-06-28
Publication date: 2023-03-14
Anticipated expiration: 2041-06-28
Also published as: CN113438474A

Abstract

The invention provides a camera module testing device and a control method thereof. The device comprises a power supply module and a processing module, wherein the processing module is provided with an FPGA and a microprocessor, the FPGA is provided with an interface unit, an early-stage testing unit and a transmission unit, the microprocessor is provided with an analysis testing unit and is externally connected with a memory device; the interface unit receives image data; the early-stage testing unit performs early-stage testing on the image data; the transmission unit transmits the data to the memory device for caching; the analysis test unit performs analysis test on the image data cached in the memory device. The invention solves the defects of large volume, high cost and difficult portable operation of the existing camera module test equipment, adopts the FPGA and the microprocessor to carry out test analysis on the image together, shortens the test time, improves the test efficiency, can realize the camera module test without a computer, and has the characteristics of small volume, low running cost and simple operation.

Description

Camera module testing device and control method thereof

Technical Field

The invention relates to the field of camera module testing, in particular to a camera module testing device and a control method thereof.

Background

In the era of smart phones, the photographing function becomes one of the most important functions of smart phones, and great attention is paid to the photographing function by various mobile phone manufacturers. The mobile phone camera module test is closely related to the shooting function, the picture quality, the use feeling of consumers and the overall performance of the mobile phone. Because the market of the smart phone is huge, the test requirement of the corresponding camera module is very large.

The test of camera module is the very important detection link of machine. Camera module manufacturers often need to purchase a large amount of test equipment to meet their test requirements. The traditional camera module testing equipment is large in size and high in cost, and analysis and test of image data shot by the camera module need to be carried out by means of a computer.

The ordinary maintenance merchant usually does not have the capability of camera module test because it can not bear the high survey cost of establishing, and this has brought the hindrance to the popularization and application of smart mobile phone. Once the camera of cell-phone is impaired, the user lacks professional test equipment, hardly carries out the test of camera module, can only seek professional maintenance department and test. In addition, the computer is adopted for testing, the testing time is long, for a camera module manufacturer, the testing time is basically equal to the productivity, the shortening of the testing time of the product is equal to the improvement of the productivity, and the development of the camera module manufacturer is severely restricted by the cost brought by the testing time.

Therefore, a camera module testing scheme with low cost, small volume, convenient operation and short testing time is urgently needed to solve the problems.

Disclosure of Invention

In view of this, the present invention provides a camera module testing apparatus and a control method thereof, and the specific scheme is as follows:

a camera module testing device comprises a power module and a processing module, wherein the processing module is electrically connected with the power module;

the processing module is provided with an FPGA and a microprocessor, the FPGA is provided with an interface unit, an early-stage testing unit and a transmission unit, and the microprocessor is provided with an analysis testing unit;

the interface unit is connected with the camera module and used for receiving image data from the camera module;

the early-stage testing unit is used for carrying out early-stage testing on the image data to obtain first testing data and transmitting the image data and the first testing data to the transmission unit;

the microprocessor is externally connected with a memory device, and the transmission unit is used for transmitting the image data and the first test data to the memory device for caching;

the analysis test unit is used for analyzing and testing the image data cached in the memory device to obtain second test data, and the first test data and the second test data are used as output data.

In a specific embodiment, an IIC control unit is further disposed on the processing module, and the IIC control unit establishes a communication connection with the camera module through IIC;

the IIC control unit is used for carrying out initialization configuration on the camera module.

In a specific embodiment, the system further comprises a storage module;

the storage module is connected with the analysis test unit and used for receiving and storing the output data.

In a particular embodiment, the transport unit is configured with VDMA;

and/or the memory device comprises a DDR4 memory bank;

and/or the processing module is provided with a ZYNQ chip, and the FPGA and the microprocessor are integrated on the ZYNQ chip.

In a specific embodiment, the interface unit includes an MIPI CSI-2 interface;

the maximum data link quantity of the interface unit supports 4Lane, and the maximum line rate supports 2.5Gbps/Lane.

In one embodiment, the pre-stage testing includes resolution testing;

the resolution test specifically comprises the following steps of acquiring the line length and the column length of an image:

each line tail of the image is provided with a line tail mark, and the last frame of each image is provided with a frame tail mark;

every time a pixel is received, the numerical value of a preset line length counter is increased by one until the line tail identification is received;

outputting the numerical value of the line length counter to obtain the line length of the image;

every time one line tail mark is received, adding one to the value of a preset column length counter until the frame tail mark is received;

and outputting the numerical value of the column length counter to obtain the image column length.

In a particular embodiment, the early stage testing includes frame rate testing;

the frame rate test comprises the following steps:

within one second, adding one to the numerical value of a preset frame rate counter every time one frame tail identification is received;

and outputting the numerical value of the frame rate counter to obtain the image frame rate.

A control method of a camera module testing device is applied to the camera module testing device, the device comprises a processing module and a power supply module, and the power supply module provides electric energy for the processing module;

the processing module is provided with an FPGA and a microprocessor, the FPGA is provided with an interface unit, an early-stage testing unit and a transmission unit, the microprocessor is externally connected with a memory device, and the microprocessor is provided with an analysis testing unit;

the control method comprises the following steps:

receiving image data from the camera module through the interface unit;

the image data is subjected to early-stage testing through the early-stage testing unit to obtain first testing data, and the image data and the first testing data are transmitted to the transmission unit;

the transmission unit transmits the image data and the first test data to the memory device for caching;

and the analysis test unit performs analysis test on the image data cached in the memory device to obtain second test data, and takes the first test data and the second test data as output data.

before receiving the image data from the camera module, still include:

and carrying out initialization configuration on the camera module through the IIC control unit.

In a specific embodiment, the device further comprises a storage module, wherein the storage module is connected with the analysis test unit;

after acquiring the output data, further comprising:

and receiving and storing the output data through the storage module.

Has the advantages that: the invention provides a camera module testing device and a control method thereof. The device adopts FPGA and microprocessor to test the analysis to the image jointly, based on FPGA's parallel processing advantage, carries out analysis and test to some parameters when the image is received, has shortened test time, has promoted efficiency of software testing. The FPGA and the microprocessor are integrated on the circuit board, the camera module can be tested without a computer, the size is small, the operation cost is low, the operation is simple, and the defects that the camera module testing equipment in the prior art is large in size, high in cost and difficult to carry are overcome.

Drawings

Fig. 1 is a system block diagram of a camera module testing device according to an embodiment of the present invention;

FIG. 2 is a flowchart of a control method of the testing device of the camera module according to the embodiment of the present invention;

FIG. 3 is a flowchart of a control method of a testing device for a camera module according to an embodiment of the present invention;

FIG. 4 is a flowchart of an embodiment of the present invention for obtaining line length of an image;

FIG. 5 is a flowchart of an embodiment of the present invention for obtaining a column length of an image;

FIG. 6 is a flowchart illustrating an embodiment of obtaining an image frame rate.

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Reference numerals: 1-a camera module; 2-a processing module; 3-a power supply module; 4-an interface unit; 5-a preliminary test unit; 6-a transmission unit; 7-a memory device; 8-an analytical test unit; 9-IIC control unit; 10-a storage module; 21-FPGA; 22-a microprocessor.

Detailed Description

Various embodiments of the present disclosure will be described more fully hereinafter. The present disclosure is capable of various embodiments, and modifications and variations are possible therein. However, it should be understood that: there is no intention to limit the various embodiments of the disclosure to the specific embodiments disclosed herein, but rather, the disclosure is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the disclosure.

The embodiment is based on the prior art, and provides the camera module testing device and the control method thereof aiming at the problems of high manufacturing cost and large volume of camera module testing equipment, so that the image data can be analyzed and tested without a computer, the testing cost is low, the device is small and portable, the operation is simple, and a user can analyze and test the image data of the camera module at any time. The FPGA is combined with the microprocessor, the FPGA carries out early-stage testing, and the microprocessor carries out later-stage testing, so that the testing time is greatly shortened, and the testing efficiency is improved.

The terminology used in the various embodiments of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present disclosure belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in various embodiments of the present disclosure.

Example 1

The embodiment 1 of the invention discloses a camera module testing device, a system block diagram specification of which is shown in an attached figure 1, and the specific scheme is as follows:

a camera module testing device comprises a power module 3 and a processing module 2, wherein the processing module 2 is electrically connected with the power module 3. The processing module 2 is a main image testing device and is connected with the external camera module 1. The power module 3 provides electric energy for the processing module 2, so that the testing device can be tested at any time and any place, and the application scene limitation of the testing device is reduced.

The processing module 2 is provided with an FPGA (programmable gate array) 21 and a microprocessor 22. The FPGA21 is provided with an interface unit 4, a previous stage testing unit 5 and a transmission unit 6, the microprocessor 22 is provided with an analysis testing unit 8, and the interface unit 4 is connected with the external camera module 1. In addition, the IIC control unit 9 for configuring the camera module 1 is further provided on the processing module 2. The analytical test element 8 may be connected externally to other devices for displaying or acquiring output data. The complete functional block diagram is shown in the specification and attached with figure 1, and the testing flow is shown in the specification and attached with figure 2.

In this embodiment, the pre-processing of the image data mainly includes performing parameter analysis, such as resolution and frame rate, through a logic function module on the FPGA21, and the image test analysis of the post-processing mainly includes performing test analysis through a program on the microprocessor 22. Through combining together earlier stage processing and post processing, realize camera module 1's complete test, very big shortening test time.

The IIC control unit 9 establishes communication connection with the camera module 1 through IIC, and the IIC control unit 9 carries out initialization configuration on the camera module 1. Before data transmission, the IIC control unit 9 is used for carrying out initialization configuration on the camera module 1, and after initialization is completed, the interface module is used for receiving image data from the camera module 1.

In this embodiment, the processing module 2 is a ZYNQ chip. The ZYNQ chip is small in size and far lower in cost than traditional large-scale test equipment. The ZYNQ chip is integrated with an FPGA21 (programmable gate array) and an ARM (a kind of microprocessor), which meets the requirements related to the processing module 2 of the present embodiment. In this embodiment, the FPGA21 part is denoted as PL terminal, and the ARM part is denoted as PS terminal. The image analysis and test work is carried out in the ZYNQ chip without a computer, so that the cost is reduced, and the volume is reduced. Preferably, the model of the ZYNQ chip is Xilinx XCZU3EG-SFVC784.

The interface unit 4 is used for connecting an external camera module 1 and is responsible for receiving image data from the camera module 1. In the present embodiment, the interface unit 4 includes, but is not limited to, any known interface form that can be used to transmit image data. Preferably, the interface unit 4 selects an MIPI CSI-2 interface. MIPI CSI-2 is a simple high-speed protocol primarily used for point-to-point image and video transmission between a camera and a host device, and interfaces complying with this protocol are referred to as MIPI CSI-2 interfaces. MIPI aims to standardize interfaces inside a mobile phone, such as a camera, a display interface, a radio frequency/baseband interface, and the like, thereby reducing the complexity of mobile phone design and increasing design flexibility. Different chips and modules can be flexibly selected from the market by mobile phone manufacturers according to requirements, and design and functions can be changed quickly and conveniently. The CSI interface has the advantages of few interfaces, strong EMI resistance, high speed, low power consumption and the like. The CSI-2 is the second version of MIPI CSI, the CSI-2 consists of an application layer, a protocol layer and a physical layer, 4-channel data transmission is supported to the maximum extent, the single-wire transmission speed is up to 1Gb/s, and the maximum wire speed supports 2.5Gbps/Lane. The embodiment selects MIPI CSI-2 interface, and can be adapted to most camera test modules on the market.

The early-stage testing unit 5 is arranged on the PL terminal, is connected with the transmission unit 6 and the interface unit 4, and is used for performing early-stage testing on the image data to obtain first testing data. The interface unit 4 is responsible for receiving image data from the camera module 1, and the image data is mainly an image. After receiving the image data, it is necessary to perform a preliminary test on the image data, including performing a parameter analysis on the image data, such as analyzing a resolution and a frame rate of the image. The early-stage test unit 5 is only a preliminary process for the image data from the camera module 1. In the present embodiment, the core image analysis test mainly passes through the analysis test unit 8 in the ARM.

Wherein the resolution and frame rate are two of many parameters to be tested. In particular, the present embodiment sets the resolution test and the frame rate test at the PL side, and performs the test using the FPGA 21. Due to the parallel processing advantage of the FPGA21, some parameters, such as resolution, frame rate, etc., can be analyzed and tested while receiving the image. The resolution test and the frame rate test are different from other parameters and originally need to be transmitted to an ARM processor for analysis test, and the test in the FPGA21 is faster than that in the ARM processor, so that the test time can be greatly shortened. And obtaining first test data through a resolution test and a frame rate test. The first test data and the image data are cached in the memory device 7 through the transmission unit 6, then the ARM processor takes out the first test data and the image data from the memory device 7, analysis and processing are carried out, and testing of other parameters is carried out through the ARM processor. And the final test result is analyzed and processed by the ARM processor and then written into the storage module 10.

Wherein the process of testing the resolution of the image comprises acquiring a row length and a column length of the image. Each line tail of the image is provided with a line tail mark, and the last frame of the image is provided with a frame tail mark; the process of testing the resolution specifically comprises:

every time a pixel is received, the numerical value of a preset line length counter is increased by one until a line tail mark is received; and outputting the numerical value of the line length counter to obtain the line length of the image. The specific flow chart is shown in figure 4 in the specification.

When a line tail mark is received, adding one to the value of a preset column length counter until a frame tail mark is received; and outputting the numerical value of the column length counter to obtain the image column length. The specific flow chart is shown in the attached figure 5 in the specification.

The process of testing the frame rate specifically includes:

within one second, every time a frame tail identifier is received, adding one to the numerical value of a preset frame rate counter; and outputting the value of the frame rate counter to obtain the image frame rate. The specific flow chart is shown in figure 6 in the specification.

The microprocessor 22 is externally connected with a memory device 7, and the transmission unit 6 transmits the image data to the memory device 7 for caching. A transfer unit 6 is provided at the PL side for storing image data in the memory device 7. The transmission unit 6 is configured with VDMA. VDMA is a functional module that directly transfers video data to a memory or outputs memory data as video data. VDMA (Video DMA) is a special soft core IP for carrying 'big data' such as Video and image in ZYNQ (between FPGA21 and microprocessor 22), and encapsulates three protocols of AXI. The VDMA internally comprises modules such as a control register, a status register, data handling, line buffering and the like, and communication protocols such as AXI4-Lite, AXI-Stream, AXI4 and the like at the top layer. The microprocessor 22 can complete configuration and access of a control register and a status register inside the VDMA through the AXI-Lite protocol of the top layer, and can specify how the data handling module works specifically through the configuration register, and the process of data handling needs to be buffered through the line buffer module.

An operating system is configured in the ARM processor, including but not limited to any one of the known operating systems. The memory device 7 is used to run an operating system and to cache image data. In this embodiment, the operating system may be a Linux operating system, and the ARM processor runs the test program to test the image data, so that intelligent analysis and processing of the data can be realized without large-scale electronic devices such as a computer. Preferably, the memory device 7 uses DDR4 memory banks, and transfers image data to the DDR4 memory banks for caching through VDMA. The analysis test unit 8 reads the image data cached in the memory device 7 and performs an analysis test to obtain output data. The DDR4 memory bank is mainly used for data buffering, and data loss caused by inconsistency of the sending rate and the receiving rate in a short time is prevented.

In addition, the processing module 2 is also connected with other devices, such as a visualization device, a storage module 10, and the like. Taking the storage module 10 as an example, the storage module 10 is connected to the analysis test unit 8 and is configured to store output data, where the output data includes first test data obtained by processing with the FPGA and second test data obtained by processing with the ARM. The user can access the storage module 10 to the analysis test unit 8, and after the output data is obtained, the output data can be conveniently checked at any time. The storage module 10 can be a Micro-SD card which is a small-sized, conveniently-plugged and unplugged high-capacity storage card. Taking the visualization device as an example, the visualization device can display the output data, and the user can intuitively obtain the output data.

The embodiment provides a camera module testing arrangement, need not the computer and can carry out analysis and test to image data, and the test cost is low, small and exquisite portable, easy operation, and the user can carry out analysis and test to the image data of camera module at any time. By adopting the mode of combining the FPGA and the microprocessor, the FPGA carries out early-stage testing, and the microprocessor carries out later-stage testing, so that the testing time is greatly shortened, and the testing efficiency is improved.

Example 2

The embodiment 2 of the invention discloses a control method of a camera module testing device, a specific flow chart is shown as an attached figure 2 in the specification, and the specific scheme is as follows:

a control method of a camera module testing device is applied to the camera module testing device in embodiment 1 and comprises a power module and a processing module, wherein the processing module is electrically connected with the power module. The processing module is a main image testing device and is connected with an external camera module 1. The power module provides electric energy for the processing module.

The processing module is provided with an FPGA (programmable logic gate array) and a microprocessor. The FPGA is provided with an interface unit, an early-stage test unit and a transmission unit, the microprocessor is provided with an analysis test unit, and the interface unit is connected with an external camera module. In addition, the processing module is also provided with an IIC control unit, and the analysis and test unit can be externally connected with other devices for displaying or acquiring output data.

The method comprises the following steps:

101. and carrying out initialization configuration on the camera module through the IIC control unit.

102. Receiving image data from the camera module through the interface unit;

103. the image data are subjected to early-stage testing through the early-stage testing unit to obtain first testing data, and the image data and the first testing data are transmitted to the transmission unit;

104. transmitting the image data and the first test data to a memory device for caching through a transmission unit;

105. and analyzing and testing the image data cached in the memory device through the analysis and test unit to obtain second test data, and taking the first test data and the second test data as output data.

106. And the storage module is connected with the analysis test unit and used for receiving and storing the output data.

Illustratively, the interface unit selects an MIPI CSI-2 interface. The processing module adopts a ZYNQ chip, and an FPGA (programmable gate array) and an ARM (microprocessor) are integrated on the chip. The transmission unit performs data transmission through the VDMA, the DDR4 memory bank is selected as the memory device, and the Micro-SD card is selected as the storage module.

The specific test method flow is shown in the attached figure 3 in the specification. Specifically, the camera module is initially configured through the IIC interface. After initialization is completed, the MIPI CSI-2 interface receives image data from the camera module. And (3) constructing an early-stage test unit by using the logic resources of the PL terminal to perform early-stage test, and testing parameters such as resolution, frame rate and the like of image data. And uploading the image data to DDR4 at the PS end for buffering through the VDMA. And the image analysis testing module at the PS end carries out further analysis testing on the image data. And finally, storing the obtained test result into the Micro-SD card.

The present embodiment provides a control method for a camera module testing apparatus, which is based on embodiment 1, and the apparatus of embodiment 1 is converted into a method, so that the apparatus has more practical applicability.

The invention provides a camera module testing device and a control method thereof. The device adopts FPGA and microprocessor to test the analysis to the image jointly, based on FPGA's parallel processing advantage, carries out analysis and test to some parameters when the image is received, has shortened test time, has promoted efficiency of software testing. The FPGA and the microprocessor are integrated on the circuit board, the camera module can be tested without a computer, the size is small, the operation cost is low, the operation is simple, and the defects that the camera module testing equipment in the prior art is large in size, high in cost and difficult to carry are overcome.

Those skilled in the art will appreciate that the drawings are merely schematic representations of preferred embodiments and that the blocks or flowchart illustrations are not necessary to practice the present invention. Those skilled in the art can understand that the modules in the device in the implementation scenario may be distributed in the device in the implementation scenario according to the implementation scenario description, and may also be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules. The above-mentioned serial numbers of the present invention are merely for description, and do not represent the merits of the implementation scenario. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.

Claims

1. The camera module testing device is characterized by comprising a power supply module and a processing module, wherein the processing module is electrically connected with the power supply module;

the early-stage test unit is used for carrying out early-stage tests including a resolution test and a frame rate test on the image data to obtain first test data, and transmitting the image data and the first test data to the transmission unit;

the analysis test unit is used for carrying out analysis test on the image data cached in the memory device to obtain second test data, and the first test data and the second test data are used as output data;

the resolution test specifically comprises the following steps of acquiring the line length and the column length of an image: each line tail of the image is provided with a line tail mark, and the last frame of each image is provided with a frame tail mark; every time a pixel is received, the numerical value of a preset line length counter is increased by one until the line tail identification is received; outputting the numerical value of the line length counter to obtain the line length of the image; every time one row tail identification is received, the numerical value of a preset column length counter is increased by one until the frame tail identification is received; outputting the numerical value of the column length counter to obtain the length of the image column;

the frame rate test specifically includes: within one second, adding one to the numerical value of a preset frame rate counter every time one frame tail identification is received; and outputting the value of the frame rate counter to obtain the image frame rate.

2. The camera module testing device according to claim 1, wherein an IIC control unit is further disposed on the processing module, and the IIC control unit establishes a communication connection with the camera module through IIC;

3. The camera module testing device according to claim 1 or 2, further comprising a storage module;

4. The camera module testing device of claim 1, wherein the transmission unit is configured with a VDMA;

and/or the memory device comprises a DDR4 memory bank;

5. The camera module testing device of claim 1, wherein the interface unit comprises an MIPI CSI-2 interface;

6. A control method of a camera module testing device, which is applied to the camera module testing device of claim 1, characterized in that the device comprises a processing module and a power supply module, wherein the power supply module supplies electric energy to the processing module;

the method comprises the following steps:

receiving image data from the camera module through the interface unit;

performing early tests including a resolution test and a frame rate test on the image data through the early test unit to obtain first test data, and transmitting the image data and the first test data to the transmission unit;

the analysis test unit is used for analyzing and testing the image data cached in the memory device to obtain second test data, and the first test data and the second test data are used as output data;

the resolution test specifically comprises the following steps of acquiring the line length and the column length of an image: each line tail of the image is provided with a line tail mark, and the last frame of each image is provided with a frame tail mark; every time a pixel is received, adding one to the value of a preset line length counter until the line tail identification is received; outputting the numerical value of the line length counter to obtain the line length of the image; every time one line tail mark is received, adding one to the value of a preset column length counter until the frame tail mark is received; outputting the numerical value of the column length counter to obtain the length of the image column;

7. The control method according to claim 6, wherein an IIC control unit is further arranged on the processing module, and the IIC control unit establishes communication connection with the camera module through IIC;

before receiving the image data from the camera module, the method further comprises the following steps:

8. The control method according to claim 6 or 7, further comprising a storage module connected to the analysis test unit;

after acquiring the output data, further comprising:

and receiving and storing the output data through the storage module.