CN206212146U - A kind of digital image acquisition device - Google Patents

Abstract

The utility model discloses a kind of digital image acquisition device, including master controller, CPLD, image pick-up card, usb circuit, power circuit and memory；CPLD is CPLD；CPLD, image pick-up card, usb circuit and memory are connected with master controller；Memory and image pick-up card are also connected with CPLD；The control signal end of usb circuit is connected with CPLD；Power circuit is that master controller and CPLD power；Master controller uses TMS320C6211 types DSP；Image pick-up card uses VC302 capture cards；VC302 capture cards have 8 parallel-by-bit buses of standard；CPLD uses IspLSI2064VE chips.The digital image acquisition device compact conformation, integrated level is high, it is easy to implement.

Description

A kind of digital image acquisition device

Technical field

The utility model is related to a kind of digital image acquisition device.

Background technology

With the development of computer technology, electronic technology and the communication technology, digital image acquisition, treatment technology are being calculated Application in machine and portable system is more and more extensive.For example in videophone, digital camera, DTV, picture control, photograph The occasions such as phase mobile phone, video conference are obtained for deeper application.Digitized image allows that picture signal is passed in high quality It is defeated, and it is easy to retrieval, analysis, treatment and the storage of image.But the expression of digital picture needs substantial amounts of data, due to storage Space and the limitation of the network bandwidth, store to image, first image are compressed before processing and transmitting.Even if using Various methods are compressed to view data, and its data volume is still huge, to transmission medium, transmission method and storage medium Also may require that higher.Therefore Image Compression Coding Technology study meaning is particularly significant, also just because of image compression encoding And transmission technology is continued to develop, updated, developing rapidly for current multimedia technology application has been promoted.

Existing image acquisition circuit, the subject matter for existing is, circuit is complicated, and reliability is low and design complexity etc. is asked Topic；Therefore, it is necessary to design a kind of sensitivity safety monitoring device higher.

Utility model content

Technical problem to be solved in the utility model is to provide a kind of digital image acquisition device, the digital image acquisition Apparatus structure is compact, and integrated level is high, it is easy to implement.

The technical solution of utility model is as follows：

A kind of digital image acquisition device, including master controller, CPLD, image pick-up card, usb circuit, power supply electricity Road and memory；CPLD is CPLD；

CPLD, image pick-up card, usb circuit and memory are connected with master controller；Memory and IMAQ Card is also connected with CPLD；The control signal end of usb circuit is connected with CPLD；

Power circuit is that master controller and CPLD power；

Usb circuit communicates for master controller with the host computer as acquisition platform；

Master controller uses TMS320C6211 types DSP；

Image pick-up card uses VC302 capture cards；VC302 capture cards have 8 parallel-by-bit buses of standard；

CPLD uses IspLSI2064VE chips.

Power circuit includes 3.3V power circuits and 1.8V power circuits；3.3V power circuits use LM1117-3.3 devices Part；1.8V power circuits use GS5808 devices.

Usb circuit uses PDIUSBD12 chips.

Memory includes a piece of HY57v561620T types SDRAM chips and MX29LV400B types flash memory (Flash) chip.

DSP and CPLD are the hardware module of maturation, and any software and method are not related to.

Beneficial effect：

Digital image acquisition device of the present utility model, has the characteristics that：

1. integrated level is high, compact conformation

Be integrated with DSP, image pick-up card, SDRAM, FLASH memory, usb circuit etc., make full use of bus and CPLD realizes interface communication, and interface is compact, and wiring is simple, it is easy to implement.

2. modularized design, perfect in shape and function are used

The extension of memory space is realized using SDRAM, FLASH memory, the integration of interface circuit is realized using CPLD, Using image pick-up card as image capture module, each equal modularization of functional circuit, reliability is high and easily designed.In CPLD Portion is gate circuit module, and reliability is high, fast response time.

In a word, this digital image acquisition device, simple for structure, and wiring is simple, using modularized design, perfect in shape and function, Reliability is high.

Brief description of the drawings

Fig. 1 is the overall electricity theory diagram of digital image acquisition device；

Fig. 2 is DSP and CPLD connection diagrams；

Fig. 3 is VC302 and DSP, CPLD connection diagram；

Fig. 4 is RAM and DSP, CPLD wiring diagram；

Fig. 5 is FLASH and DSP, CPLD wiring diagram；

Fig. 6 is usb circuit schematic diagram；

Fig. 7 is 3.3V power circuit principle figures；

Fig. 8 is 1.8V power circuit principle figures.

Specific embodiment

The utility model is described in further details below with reference to the drawings and specific embodiments：

Embodiment 1：Such as Fig. 1~8, a kind of digital image acquisition device, including master controller, CPLD, image pick-up card, Usb circuit, power circuit and memory；CPLD is CPLD；

CPLD, image pick-up card, usb circuit and memory are connected with master controller；Memory and IMAQ Card is also connected with CPLD；The control signal end of usb circuit is connected with CPLD；

Power circuit is that master controller and CPLD power；

Usb circuit communicates for master controller with the host computer as acquisition platform；

Master controller uses TMS320C6211 types DSP；

Image pick-up card uses VC302 capture cards；VC302 capture cards have 8 parallel-by-bit buses of standard；

CPLD uses IspLSI2064VE chips.

Power circuit includes 3.3V power circuits and 1.8V power circuits；3.3V power circuits use LM1117-3.3 devices Part；1.8V power circuits use GS5808 devices.

Usb circuit uses PDIUSBD12 chips.

Memory includes a piece of HY57v561620T types SDRAM chips and MX29LV400B types flash memory (Flash) chip.

Functions and operation principle are described separately below：

1.DSP

Because various peripheral interface circuits are more in the present system, the SECO of system is complex, and due to DSP's Universaling I/O port is few, it is necessary to expansion I/O mouthful.So system employs PLD Lattice companies The patch chip of IspLsi2064VE, the chip has 84 assignable I/O pins of user, can be with 5V, 3.3V, logic level It is mutually compatible.Its combination of transmitted postpones minimum 5.5ns, and input register setup time is very short, and with programmable speed Degree/power consumption control.The extension of I/O circuits is carried out with VHDL language programming and produce the sequential controlled peripheral circuit, electricity Road is as shown in Figure 2.

By the output control signal CE [0: 3] of DSP, (outside chip selection signal, energy, writes choosing during output for/AOE ,/AWE ,/ARE Messenger, read strobe signal) as the input signal of CPLD.Mainly each peripheral components control signal of the output of CPLD, Piece choosing including memory (program storage, data storage), video capture card, read-write, 320240 piece choosing With display control signal etc..The data exchange of image pick-up card USB2.0 and DSP (D0-D7) is also by CPLD (VD0- simultaneously VD7) carry out, to avoid directly being controlled to produce excessive latent period by DSP.

2. image pick-up card

VC302 Acquisition Circuits are cached and the group such as sequential interface and bus data circuit by Video Decoder, high speed FIFO Into it is 5V and 3.3V that VC302 capture cards can use supply voltage, can directly and dsp interface.Its data-interface is standard 8 parallel-by-bit buses, the access method carried out to it is similar with read-write random-access memory (SRAM).VC302 can support the frame of highest 25/ The picking rate of second, data/address bus setup time only 25ns.The power supply of+3.3V is used, while supporting I/O voltages, is owned These characteristics are all adapted to and are directly connected to DSP, CPLD.Fig. 3 gives image pick-up card connection diagram.

VC302 capture cards, its analog signal input can directly input PAL-system composite color video signal, or 50Hz Monochrome television signal.During input color vision signal, it is possible to use black and white drainage pattern.When black-and-white video signal is input into, Color acquisition pattern can be used, but output is still black and white.Collection can carry out four kinds of acquisition modes altogether：320× 240 black and white/colour TV signal, 640 × 240 colour signals, (black and white is 8 to 640 × 480 monochrome television signal, and colour is 16).What the design was selected is 16 colours and 8 black white images of the dot matrix of collection 320 × 240.

It is using special analog video signal decoder SAA71113, SAA71113 vision signal decoding is simulated Video Decoder is dual-channel analog pretreatment circuit, automatic clamping and many marks of gain control circuit, clock generation circuit, numeral Quasi- decoder, brightness/contrast/saturation degree control circuit, the combination of color space matrix, are at the video of a perfect in shape and function Reason device.SAA71113 only needs to single 3.3V power supplys and powers, and the I/O voltages with C6211 are consistent.It is (multiple that SAA7113 receives CVBS Close video) or the input of S-video analog videos, the colour-video signal of PAL, SECAM, NTSC pattern can be decoded as automatically CCIR-601/656 compatible colorful digital component value, device function passes through I2C Interface Controllers.So image acquisition process can be with All completed on backstage, the intervention of CPU is not needed substantially, the substantial amounts of CPU time can be saved.But so it is designed with one Difficult point：The digital video signal data amount drawn by analog video signal decoding is very big, and due to being real time video signals, So data output rate is also very high；But conversely, the read-out speed of DSP external memory interfaces is slow.To understand Certainly this problem, what this card was taken is high speed 3Mbit FIFO (data first in first out), and data are kept in alleviate speed On difference, i.e., keep in N row view data using FIFO, Video Decoder in FIFO directly to writing view data.When After N row view data is written with FIFO, interrupt requests are sent from CPLD to DSP；Meanwhile, after DSP is connected to interrupt requests, start Be read into N row view data from FIFO in its outside SDRAM and deposit by collection.So while collection, DSP can just read The N row data for having gathered are taken, without waiting frame image data collection to complete.So improve the treatment effeciency of DSP.CPLD master Control decoder that data are read from FIFO to write-in data and DSP in FIFO.System can collect a two field picture Size is 320 (point/OK) × 240 (OK), from SA71113 export be 4: 2: 2 YcrCb data forms, a pixel is with 2 Byte representation, a byte representation Y, another byte is Cb and Cr, then total data volume is 320 × 240 × 2=150KB. For luminance signal, each pixel Y accounts for a byte, a line totally 320 bytes, with 320 Y numbers of memory cell storing one row According to for carrier chrominance signal Cb, totally 320 points of a line, each two pixel shares a carrier chrominance signal Cb, accounts for a byte, totally 160 Byte, the data of a line are deposited with 160 byte units, and for carrier chrominance signal Cr, storage format is as Cb.Such frame figure As the buffer size that data need is：320 × 240+160 × 240 × 2=150KB.This is extended two panels 256K × The SDRAM of 16bit, and selected the FIFO with 3Mbit to carry out buffered data.

3. memory

The system have selected be HYNIX companies the storage limited to extend C6211 of HY57v561620T SDRAM chips Space.And a piece of Flash chip MX29LV400B extends its program storage.

The EMIF that C6211 inside has is the interface of external memory storage interior other units of its piece, with very strong interface energy Power.Its data-bus width is 32bits, and addressing space is 4GB, can directly be connect with current almost all kinds of memory Mouthful.The external bus request of EMIF treatment has EDMAExtended Direct Mernory Access controllers and outside in piece common The equipment for enjoying memory.Be to the control of EMIF by setting what the storage stack mapping register in EMIF was completed, including Each type of memory spatially is configured, corresponding interface sequence etc. is set.It is whole different when EMIF is with asynchronous device interface Step interface signal includes tetra- control signals of #AOE, #AWE, #ARE, ARDY.In SECO, by the global controls of EMIF Flexible parameter configuration is carried out in register and corresponding CEx (x is 0~3) space control register, is completed and different components Sequential interface.

Because C6211DSP is dual power supply, core voltage is 1.6V, (it is different according to different model chip, typically It is 1.5V-2.5V, I/O pins power supply is 3.3V.And the device of 5V is more in the market, it is contemplated that 3V and 5V (general peripheries Chip) Mixed Design problem, if being directly connected to, can damage dsp chip.If 3.3VDSP, CPLD processor Will be with the peripheral components interface of 5V, it is necessary to a middle plus voltage conversion chip, conventional voltage conversion chip： SN74LVCC3245, SN74LVCC4245 etc..In order to simplify circuit design and reduces cost, in this regard, memory chip RAM is used HY57v561620T.It is single electricity by being the asynchronous static RAM of high-speed cmos of the 4BANK*1MB*16bit that HYNIX companies produce Source+3.3V powers, and access speed is compatible with Transistor-Transistor Logic level up to 10ns.Full static state operation is without clock and refresh circuit.Therefore It can not need level conversion with DSP direct interfaces, centre.RAM is as shown in Figure 4 with DSP, CPLD connection diagram.

The address A0-A12 of HY57v561620T SDRAM is connected with the EA2-EA14 of DSP C6211, BA0-BA1 with The EA13-EA14 of C6211 is connected as selecting the BANK areas signal of SDRAM.Data wire D0-D15 is connected with the D0-D15 of C6211./ RAS ,/CAS connect AOE, ARE pin connection of DSP respectively, are gated as ranks and driven.DQM [3: 0] and C6211 /BE [3: 0] Connection enables signal as byte.And control signal wire/the CE of SDRAM ,/WE, LDQM, UDQM are produced by CPLD.

MX29LV400BTC is the flash of 256 × 16bit, supports the wide operating voltage range of 2.7V to 3.6V, is supported JEDEC single supply flash storage standards；The microprocessor instruction of standard need to be only write to its command register, specifically program, Whether erasing operation realized by the algorithm that is internally embedded, and can complete by inquiring about specific pin or data wire policer operation Into；Any sector can be read and write or erasing operation, the data without influenceing other parts.This chip can also be direct With DSP, CPLD interface.Its connection diagram is as shown in Figure 5.

4.USB interface circuits

PDIUSBD12 usb circuits such as Fig. 6.

Wherein the control signal of PDIUSBD12 is all produced by CPLD, including：CS (chip selection signal), RD (read strobe signal), WR (write strobe signals), EOT (DMA transfer end signal), AO (data, command selection signal).PDIUSBD12 Embeddeds 6M to 48M clock multiplication PLL, therefore outside only needs high-speed cruising by 6MHz crystal oscillators, and EMI also to decrease.

5. power circuit design

It is power and heat dissipation problem that the subject matter for considering is needed in Power Management Design.C6211 in order to reduce power consumption, using low Power voltage supply mode, and it has two kinds of power supplys：The I/O power supplys (DVDD) of+3.3V, the core power (CVDD) of+1.8V.Reduce The main purpose of core voltage is to reduce power consumption.

Current requirements：The consumption of electric current depends primarily on the activity of device, the i.e. activity of CPU.The electricity of peripheral hardware consumption Stream depends primarily on the peripheral hardware and its speed for working, and compared with CPU, the electric current of peripheral hardware consumption is smaller.Clock Sub-fraction electric current is consumed, and is constant, the degree with CPU and peripheral hardware activation is unrelated.

The maximum functional clock of TMS320C6211 is 167MHz, it is considered under the conditions of greatest limit：

Core voltage Vc=1.8V, tests electric current Ic=45mA, I/O voltage Vd=3.3V, test electric current Id=30mA.

Then institute's consumption peaks power：

Pmax=Vc × Ic+Vd × Id=1.8V × 45mA+3.3V × 30mA=180mW

Thus general power supply can meet its power requirement.

In addition, DSP is required for the upper electric order of two kinds of voltages.Ideally the core voltage Vc of power supply should be first In electricity on I/O voltages Vd, Vc should be later than I/O voltages Vd power-off during shut-off.The reason for so requiring is, if Vc is prior on Vd Electricity, simply chip perimeter input and output are invalid, do not damaged in itself for chip, but if order is conversely, the then buffering of chip A unknown state will be in drive part, easily chip is caused damage.

Other devices such as CPLD, RAM, FLASH and image pick-up card etc. are 3.3V devices, so the system provides total 3 road DC voltages are provided altogether.Input power is the direct-flow steady voltage of+5V, by 3.3 power conversion chips, is respectively supplied to The core voltage 1.8V of DSP, CPLD, RAM, FLASH, the 3.3V required for image pick-up card, and C6211.The system is used Two panels voltage conversion chip is designed, LM1117-3.3 (3.3V voltage conversions) and GS5808 (1.8V voltage conversions), its design electricity Road such as Fig. 7, Fig. 8.

Claims (4)

1. a kind of digital image acquisition device, it is characterised in that including master controller, CPLD, image pick-up card, USB interface electricity Road, power circuit and memory；CPLD is CPLD；

CPLD, image pick-up card, usb circuit and memory are connected with master controller；Memory and image pick-up card are also It is connected with CPLD；The control signal end of usb circuit is connected with CPLD；

Power circuit is that master controller and CPLD power；

Master controller uses TMS320C6211 types DSP；

Image pick-up card uses VC302 capture cards；VC302 capture cards have 8 parallel-by-bit buses of standard；

CPLD uses IspLSI2064VE chips.

2. digital image acquisition device according to claim 1, it is characterised in that power circuit includes 3.3V power circuits With 1.8V power circuits；3.3V power circuits use LM1117-3.3 devices；1.8V power circuits use GS5808 devices.

3. described digital image acquisition device according to claim 2, it is characterised in that usb circuit is used PDIUSBD12 chips.

4. the digital image acquisition device according to claim any one of 1-3, it is characterised in that memory includes a piece of HY57v561620T type SDRAM chips and MX29LV400B type flash chips.