CN207233743U - 超结金属氧化物半导体场效晶体管 - Google Patents

超结金属氧化物半导体场效晶体管 Download PDF

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CN207233743U
CN207233743U CN201720808516.8U CN201720808516U CN207233743U CN 207233743 U CN207233743 U CN 207233743U CN 201720808516 U CN201720808516 U CN 201720808516U CN 207233743 U CN207233743 U CN 207233743U
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epitaxial layer
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金荣锡
金范锡
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DB HiTek Co Ltd
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Abstract

超结金属氧化物半导体场效晶体管包括：具有第一导电类型的衬底；在衬底上形成的外延层，该外延层具有第一导电类型；在外延层中沿垂直方向延伸的柱，该柱彼此分隔开；第二导电类型的第一阱，其在外延层中形成以延伸至外延层的上表面，每个第一阱连接至每个柱的上部；第一导电类型的第二阱，其在第一阱中形成；和在外延层上形成的多个栅极结构，每个栅极结构沿第一方向延伸以具有条形形状，使得栅极结构彼此分隔开。因此，栅极结构具有相对小的面积以减小超结金属氧化物半导体场效晶体管的输入电容。

Description

超结金属氧化物半导体场效晶体管
技术领域
本发明涉及金属氧化物半导体场效晶体管(以下称 MOSFET)，且更具体地，涉及超结MOSFET。
背景技术
一般而言，超结结构被广泛用于改善功率半导体器件击穿电压的正向特性和反向特性之间的权衡关系。
根据现有技术，超结MOSFET的柱和栅结构具有相同的布局。布局的示范例包括线性阵列、正方形阵列、六边形阵列等。
导通电阻Rsp与有源区中柱占据的面积成比例地增加。输入电容也与栅结构占用的面积成比例地增加。柱的面积以线性阵列、正方形阵列和六边形阵列的顺序减少。栅结构的面积随着线性阵列、正方形阵列和六边形阵列的顺序而增加。
因此，当柱和栅结构的布局是线性的时，导通电阻由于柱的相对大的面积而增大，但是输入电容由于栅极结构的相对小的面积而减小。
与此同时，当柱和栅结构的布局是六边形的时，导通电阻由于柱的相对小的面积而减小，但是栅极电容由于栅极结构的相对大的面积而增大。
因此，需要一种可同时减小导通电阻以及输入电容的柱和栅布局。
发明内容
本发明的示范实施例提供了能够同时降低导通电阻以及输入电容的超结金属氧化物半导体场效晶体管。
根据本发明的一示范实施例，超结金属氧化物半导体场效晶体管包括：衬底，其具有第一导电类型；外延层，其在衬底上形成，外延层具有第一导电类型；多个柱，其沿与外延层垂直的方向延伸，柱之间彼此分隔开；具有第二导电类型的多个第一阱，其在外延层中形成以延伸至外延层上表面，每个第一阱与每一柱的上部相连；具有第一导电类型的多个第二阱，其在第一阱中形成；以及在外延层上形成的多个栅极结构，每个栅极结构沿第一方向延伸以形成条形，使得栅极结构彼此分隔开。
在一示范实施例中，每个柱可具有六边形且柱沿第一方向设置呈蛇形。
在一示范实施例中，从平面图来看每个栅极结构可在柱之间延伸。
在一示范实施例中，每一柱可具有六边形，且柱可沿与第一方向垂直的第二方向设置呈蛇形。
在此，从平面图来看每个栅极结构可在第一行中设置的某些柱之间且在与第一行相邻的第二行中设置的其它柱之上延伸。
此外，某些柱可在外延层中形成，且可与第一阱和栅极结构分隔开。
在一示范实施例中，每个柱具有六边形、圆形和矩形截面形状中的一种。
在一示范实施例中，每个栅极结构可包括在外延层上形成的栅极绝缘层、在栅极绝缘层上形成的栅电极以及围绕栅电极的绝缘夹层。
在一示范实施例中，每个栅极结构可具有沟槽结构。
根据本发明一示范实施例，超结金属氧化物半导体场效晶体管通过以下步骤制备：在第一导电类型的衬底上形成具有第一导电类型的外延层；在外延层上形成具有第二导电类型的多个柱，其中柱沿垂直方向延伸以彼此分隔开；在外延层上形成初始的栅极绝缘层，多个柱在该绝缘层上形成；在初始栅极绝缘层上形成栅电极以暴露出初始绝缘层的一部分，每一个均具有条形形状并沿第一方向延伸；使用栅电极作为掩模将第二导电类型的杂质注入填充物的上部以形成第一阱；将第一导电类型的杂质注入第一阱以形成第二阱，第二阱用作源区；形成初始绝缘夹层以覆盖栅电极和初始栅极绝缘层的暴露部分；且部分蚀刻初始绝缘夹层和初始栅极绝缘层直至第一阱的上表面暴露以形成包括栅极绝缘层、栅电极和绝缘夹层的栅极结构。
在一示范实施例中，每一柱可具有六边形形状且柱可设置成沿第一方向呈蛇形，且从平面图来看每一栅极结构可在柱之间延伸。
在一示范实施例中，每一柱可具有六边形形状且柱可设置成沿与第一方向垂直的第二方向呈蛇形，且从平面图来看每个栅极结构在第一行中设置的某些柱之间且在与第一行相邻的第二行中设置的其它柱之上延伸。
在一示范实施例中，某些柱可在外延层中形成，且与第一阱和栅极结构分隔开，且其他柱的上部可选择性地连接第一阱。
在一示范实施例中，每一柱可形成六边形、圆形和矩形截面形状中的一种。
在一示范实施例中，每一栅极结构可具有平面结构。
在一示范实施例中，每一栅极结构可具有沟槽结构。
根据超结MOSFET及制备超结MOSFET的方法的示范实施例，柱设置呈六边形以最小化超结MOSFET的面积。因此，超结MOSFET的导通电阻可通过最小化柱的面积而减小。
此外，由于每个栅极结构向一个方向延伸而呈条状，栅极结构相对较小，使得超结MOSFET的输入电容可被减小。
因此，超结MOSFET可以具有低值的导通电阻以及相对低值的输入电容。
附图说明
从以下参照附图的说明可更详细地理解示范实施例，其中附图如下：
图1是显示根据本发明一示范实施例的超结MOSFET的立体图；
图2是显示图1中的柱和栅极结构的布局的平面图；
图3是显示根据本发明一示范实施例的超结MOSFET的立体图；
图4是显示图3中的柱和栅极结构的布局的平面图；且
图5-11是显示根据本发明一示范实施例的超结MOSFET的制备方法的截面图。
具体实施方式
以下参照附图更详细地说明具体实施例。然而，本发明可以以不同的形式实施且不应解释为局限于本文提出的实施例。
作为本申请中使用的明确定义，当提及层、薄膜、区域或板在另一个“之上”时，它可以直接在另一个之上，或者也可以存在一个或多个介于其间的层、薄膜、区域或板。与此不同，也应当认识到，当提及层、薄膜、区域或板“直接在另一个之上”时，它直接在另一个之上，并且不存在一个或多个介于其间的层、薄膜、区域或板。而且，尽管使用了像是第一、第二和第三的术语来描述不同的组件，但本发明的各个实施例中的组分、区域和层并不局限于这些术语。
此外，仅处于描述的便利，元素可被指位于彼此“之上”或
“之下”。将理解，上述描述是指所述的附图上显示的方向，且在各种使用和替代实施例中这些元素可能被翻转或转置成替代性设置和结构。
在以下描述中，技术术语仅用于解释具体实施例，而不是限制本发明的范围。除非在本文中另外定义，否则本文中使用的所有术语，包括技术或科技术语，可具有与本领域技术人员通常理解的相同的含义。
参照本发明理想的实施例的示意图来描述请求保护的本发明的实施例。于是，图形形状的变化，例如，制造工艺和/或容许误差的变化，是充分预期的。于是，本发明的实施例不会描述成局限于用图形描述的区域的具体形状，而是包括形状的偏差，并且附图描绘的区域也是完全示意的，他们的形状并不代表准确的形状，也不限制本发明的范围。
图1是显示根据本发明一示范实施例的超结MOSFET的立体图。图2是显示图1中的柱和栅极结构的布局的平面图。
参照图1和2，根据本发明一示范实施例的超结MOSFET100包括衬底110、外延层120、柱130、第一阱140、第二阱150、栅极结构160、源电极170和漏电极180。
衬底110可包括硅衬底且具有第一导电类型，例如，高浓度n+型。
外延层120在衬底110上形成且具有第一导电类型，例如，低浓度n-型。外延层120可通过外延生长工艺形成。
柱130设置在外延层120里面沿垂直方向延伸。柱130具有第二导电型，例如，p-型。柱130在水平方向上以预定的距离彼此分开。例如，每个柱130具有六边形的横截面形状，其如图2所示的方式设置。当具有六边形形状的柱130被设置时，柱130在外延层120中占据的面积可最小化。因此，超结MOSFET100的导通电阻可通过最小化柱130的面积而减小。
此外，每个柱130的横截面形状可不同。例如，每个柱130的横截面形状是图1和2中所示的六边形。替代性地，每个柱130的横截面形状是矩形或圆形。
p-型导电型的柱130设置在n-型导电型的外延层120中以形成超结结构。当反向电压施加在超结MOSFET100上时，电场沿与每个柱130和外延层120之间的结合面(即，PN结合面)平行的方向形成，使得电场具有多边形柱形形状，以扩大电场区域的面积。因此，通过调整流经柱130和外延层120的电量，外延层120可完全转换成耗尽区。因此，根据一示范实施例的超结MOSFET100可保持与传统MOSFET基本相同的击穿电压值，尽管外延层120的掺杂浓度高于在传统MOSFET中形成的外延层的掺杂浓度。
第一阱140在外延层120上部的预定深度形成且沿第一方向延伸。第一阱140彼此分隔开。第一阱140分别连接至外延层120中柱130的上部。每一第一阱140具有第二导电类型，如p-型。
第二阱150分别位于第一阱140内。例如，第二阱150可设置在第一阱140上部的预定深度。每个第二阱150具有第一导电类型，如高浓度n+型。
同时，尽管未示出，第二导电类型(例如，高浓度p+型)的第三阱可定位在处于第一阱140内的一对第二阱150之间。
栅极结构160位于外延层120上。每个栅极结构160沿第一方向延伸以具有条形形状，使得栅极结构160彼此分隔开。栅极结构160定位在柱130上，每一个均为六边形。
由于每个栅极结构160为条状，栅极结构160具有相对小的面积，以使超结MOSFET100的输入电容可减小。
在一示范实施例中，每一栅极结构160包括栅极绝缘层162、栅电极164和绝缘夹层166。
栅极绝缘层162设置在外延层120上。栅极绝缘层162在柱130 之间延伸以彼此分隔开。例如，栅极绝缘层162形成为部分覆盖第二阱150，其每一个位于不同的每一第一阱140中且彼此相邻。也就是说，栅极绝缘层 162的宽度可与分别位于不同的第一阱140中的第二阱150之间的距离大致相同，且彼此相邻。栅极绝缘层162可包括氧化物。
栅电极164位于栅极绝缘层162上。栅电极164的宽度可窄于栅极绝缘层162的宽度。例如，栅电极164可包括多晶硅。
绝缘夹层166布置在栅电极164上以围绕栅电极164。绝缘夹层 166将栅电极164和源电极170彼此电绝缘。绝缘夹层166可包括氮化层。
在一示范实施例中，尽管未示出，栅极结构160可具有沟槽结构。在此情况下，栅极结构160在外延层120内形成以沿第一方向延伸。
具体地，沟槽在外延层120中以特定的深度形成。栅极绝缘层 162沿沟槽的内壁设置以在彼此相邻的柱130的上部延伸。例如，栅极绝缘层 162具有大致为U形的截面形状。也就是说，栅极绝缘层162形成为在彼此相邻的第一阱140之间沿第一方向延伸。栅极绝缘层162使位于不同的第一阱 140中且彼此相邻的第二阱150相接触。
栅电极164设置在栅极绝缘层162上，以部分填充在外延层120 中形成的沟槽。
绝缘夹层166设置为覆盖栅极绝缘层162和栅电极164。
当栅极结构160具有沟槽结构时，柱130之间的间隔可减少，且超结MOSFET100可通过增强超结MOSFET100的集成性来提高其正向特性。
源电极170在外延层120上形成以覆盖栅极结构160。源电极170电连接至第二阱150，其可用作源区。
漏电极180在衬底110的下表面上形成。当超结MOSFET100开启时，电子从作为源区的第二阱150中注出并通过在第一阱140中形成的通道随后穿过外延层120注入至漏电极180。因此，产生电流。
根据超结MOSFET100的一示范实施例，每个具有六边形的柱 130被设置且每个具有条形形状的栅极结构160延伸使得超结MOSFET100可减小导通电阻值且可降低输入电容值。
图3是显示根据本发明一示范实施例的超结MOSFET的立体图。图4是显示图3中的柱和栅极结构的布局的平面图。
参照图3和4，栅极结构160位于外延层120上且每一栅极结构160具有沿与第一方向垂直的第二方向延伸的条形形状。此外，栅极结构160 彼此分隔开。具体地，某些柱130沿第二方向布置以形成第一行柱130，同时其他柱130沿第二方向布置以形成与第一行相邻的第二行柱130。栅极结构 160在某些柱130之间延伸并且延伸到其他柱130之上。
位于栅极结构160之下的某些柱130被定位在外延层120中且与栅极结构160分隔开。此外，某些柱130未连接至第一阱140。也就是说，某些柱130可保持漂浮状态。
与此同时，位于栅极结构160之下的其他柱130可连接至第一阱140。
图5-10是显示根据本发明一示范实施例的超结MOSFET的制备方法的横截面图。
参照图5，第一导电类型(例如，低浓度n型)的外延层120在第一导电类型(例如，高浓度n+型)的衬底110上形成。外延层120可通过在衬底110上执行外延生长工艺来形成。
参照图6，在第一掩模图案(未示出)在外延层120的上表面上形成之后，使用第一掩模图案作为蚀刻掩模执行蚀刻工艺以在外延层中形成沟槽122，沟槽122用于形成柱130(见图7)。第一掩模图案可使用光致抗蚀剂来形成。
沟槽122在水平方向上彼此分隔开预定的距离。例如，每个沟槽122具有六边形横截面。替代性地，每个沟槽122可具有多种横截面形状。例如，每个沟槽122具有正方形或圆形横截面。
第一掩模图案可在形成沟槽122之后移除。
参照图7，在第二掩模图案在除去沟槽122的外延层120的上表面上形成之后，第二导电类型(例如，p-型)杂质被植入通过沟槽122暴露出的衬底110的下部。第二掩模图案可使用氧化物形成，且硼(B)离子可用作p型杂质。
在第二掩模图案被移除后，进行外延工艺以形成沟槽122内以及外延层120上的填充层，且随后，进行抛光一部分填充层的CMP(化学机械抛光)工艺以暴露出外延层120的上表面，以上构成沟槽填充工艺的一个循环。沟槽填充工艺被重复进行以填充沟槽122以在沟槽120中形成柱130。
柱130通过生长植入衬底110下部的第二导电类型(如p-型)
杂质来填充沟槽122。因此，柱130沿垂直方向延伸以在外延层120中具有第二导电类型。
此外，柱130在水平方向上彼此分隔开预定的距离。每个柱130 可具有六边形形状。当具有六边形形状的柱130被设置时，占据外延层120 的柱130的面积被最小化。于是，柱130的面积可被最小化，由此减小超结 MOSFET100的导通电阻Rsp。
每个柱130可具有多种横截面形状。例如，每个柱130的横截面形状是六边形、矩形或圆形。
参照图8，初始栅极绝缘层161在其中有柱130形成的外延层 120上形成，且随后用于形成栅电极的多晶硅层(未示出)在初始栅极绝缘层 161上形成。例如，初始栅极绝缘层使用氧化物形成。
多晶硅层通过光刻工艺图案化以在初始栅极绝缘层161上形成栅电极164。每个栅电极164可具有条形形状以沿第一方向延伸。
在一示范例中，当从平面图来看时，每个栅电极164可定位在柱130之间。
在另一示范例中，每个栅电极164可形成在某些柱130之间且在形成在其他柱130之上。
另一方面，当栅电极160具有沟槽结构而不是以上所述的平面结构时，具有沿第一方向延伸的特定深度的沟槽在外延层120的上部形成。
在一示范例中，当从平面图来看时，沟槽可定位为在柱130之间延伸。
在另一示范例中，当从平面图来看时，沟槽可定位在某些柱130 之间且在其他柱130之上。在此情况下，某些沟槽未连接至柱130。
初始栅极绝缘层161在柱130所形成的外延层120的上表面上以及在沟槽的内壁上形成。
多晶硅层被形成以填充其中有初始栅极绝缘层162形成的沟槽，且随后，多晶硅层被部分蚀刻以暴露位于沟槽之外的初始栅极绝缘层161 的一部分，以使栅电极164被形成以填充沟槽。
参考图9，第一阱140通过使用栅电极164作为掩模在柱130的上部区域植入第二导电类型(如p-型)的杂质而形成。
当每个栅电极164被定位在柱130之间时，柱130定位在栅电极164之间，且第一阱140在柱130的上部形成，以使第一阱140与所有的柱130连接。
如果栅电极164在某些柱130之间以及其他柱130之上延伸，当从平面图看时，某些柱130位于栅电极164之间而其他柱130位于栅电极 164之下。因此，第一阱140可在某些柱130的上部形成，但第一阱140不可在其他柱130的上部形成。
接下来，第一导电类型(例如，高浓度n+型)杂质被植入第一阱140中以形成用作源区的至少一个第二阱150。同时，至少一个第二阱150 可在每个第一阱140中形成且可使用掩模图案来形成。例如，两个第二阱150 可在每一第一阱140中成对地形成。
参照图10，初始绝缘夹层(未示出)被形成以覆盖栅电极164 和初始栅极绝缘层161的暴露部分。例如，初始绝缘夹层使用氮化物形成。在形成初始绝缘夹层165之后，第二导电类型(例如，高浓度p+型)的杂质被进一步植入到成对的第二阱150之间以形成第三阱。
然后，初始绝缘夹层和初始栅极绝缘层161通过光刻工艺被部分蚀刻以形成绝缘夹层166和栅极绝缘层162。因此，可形成具有栅极绝缘层 162、栅电极164和绝缘夹层166的栅极结构160。
由于每个栅电极164具有沿一个方向延伸的条形形状且在柱130 之上以及在柱130之间延伸，每个栅极结构160也具有条形形状，在柱130 上沿一个方向延伸。
由于每个栅极结构160具有条形形状，栅极结构160具有相对小的面积，使得超结MOSFET的输入电容被减小。
此外，初始绝缘夹层和初始栅极绝缘层161被部分蚀刻以暴露第一阱140的上表面。
参照图11，第一金属层在外延层120上形成以覆盖栅极结构 160，使得形成源电极170。源电极170可与用作源区的第二阱150电接触。
此外，第二金属层在衬底110的下表面上形成以形成漏电极 180。
由于超结MOSFET100中包括的柱130被布置，每一个均为六边形形状，且每个栅极结构160具有条形形状，根据本发明的示范实施例的超结MOSFET100可减少导通电阻以及输入电容值。
如上所述，根据本发明的示范实施例中的超结MOSFET及制备方法，柱被布置，每个均具有六边形形状以使超结MOSFET的导通电阻可通过最小化填充物的面积来减小。由于每个栅极结构具有条形形状以沿一个方向延伸，栅极结构的面积相对很小，使得超结MOSFET的输入电容可被减小。
在降低超结MOSFET的导通电阻的同时输入电容可被减小，使得超结MOSFET的性能被改善。
尽管超结MOSFET是参照具体实施例来描述的，其并不限于所述实施例。因此，本领域的技术人员很容易理解，可对本发明作出各种修改和变化而不背离所附权利要求的实质和范围。

Claims (9)

1.超结金属氧化物半导体场效晶体管，包括：
衬底，其具有第一导电类型；
外延层，其在所述衬底上形成，所述外延层具有所述第一导电类型；
多个柱，其在所述外延层中沿垂直方向延伸，所述柱彼此分隔开；
多个第一阱，其具有第二导电类型，在所述外延层中形成以延伸至所述外延层的上表面，每个所述第一阱分别连接至所述柱的上部；
多个第二阱，其具有第一导电类型，在所述第一阱中形成；和
多个栅极结构，其在所述外延层上形成，每个所述栅极结构沿第一方向延伸以具有条形形状，使得所述栅极结构彼此分隔开。
2.如权利要求1中所述的超结金属氧化物半导体场效晶体管，其中每个所述柱具有六边形且所述柱沿所述第一方向设置呈蛇形。
3.如权利要求2中所述的超结金属氧化物半导体场效晶体管，其中当从平面图来看时，每个所述栅极结构在所述柱之间延伸。
4.如权利要求1中所述的超结金属氧化物半导体场效晶体管，其中每个所述柱具有六边形形状且所述柱沿与所述第一方向垂直的第二方向设置呈蛇形。
5.如权利要求4中所述的超结金属氧化物半导体场效晶体管，当从平面图来看时，其中每个所述栅极结构在第一行中某些所述柱之间延伸，且在与所述第一行相邻的第二行中的其他所述柱之上延伸。
6.如权利要求4中所述的超结金属氧化物半导体场效晶体管，其中所述某些所述柱在所述外延层中形成，且与所述第一阱和所述栅极结构分隔开。
7.如权利要求1中所述的超结金属氧化物半导体场效晶体管，其中每个所述柱具有六边形、圆形和矩形截面形状中的一种。
8.如权利要求1中所述的超结金属氧化物半导体场效晶体管，其中每个所述栅极结构包括：
栅极绝缘层，其在所述外延层上形成；
栅电极，其在所述栅极绝缘层上形成；和
绝缘夹层，其围绕所述栅电极。
9.如权利要求1中所述的超结金属氧化物半导体场效晶体管，其中每一所述栅极结构具有沟槽结构。
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