CN207233740U - It is a kind of silicon-controlled with channel cutoff ring - Google Patents
It is a kind of silicon-controlled with channel cutoff ring Download PDFInfo
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- CN207233740U CN207233740U CN201721251978.0U CN201721251978U CN207233740U CN 207233740 U CN207233740 U CN 207233740U CN 201721251978 U CN201721251978 U CN 201721251978U CN 207233740 U CN207233740 U CN 207233740U
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Abstract
The utility model discloses a kind of silicon-controlled with channel cutoff ring, including N-type semiconductor matrix, p-type base, P+ type isolation diffusion area, groove, N+ types cathodic region, channel cutoff ring and metal electrode；Channel cutoff ring can be that P+ type channel cutoff ring can also be N+ type channel cutoff rings.Silicon-controlled manufacturing step with P+ type channel cutoff ring includes：Silicon chip twin polishing, oxidation, break-through photoetching, break-through diffusion, the diffusion of short base, cut-off ring photoetching, the diffusion of cut-off ring, cathode photoetching, phosphorus diffusion, trench lithography, trench etching, groove passivation, fairlead photoetching, evaporation of aluminum, aluminium anti-carve, aluminium alloy, back metal.The utility model between gate pole and cathode by being provided with a channel cutoff ring, channel cutoff ring can prevent the adverse effect that the positive charge in the oxide layer between cathode and gate pole produces silicon controlled trigger current, the stability of silicon controlled trigger current is improved, and then improves the silicon-controlled reliability used.
Description
Technical field
The utility model belongs to power semiconductor device technology field, is related to a kind of controllable with channel cutoff ring
Silicon.
Background technology
It is silicon-controlled, it is the abbreviation of silicon controlled rectifier, there is the features such as small, structure is relatively easy, strong, be
One of more commonly used semiconductor devices.The device is widely used in various electronic equipments and electronic product, be used for making more
Controlled rectification, inversion, pressure regulation, noncontacting switch etc..Desk lamp with dimmer switch, speed-regulating fan, air conditioner, TV in household electrical appliance
Mechanical, electrical refrigerator, washing machine, combination audio, timing controller, toy apparatus, wireless remotecontrol, video camera and Industry Control etc. are all
Largely silicon-controlled device is used.
Trigger current is a silicon-controlled important parameter, and in actual production process, silicon-controlled trigger current is
It is produced from it what technique accurately controlled, to meet the requirement of client, but many factors can all influence to touch in process of production
Generate electricity the size flowed, for example the positive charge assembled in oxide layer can increase trigger current, and Oxide trapped charge can to micro-touch hair style
The influence for controlling silicon is very big.
Utility model content
It is provided by the utility model a kind of silicon-controlled with channel cutoff ring, it is therefore an objective to reduce in silicon-controlled manufacturing process
Influence of the positive charge formed in middle oxide layer to silicon controlled trigger current, has manufacturing process simple, the characteristics of being easy to implement.
The purpose of this utility model can be achieved through the following technical solutions：
It is a kind of silicon-controlled with channel cutoff ring, including N-type semiconductor matrix, two above and below N-type semiconductor matrix
The p-type base of side, positioned at the P+ type isolation diffusion area of N-type semiconductor matrix both sides, the ditch positioned at N-type semiconductor matrix upper surface
Groove, the N+ types cathodic region in the p-type base of upside, the gate pole between N+ types cathodic region 4, positioned at N+ types cathodic region and gate pole
Between channel cutoff ring, and the anode metal electrodes A positioned at downside p-type base region surface, the gate pole positioned at gate pole upper surface
The cathodic metal electrode K of metal electrode G and N+ type cathodic region upper surface.
Further, the channel cutoff ring is P+ type channel cutoff ring or N+ type channel cutoff rings.
The beneficial effects of the utility model：
The utility model can prevent cathode by being provided with a channel cutoff ring, channel cutoff ring between gate pole and cathode
The adverse effect that the positive charge in oxide layer between gate pole produces silicon controlled trigger current, improves silicon controlled trigger current
Stability, and then improve the reliability used, have technique simple, the characteristics of being easy to implement.
Brief description of the drawings
In order to illustrate more clearly of the technical solution of the utility model embodiment, make required for being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the utility model,
For those of ordinary skill in the art, without creative efforts, can also be obtained according to these attached drawings
Other attached drawings.
Fig. 1 is a kind of silicon-controlled planar structure schematic diagram with channel cutoff ring of the utility model；
Fig. 2 is the SCR structure schematic diagram of the corresponding P+ type channel cutoff ring of embodiment 1 in the utility model；
Fig. 3 is the SCR structure schematic diagram of the corresponding N+ types channel cutoff ring of embodiment 2 in the utility model；
In attached drawing, parts list represented by the reference numerals is as follows：
1- channel cutoff rings, 2- gate poles, 3- grooves, 4-N+ types cathodic region.
Embodiment
The following is a combination of the drawings in the embodiments of the present utility model, and the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are without creative efforts
The all other embodiment obtained, shall fall within the protection scope of the present invention.
Please refer to Fig.1 shown in -3, the utility model has the silicon-controlled of channel cutoff ring, including N-type semiconductor to be a kind of
Matrix, the p-type base of both sides above and below N-type semiconductor matrix, the P+ type isolation diffusion positioned at N-type semiconductor matrix both sides
Area, the groove 3 positioned at N-type semiconductor matrix upper surface, the N+ types cathodic region 4 in the p-type base of upside, positioned at N+ type cathodes
Gate pole 2 between area 4, the channel cutoff ring 1 between N+ types cathodic region and gate pole 2, and positioned at downside p-type base region surface
Anode metal electrodes A, the cathodic metal electrode positioned at 4 upper surface of gate metal electrode G and N+ type cathodic region of 2 upper surface of gate pole
K。
Embodiment 1
It is a kind of with channel cutoff ring it is silicon-controlled in, the channel cutoff ring 1 is P+ type channel cutoff ring.
For the silicon-controlled manufacture method of P+ type channel cutoff ring, comprise the following steps：
S1, substrate material prepare：Select N-type silicon single crystal flake, it is desirable to which electricalresistivityρ is 30~50 Ω cm, to selected N-type silicon
Single-chip twin polishing, piece thickness is 220~230 μm after throwing；
S2, oxidation：Silicon chip after throwing is aoxidized, oxidizing temperature is 1150 DEG C, and time 5h, oxidated layer thickness is at least
1.2μm；
S3, break-through photoetching：Silicon chip obverse and reverse sides after oxidation are coated into photoresist using sol evenning machine, at a temperature of 105 DEG C
The front baking of 25min is carried out, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out break-through window, then removes photoresist, clearly
Wash, dry；
S4, break-through diffusion：Boron pre-deposition is used first, and the temperature of pre-expansion is 1070 DEG C, diffusion time 180min, it is desirable to
R□=3~5 Ω/；Temperature when then carrying out break-through boron again to expand, then spreading is 1270 DEG C, diffusion time 140h；
S5, the diffusion of short base：Carry out light boron pre-deposition first, the temperature of pre-expansion is 1000 DEG C, diffusion time 60-
120min, it is desirable to R□=40~55 Ω/；Then carry out light boron again to expand, then expand temperature as 1250 DEG C, then it is 25h to expand the time；
S6, cut-off ring photoetching：Silicon chip obverse and reverse sides are coated into photoresist using sol evenning machine, are carried out at a temperature of 105 DEG C
The front baking of 25min, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out to end ring window, then removes photoresist, clearly
Wash, dry；
S7, P+ cut-off ring diffusion：Carry out light boron pre-deposition first, the temperature of pre-expansion is 1050 DEG C, diffusion time 30-
60min, it is desirable to R□=8~10 Ω/；Then carry out light boron again to expand, then it is 1150 DEG C to expand temperature, diffusion time 1-3h；
S8, cathodic region photoetching：Silicon chip obverse and reverse sides are coated into photoresist using sol evenning machine, are carried out at a temperature of 105 DEG C
The front baking of 25min, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out cathodic region window, then removes photoresist, clearly
Wash, dry；
S9, phosphorus diffusion：Phosphorus pre-deposited is carried out first, and the temperature of pre-expansion is 1050 DEG C, diffusion time 120-200min,
Seek R□=0.8~1 Ω/；Then phosphorus is carried out again to expand, then T=1200 DEG C of the temperature expanded, then the time expanded is 90-120min；
S10, trench lithography：Silicon chip obverse and reverse sides are coated into photoresist using sol evenning machine, are carried out at a temperature of 105 DEG C
The front baking of 25min, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out trench openings, then removes photoresist, and cleans,
Drying；
S11, trench etching：Trench etching is carried out to silicon chip using the silicon etch solution configured, it is desirable to 60-70 μm of groove depth；
S12, groove passivation：Groove, then high temperature sintering are scraped to fill using the glass paste configured；
S13, fairlead photoetching：Front side of silicon wafer is coated into photoresist using sol evenning machine, is carried out at a temperature of 105 DEG C
The front baking of 25min, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosive liquid corrodes in front side of silicon wafer lead window, at the same time
Silicon chip back side oxide layer corrosion is clean, then remove photoresist, clean, drying；
S14, evaporation of aluminum：It is 4.0~5.0 μm to ensure aluminum layer thickness.
S15, aluminium anti-carve：Reticle progress aluminium is anti-carved using aluminium to anti-carve.
S16, aluminium alloy：Condition is 450 DEG C of temperature, time 20min；
S17, back metal：Ti-Ni-Ag three-layer metals are evaporated at the back side, and thickness is respectively
Embodiment 2
It is a kind of with channel cutoff ring it is silicon-controlled in, the channel cutoff ring 1 is N+ type channel cutoff rings.
For the silicon-controlled manufacture method of N+ type channel cutoff rings, comprise the following steps：
S1, substrate material prepare：Select N-type silicon single crystal flake, it is desirable to which electricalresistivityρ is 30~50 Ω cm, to selected N-type silicon
Single-chip carries out twin polishing, and piece thickness is 220~230 μm after throwing；
S2, oxidation：Silicon chip after throwing is aoxidized, oxidizing temperature is 1150 DEG C, time 5h, it is desirable to the oxidation thickness of growth
Spend for 1.2 μm.
S3, break-through photoetching：Silicon chip obverse and reverse sides after oxidation are coated into photoresist using sol evenning machine, at a temperature of 105 DEG C
The front baking of 25min is carried out, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out break-through window, then removes photoresist, clearly
Wash, dry；
S4, break-through diffusion：Boron pre-deposition is carried out first, and the temperature of pre-expansion is 1070 DEG C, diffusion time 180min, it is desirable to
R□=3~5 Ω/；Temperature when then carrying out break-through boron again to expand, then spreading is 1270 DEG C, diffusion time 140h；
S5, the diffusion of short base：Carry out light boron pre-deposition first, the temperature of pre-expansion is 1000 DEG C, diffusion time 60-
120min, it is desirable to R□=40~55 Ω/；Then carry out light boron again to expand, then expand temperature as 1250 DEG C, then it is 25h to expand the time；
S6, cathodic region and cut-off ring photoetching：Silicon chip obverse and reverse sides are coated into photoresist using sol evenning machine, in 105 DEG C of temperature
The lower front baking for carrying out 25min of degree, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out cathodic region and cut-off ring window
Mouthful, then remove photoresist, clean, drying；
S7, phosphorus diffusion：Phosphorus pre-deposited is carried out first, and the temperature of pre-expansion is 1050 DEG C, diffusion time 120-200min,
Seek R□=0.8~1 Ω/；Then phosphorus is carried out again to expand, then T=1200 DEG C of the temperature expanded, then the time expanded is 90-120min；
S8, trench lithography：Silicon chip obverse and reverse sides are coated into photoresist using sol evenning machine, are carried out at a temperature of 105 DEG C
The front baking of 25min, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosion corrosion goes out trench openings, then removes photoresist, and cleans,
Drying；
S9, trench etching：Trench etching is carried out to silicon chip using the silicon etch solution configured, it is desirable to 60-70 μm of groove depth；
S10, groove passivation：Groove, then high temperature sintering are scraped to fill using the glass paste configured.
S11, fairlead photoetching：Front side of silicon wafer is coated into photoresist using sol evenning machine, is carried out at a temperature of 105 DEG C
The front baking of 25min, photo-etching machine exposal, development, post bake, utilizes SiO2Corrosive liquid corrodes in front side of silicon wafer lead window, at the same time
Silicon chip back side oxide layer corrosion is clean, then remove photoresist, clean, drying；
S12, evaporation of aluminum：It is 4.0~5.0 μm to ensure aluminum layer thickness；
S13, aluminium anti-carve：Reticle progress aluminium is anti-carved using aluminium to anti-carve；
S14, aluminium alloy：Condition is 450 DEG C of temperature, time 20min；
S15, back metal：Ti-Ni-Ag three-layer metals are evaporated at the back side, and thickness is respectively
The utility model can prevent cathode by being provided with a channel cutoff ring, channel cutoff ring between gate pole and cathode
The adverse effect that the positive charge in oxide layer between gate pole produces silicon controlled trigger current, improves silicon controlled trigger current
Stability, and then improve the reliability used, have technique simple, the characteristics of being easy to implement.
Above content is only to the utility model structure example and explanation, the technology people of affiliated the art
Member does various modifications or additions to described specific embodiment or substitutes in a similar way, without departing from reality
With new structure or surmount scope defined in the claims, all should belong to the protection range of the utility model.
Claims (2)
- It is 1. a kind of silicon-controlled with channel cutoff ring, it is characterised in that：Including N-type semiconductor matrix, positioned at N-type semiconductor base The p-type base of both sides above and below body, positioned at the P+ type isolation diffusion area of N-type semiconductor matrix both sides, on N-type semiconductor matrix The groove (3) of end face, the N+ types cathodic region (4) in the p-type base of upside, the gate pole (2) between N+ types cathodic region 4, position Channel cutoff ring (1) between N+ types cathodic region and gate pole (2), and the anode metal electricity positioned at downside p-type base region surface Pole A, the cathodic metal electrode K positioned at gate metal electrode G and N+ type cathodic region (4) upper surface of gate pole (2) upper surface.
- It is 2. according to claim 1 a kind of silicon-controlled with channel cutoff ring, it is characterised in that：The channel cutoff ring (1) it is P+ type channel cutoff ring or N+ type channel cutoff rings.
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| CN201721251978.0U CN207233740U (en) | 2017-09-27 | 2017-09-27 | It is a kind of silicon-controlled with channel cutoff ring |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634096A (en) * | 2017-09-27 | 2018-01-26 | 安徽富芯微电子有限公司 | A kind of controllable silicon and its manufacture method with channel cutoff ring |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634096A (en) * | 2017-09-27 | 2018-01-26 | 安徽富芯微电子有限公司 | A kind of controllable silicon and its manufacture method with channel cutoff ring |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 230000 Hefei 503 high tech park, Anhui Patentee after: Wick Microelectronics Co., Ltd. Address before: 230000 room 521, innovation building, 860 Wangjiang West Road, Hefei high tech Zone, Anhui Patentee before: Anhui core Microelectronics Co., Ltd. |
|
| CP03 | Change of name, title or address | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Silicon controlled rectifier with channel cut-off ring and fabrication method thereof Effective date of registration: 20181112 Granted publication date: 20180413 Pledgee: Hefei Xingtai financing guarantee Group Limited Pledgor: Wick Microelectronics Co., Ltd. Registration number: 2018340000635 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20191128 Granted publication date: 20180413 Pledgee: Hefei Xingtai financing guarantee Group Limited Pledgor: Wick Microelectronics Co., Ltd. Registration number: 2018340000635 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |