CN105336628A - Wafer surface bonding technology and semiconductor device structure - Google Patents
Wafer surface bonding technology and semiconductor device structure Download PDFInfo
- Publication number
- CN105336628A CN105336628A CN201510624214.0A CN201510624214A CN105336628A CN 105336628 A CN105336628 A CN 105336628A CN 201510624214 A CN201510624214 A CN 201510624214A CN 105336628 A CN105336628 A CN 105336628A
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- wafer
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- thin layer
- dielectric layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/2954—Coating
- H01L2224/2957—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
- H01L2224/83375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
Abstract
The invention relates to the technical field of semiconductor device preparation, and particularly relates to a wafer surface bonding technology and a semiconductor device structure. A thin film layer is deposited on the surface of a wafer, then a dielectric layer including H+ ions is deposited, and finally bonding of the H+ ions in the dielectric layer and wafer Si interface dangling bonds is facilitated through an Anneal technology so that the degree of bonding of the wafer Si interface dangling bonds is enhanced. With application of the technical scheme, Dark Current and BLC performance of the device can be obviously improved.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation, particularly relate to a kind of crystal column surface bonding technology and a kind of semiconductor device structure.
Background technology
In wafer manufacturing process, because Si interface becomes key Si atom to lack and the existence of the non-bonding electrons of interface Si atom, form the dangling bonds with electrical activity (general crystal stops suddenly in surface because of lattice at Si interface, a unpaired electronics will be had at outermost each atom on surface, namely a unsaturated key is had, this key is called dangling bonds, be called for short Traps), the bonding degree of these dangling bonds is lower, the atom source forming bonding in prior art with dangling bonds is less and lack bonding power, cause the bonding degree of dangling bonds between Si interface lower, cause the DarkCurrent (dark current) of device, the poor-performings such as BLC (BLC function).
Therefore, how bonded energy makes the bonding degree of dangling bonds higher, makes the DarkCurrent of device, a great problem that the higher those skilled in the art of becoming of the performances such as BLC face simultaneously.
Summary of the invention
In view of the above problems, the invention provides a kind of crystal column surface bonding technology and a kind of semiconductor device structure, by depositing a thin layer at crystal column surface, then the dielectric layer that comprises H+ ion is deposited, finally adopt Anneal technique, promote the H+ ion in dielectric layer and wafer Si interface dangling bonds bonding, this technical scheme is specially:
A kind of wafer Si surface bond technique, wherein, described technique comprises:
There is provided a wafer, the surface of described wafer includes dangling bonds;
Deposit the surface that a thin layer covers described wafer;
The dielectric layer that deposition one comprises H+ ion covers the upper surface of described thin layer;
Adopt Anneal technique, make the dangling bonds bonding on the H+ ion of described dielectric layer and the surface of described wafer.
Above-mentioned wafer Si surface bond technique, wherein, described thin layer comprises the first film layer and the second thin layer.
Above-mentioned wafer Si surface bond technique, wherein, described dielectric layer material is SiN.
A kind of semiconductor device structure, wherein, described structure comprises:
Wafer, remained on surface has dangling bonds;
Thin layer, covers the surface of described wafer;
Dielectric layer, covers the upper surface of described thin layer, and has H+ ion in described dielectric layer; And
Utilize annealing process, make described H+ ion and described dangling bonds bonding, to improve the bonding degree of described crystal column surface.
Above-mentioned semiconductor device structure, wherein, described thin layer comprises the first film layer and the second thin layer;
Described the first film layer covers the surface of described wafer, and described second thin layer covers the surface of described the first film layer, and described dielectric layer covers the surface of described second thin layer.
Above-mentioned semiconductor device structure, wherein, described dielectric layer material is SiN.
Technique scheme tool has the following advantages or beneficial effect:
Adopt the technical program, promote that through SiNDEP and Anneal technique the dangling bonds of the Si of H+ ion and crystal column surface in SiN layer carry out bonding, improve wafer Si interface dangling bonds bonding degree, DarkCurrent and the BLC performance of device obviously improves.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is crystal column surface bonding technology flow chart in the embodiment of the present invention;
Fig. 2 a-2d is crystal column surface bonding technology structural representation in the embodiment of the present invention;
Fig. 3 a-3d is the present invention one specific embodiment crystal column surface bonding technology structural representation.
Embodiment
Structure shown in Figure 1, the invention provides a kind of crystal column surface bonding technology, this technique specifically comprises:
First, provide a wafer 1, the material on wafer 1 surface is Si, and the surface of wafer 1 comprises dangling bonds, shown in Fig. 2 a.
Secondly, deposit the surface that a thin layer covers wafer 1, preferably, shown in Fig. 2 b, first deposit a first film layer 2, preferably, the first film layer 2 is high-K dielectric layer, and wherein, the first film layer 2 covers the upper surface of wafer 1; Shown in Fig. 2 c, deposition one second thin layer 3, preferably, the second thin layer is silicon oxide layer, and the second thin layer 3 covers the upper surface of the first film layer 2.
Continue the dielectric layer 4 that deposition one comprises H+ ion, shown in Fig. 2 d, preferably, dielectric layer 4 is SiN layer, and dielectric layer 4 covers the upper surface of the second thin layer 3, comprises H+ ion in dielectric layer.
Finally, adopt Anneal technique, make the dangling bonds bonding on the surface of H+ ion in dielectric layer and wafer.
See structure shown in Fig. 3 a, the wafer 1 that one comprises Si surface is provided, this Si surface is formed with the dangling bonds of the Si with electrical activity, continue to cover a high-K dielectric layer 2 and one silica layer 3 on the surface at the Si of wafer, shown in Fig. 3 b, continue, shown in Fig. 3 c, cover the upper surface that a SiN layer 4 comprising H+ ion covers the second thin layer silica, in this SiN layer, comprise H+ ion.Finally, adopt Anneal technique, promote that the dangling bonds at the H+ ion in SiN layer and Si interface carry out bonding, improve the bonding degree of crystal column surface Si dangling bonds.
See structure shown in Fig. 3 d, the invention provides a kind of semiconductor device structure, wherein, this semiconductor device structure comprises wafer, thin layer and dielectric layer, wherein:
Wafer 1 remained on surface has dangling bonds; Thin layer, covers the surface of described wafer, and thin layer comprises the second thin layer 3 that the first film layer 2 that material is high K dielectric and material are silica; Dielectric layer 4, the upper surface of cover layer, and there is in dielectric layer H+ ion; Utilize annealing process, make the dangling bonds bonding on H+ ion in dielectric layer and wafer 1 surface, to improve the bonding degree of described crystal column surface.
Above-mentioned semiconductor device structure, wherein, described thin layer comprises the first film layer and the second thin layer;
In the present embodiment, the first film layer 2 covers the surface of wafer 1, and the second thin layer 3 covers the surface of the first film layer 2, and dielectric layer 4 covers the surface of the second thin layer 3.
In sum, the present invention is by the surface deposition thin layer comprising Si at wafer, then the upper surface of a dielectric layer cover layer is deposited, finally adopt Anneal technique, promote the dangling bonds bonding at H+ ion and the wafer Si interface comprised in the dielectric layer of H+ ion, adopt the technical program, DarkCurrent and the BLC performance of device obviously improves, simultaneously, through SiNDEP (deposition, deposition) and Anneal (annealing) technique impel the dangling bonds at the Si interface of H+ ion and wafer in SiN layer to carry out bonding, improve the bonding degree of wafer Si interface dangling bonds.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (6)
1. a wafer Si surface bond technique, is characterized in that, described technique comprises:
There is provided a wafer, the surface of described wafer includes dangling bonds;
Deposit the surface that a thin layer covers described wafer;
The dielectric layer that deposition one comprises H+ ion covers the upper surface of described thin layer;
Adopt Anneal technique, make the dangling bonds bonding on the H+ ion of described dielectric layer and the surface of described wafer.
2. wafer Si surface bond technique as claimed in claim 1, it is characterized in that, described thin layer comprises the first film layer and the second thin layer.
3. wafer Si surface bond technique as claimed in claim 1, it is characterized in that, described dielectric layer material is SiN.
4. a semiconductor device structure, is characterized in that, described structure comprises:
Wafer, remained on surface has dangling bonds;
Thin layer, covers the surface of described wafer;
Dielectric layer, covers the upper surface of described thin layer, and has H+ ion in described dielectric layer; And
Utilize annealing process, make described H+ ion and described dangling bonds bonding, to improve the bonding degree of described crystal column surface.
5. semiconductor device structure as claimed in claim 4, it is characterized in that, described thin layer comprises the first film layer and the second thin layer;
Described the first film layer covers the surface of described wafer, and described second thin layer covers the surface of described the first film layer, and described dielectric layer covers the surface of described second thin layer.
6. semiconductor device structure as claimed in claim 4, it is characterized in that, described dielectric layer material is SiN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510624214.0A CN105336628B (en) | 2015-09-25 | 2015-09-25 | A kind of crystal column surface bonding technology and a kind of semiconductor device structure |
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| CN201510624214.0A CN105336628B (en) | 2015-09-25 | 2015-09-25 | A kind of crystal column surface bonding technology and a kind of semiconductor device structure |
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| CN105336628A true CN105336628A (en) | 2016-02-17 |
| CN105336628B CN105336628B (en) | 2018-10-19 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158676A (en) * | 2016-07-27 | 2016-11-23 | 武汉新芯集成电路制造有限公司 | The bonding technology of a kind of crystal column surface and semiconductor device structure |
| CN106531649A (en) * | 2016-12-19 | 2017-03-22 | 武汉新芯集成电路制造有限公司 | Method for improving wafer bonding degree |
| CN106981414A (en) * | 2017-03-30 | 2017-07-25 | 武汉新芯集成电路制造有限公司 | The bonding method and semiconductor devices of crystal column surface |
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| CN1930668A (en) * | 2003-05-30 | 2007-03-14 | 东京毅力科创株式会社 | Method of modifying insulating film |
| CN101710580A (en) * | 2009-12-01 | 2010-05-19 | 杭州士兰集成电路有限公司 | Multi-layer compound passivation layer structure of Bipolar circuit and manufacturing process thereof |
| CN102136428A (en) * | 2011-01-25 | 2011-07-27 | 北京大学 | Preparation method of germanium-based Schottky N-type field effect transistor |
| CN102420194A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Passivation layer of integrated circuit and manufacturing method of passivation layer |
| CN103378003A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing CMOS device by means of stress memorization technique |
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2015
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1930668A (en) * | 2003-05-30 | 2007-03-14 | 东京毅力科创株式会社 | Method of modifying insulating film |
| CN101710580A (en) * | 2009-12-01 | 2010-05-19 | 杭州士兰集成电路有限公司 | Multi-layer compound passivation layer structure of Bipolar circuit and manufacturing process thereof |
| CN102136428A (en) * | 2011-01-25 | 2011-07-27 | 北京大学 | Preparation method of germanium-based Schottky N-type field effect transistor |
| CN102420194A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Passivation layer of integrated circuit and manufacturing method of passivation layer |
| CN103378003A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing CMOS device by means of stress memorization technique |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158676A (en) * | 2016-07-27 | 2016-11-23 | 武汉新芯集成电路制造有限公司 | The bonding technology of a kind of crystal column surface and semiconductor device structure |
| CN106531649A (en) * | 2016-12-19 | 2017-03-22 | 武汉新芯集成电路制造有限公司 | Method for improving wafer bonding degree |
| CN106531649B (en) * | 2016-12-19 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A method of improving wafer bonding degree |
| CN106981414A (en) * | 2017-03-30 | 2017-07-25 | 武汉新芯集成电路制造有限公司 | The bonding method and semiconductor devices of crystal column surface |
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| CN105336628B (en) | 2018-10-19 |
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