CN207124090U - Flat electrodes arrayed chip resistor - Google Patents

Abstract

Flat electrodes arrayed chip resistor, insulated substrate (1) positive and negative is corresponding with front electrode (3) and backplate (2) with respect to two edges, there is lateral conduction layer (7) on the lateral wall of this two sides opposite edges, there is resistive layer (4) between the positive two side front electrodes (3) of insulated substrate (1), in resistive layer (4), at least part is coated with the first protective layer (5) outside, the second protective layer (6) is coated with resistive layer (4) or the first protective layer (5), in front electrode (3), backplate (2) and lateral conduction layer (7) are coated with nickel dam (8) and tin layers (9) from inside to outside outside.Optimal improvements structure design, using special masking tool manufacture, it is easy to align under image instrument, cancel the printing of multiple tracks mask and film process, position is accurate, and electrode pattern is complete, easily fabricated, properties of product are stable and manufacturing cost is low, while are applicable to bulk production.

Description

Flat electrodes arrayed chip resistor

Technical field

It the utility model is related to and be conductively connected or the structure improved technology of current collector electrode, especially flat electrodes arrangement paster Resistor.

Background technology

Chip fixed resister, or Chip-R (SMD Resistor), are one kind in glassy metal uranium resistor. It is to mix metal powder and glass uranium powder, manufactured resistor, humidity and high temperature on substrate is imprinted on using silk screen print method, temperature It is small to spend coefficient, circuit space cost can be greatlyd save, design is more become more meticulous.Arrayed chip resistor is due to its small product size Small, power is big, dense arrangement, is easy to mount, and can be widely used in the communication products such as each electric appliances, personal data storage, mobile phone, And promote the further miniaturization of this electronic product.Because termination electrode shape is different, arrayed chip resistor is divided into three classes, A. male；B. female；C, flat electrodes.

The utility model proposes mainly for flat electrodes arrayed chip resistor.

Utility model content

The purpose of this utility model is to provide flat electrodes arrayed chip resistor, saves manufacturing cost, eliminates electrode quality Hidden danger.

The purpose of this utility model will be realized by following technical measures：Insulated substrate positive and negative is corresponding with respect to two edges There are front electrode and backplate, have lateral conduction layer on the lateral wall of this two sides opposite edges, in insulated substrate front two There is resistive layer between the front electrode of side, it is at least local outside resistive layer to be coated with the first protective layer, protected in resistive layer or first Layer is coated with the second protective layer, and nickel dam and tin are coated with from inside to outside outside front electrode, backplate and lateral conduction layer Layer.

Especially, longitudinal line of weakness and transverse scribes are formed with uniformly corresponding to clathrate in the front and back of insulated substrate Line；Backplate forms one group across being imprinted on each longitudinal line of weakness between each transverse scribes line；Front electrode position pair Should be in backplate.

The advantages of the utility model and effect：Optimal improvements structure design, using special masking tool manufacture, it is easy in shadow As being aligned under instrument, cancel the printing of multiple tracks mask and film process, position is accurate, and electrode pattern is complete, easily fabricated, properties of product Stable and manufacturing cost is low, while is applicable to bulk production.

Brief description of the drawings

Fig. 1 is the utility model manufacture method step schematic diagram.

Fig. 2 is the structural representation of the utility model embodiment 1.

Fig. 3 is the insulated substrate schematic diagram after step a described in the utility model；

Fig. 4 is the insulated substrate groove schematic diagram after step a described in the utility model；

Fig. 5 is the insulated substrate schematic rear view after step b described in the utility model；

Fig. 6 is the insulated substrate front schematic view after step c described in the utility model；

Fig. 7 is the insulated substrate front schematic view after step d described in the utility model；

Fig. 8 is the insulated substrate front schematic view after step e described in the utility model；

Fig. 9 is the insulated substrate front schematic view after step f described in the utility model；

Figure 10 is the insulated substrate front schematic view after step g described in the utility model；

Figure 11 is the strip substrate schematic diagram after step h described in the utility model；

Figure 12 is schematic diagram before the strip substrate sputtering after step i described in the utility model；

Figure 13 is that the masking baffle plate after step j described in the utility model synthesizes schematic diagram with tool；

Figure 14 is schematic diagram after the strip substrate sputtering after step k described in the utility model

Figure 15 is the granular semi-finished product resistance schematic diagram after step l, m described in the utility model；

Figure 16,17 are the granular semi-finished product resistance schematic diagram after step n described in the utility model；

Reference includes：

Insulated substrate 1, backplate 2, front electrode 3, resistive layer 4, the first protective layer 5, the second protective layer 6, side are led Electric layer 7, nickel dam 8, tin layers 9.

Embodiment

The utility model principle is, on the basis of use direction, as shown in Figure 1, manufacture method includes：In insulation base The front and back of plate forms longitudinal line of weakness and transverse scribes line with uniformly corresponding to clathrate, and corresponds to printing front electricity respectively Pole and backplate, and be dried and sinter；Printing forms electricity respectively between the longitudinal direction of each surface electrode of insulated substrate Resistance layer, burnt till again after drying；Printing forms first between the transverse direction of each resistive layer of insulated substrate and on each resistive layer Protective layer, burnt till again after drying；Resistance adjustment is carried out to each resistive layer of insulated substrate and the first protective layer by laser, And line of cut is produced, printing forms one layer of second protective layer on the first protective layer, then is dried and burns till；Along insulated substrate On transverse scribes line insulated substrate is fractureed substrate into strips, be stacked in special fixture；Tool is put into 2.5 element images Check, align under instrument；Side sputtering is carried out to each strip substrate using vacuum sputtering stove, forms lateral conduction layer；By each strip Substrate fractures to form independent arrangement Chip-R semi-finished product along longitudinal line of weakness, is put into the electro-plating roller of electroplating bath, makes row Front electrode, backplate and the lateral conduction layer of row Chip-R semi-finished product are respectively formed on one layer of nickel dam, then again in nickel dam One layer of tin layers of electroplating surface, and after over cleaning and drying formed arrangement Chip-R.

The utility model is described in further detail with reference to the accompanying drawings and examples.

Embodiment 1：As shown in Figure 2, to the flat electrodes arrayed chip resistor structure of single shaping, insulated substrate 1 is just Reverse side is corresponding with front electrode 3 and backplate 2 with respect to two edges, has lateral conduction on the lateral wall of this two sides opposite edges Layer 7, there is resistive layer 4 between the positive two side front electrodes 3 of insulated substrate 1, it is at least local outside resistive layer 4 to be coated with the first guarantor Sheath 5, the second protective layer 6 is coated with the protective layer 5 of resistive layer 4 or first, is led in front electrode 3, backplate 2 and side Nickel dam 8 and tin layers 9 are coated with from inside to outside outside electric layer 7.

The present embodiment process steps are as follows：

A. as shown in Figure 3, an insulated substrate is prepared, in the front and back of the insulated substrate with uniformly corresponding to clathrate Form longitudinal line of weakness and transverse scribes line as shown in Figure 4；

B. in the back up backplate of insulated substrate, as shown in Figure 5, the backplate is across being imprinted on each longitudinal direction On line of weakness, one group is formed between each transverse scribes line；

C. in the front printing front electrode of insulated substrate, as shown in Figure 6, the front electrode position correspondence is in back side electricity Pole, and be dried and sinter；

D. as shown in Figure 7, printing forms a resistive layer respectively between the longitudinal direction of each surface electrode of insulated substrate, does Burnt till again after dry；

E. as shown in Figure 8, printing forms first between the transverse direction of each resistive layer of insulated substrate and on each resistive layer Protective layer, burnt till again after drying；

F. as shown in Figure 9, each resistive layer of insulated substrate and first are protected by laser using radium-shine laser machine Layer carries out resistance adjustment, and produces line of cut, the resistance is adapted to required resistance value；

G. as shown in Figure 10, the second protective layer of printing formation is dried again on each first protective layer of insulated substrate And burn till；

H. as shown in Figure 11, insulated substrate is fractureed substrate into strips along the transverse scribes line on insulated substrate, and will Each strip substrate is stacked in special fixture by special board；

I. tool lateral means are adjusted, make material strip in tool neat；As shown in Figure 12, it is put into band iron in tool upper end And shell fragment in clinching；

J. as shown in Figure 13, shade flap and fixation are respectively loaded onto in tool tow sides；

K. as shown in Figure 14, tool is put under 2.5 dimension image instruments and checked, aligned；

L. as shown in Figure 15, side sputtering is carried out to each strip substrate using vacuum sputtering stove, forms lateral conduction layer；

M. each strip substrate is fractureed along longitudinal line of weakness to be formed arrangement Chip-R independent as shown in Figure 15 half into Product；

N. arrangement Chip-R semi-finished product are put into the electro-plating roller of electroplating bath, electro-plating roller is turned with setting speed It is dynamic, in the electric current of setting and under the conditions of the time, as shown in accompanying drawing 16,17, make front electrode, the back of the body of arrangement Chip-R semi-finished product Face electrode and lateral conduction layer are respectively formed on one layer of nickel dam, then again in one layer of tin layers of electroplating surface of nickel dam, and through over cleaning And arrangement Chip-R is formed after drying.

In the utility model, special masking tool is used after folding bar, is aligned under image instrument, position precision is high, cancels The process such as the printing of multiple tracks mask and pad pasting, electrode pattern is complete, and process procedure substantially reduces, and optimizes pure physical technology, ring Border affinity is excellent, and properties of product are stable and manufacturing cost is low, while are applicable to bulk production.

Claims (2)

1. flat electrodes arrayed chip resistor, it is characterised in that insulated substrate (1) positive and negative is corresponding with positive electricity with respect to two edges Pole (3) and backplate (2), there is lateral conduction layer (7) on the lateral wall of this two sides opposite edges, in insulated substrate (1) just There is resistive layer (4) between the side front electrode (3) of face two, in resistive layer (4), at least part is coated with the first protective layer (5) outside, Resistive layer (4) or the first protective layer (5) are coated with the second protective layer (6), in front electrode (3), backplate (2) and side Conductive layer (7) is coated with nickel dam (8) and tin layers (9) from inside to outside outside.

2. flat electrodes arrayed chip resistor as claimed in claim 1, it is characterised in that insulated substrate (1) front and The back side forms longitudinal line of weakness and transverse scribes line with uniformly corresponding to clathrate；Backplate (2) across be imprinted on each longitudinal direction carve In trace line, one group is formed between each transverse scribes line；Front electrode (3) position correspondence is in backplate (2).