CN207051795U - A kind of single channel server master board, single channel server master board interconnection architecture - Google Patents
A kind of single channel server master board, single channel server master board interconnection architecture Download PDFInfo
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- CN207051795U CN207051795U CN201721032709.5U CN201721032709U CN207051795U CN 207051795 U CN207051795 U CN 207051795U CN 201721032709 U CN201721032709 U CN 201721032709U CN 207051795 U CN207051795 U CN 207051795U
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- single channel
- server master
- master board
- channel server
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Abstract
It the utility model is related to a kind of single channel server master board, single channel server master board interconnection architecture, it is characterized in that, including single channel server master board, the single channel server master board is provided with processor, system control trunk module is provided with the processor, the processor is connected with several connectors, and some memory modules are additionally provided with the single channel server master board, and the memory module is dual inline memory module；The single channel server master board quantity is two, and two single channel server master boards are interconnected by cable.The connector is PCIe connectors, PCIe connectors quantity is 8 on each single channel mainboard, 8 PCIe connectors are divided into two groups, every group of 4 PCIe connectors, EYPC processors connect PCIe device by one of which PCIe connectors, and another group of PCIe connector is interconnected by cable and another single channel mainboard.
Description
Technical field
The utility model belongs to server design technical field, and in particular to a kind of single channel server master board, single channel service
Device mainboard interconnection architecture.
Background technology
EPYC is that Advanced Micro Devices release latest generation high-performance server processor.Compared with current Intel CPU,
There are higher core amounts, more internal memories to support and more high speed input/output passage on its single-chip, every
CPU is owned by 8 DDR4 main memory accesses（Highest can support 2TB internal memories）, the up to PCIe passages of 128.
Two-way server based on Intel CPU is interconnected by UPI buses, and UPI is QPI upgrading, and QPI is one
String type high speed point to point protocol of the kind based on bag transmission, is transmitted using differential signal and special clock.
2 groups of QPI have 20 data transmission lines, and send（TX）And recipient（RX）Clock signal.Intel UPI
The entitled super path interconnection technique of Intel of technology Chinese, there is the disposal ability of more efficient operating efficiency and more information, increase
Add bandwidth and performance, improve the transmission efficiency of message and the disposal ability of multitask.But based on UPI bus bars
CPU can only be connected on same mainboard, i.e., two CPU are placed on one piece of mainboard.The interconnection between mainboard can not be carried out, is applied to
This is higher.This is the deficiencies in the prior art part.
Utility model content
The purpose of this utility model is, the problems such as that can not be interconnected between above-mentioned prior art mainboard, there is provided design one
Kind single channel server master board, single channel server master board interconnection architecture, to solve above-mentioned technical problem.
In order to achieve the above object, the technical solution of the utility model is：
A kind of single channel server master board, including mainboard body, the mainboard body are provided with processor, in the processor
Trunk module is controlled provided with system, the processor is connected with several connectors, some deposit is additionally provided with the mainboard body
Module is stored up, the memory module is dual inline memory module.
Further, the processor is EYPC processors, and EYPC processors are internally integrated system control trunk module, institute
State system control trunk module and ethernet control chip is connected with by substrate management module.
Further, the connector is PCIe connectors, and EYPC processors connect PCIe device by PCIe connectors.
Further, the PCIe connectors quantity is 8；Dual inline memory module quantity is 16.
PCIe connectors are x16 PCIe connectors.
Single channel server master board maximum can be supported to be configured to：The thread of 32 core 64, dominant frequency 2.0GHz can farsighted frequency to 3.0GHz,
8 passage internal memories support maximum 2TB internal memories, 128 passages of PCIe 3.0, power consumption 180W.This single channel server master board and current E5-
2650 v4 two-way server mainboard is similar compared to performance, and price is in same section.
A kind of single channel server master board interconnection architecture, including single channel server master board, set on the single channel server master board
There is processor, system control trunk module is provided with the processor, the processor is connected with several connectors, the list
Some memory modules are additionally provided with the server master board of road, the memory module is dual inline memory module；
The single channel server master board quantity is two, and two single channel server master boards are interconnected by cable.
Further, the processor is EYPC processors, and EYPC processors are internally integrated system control trunk module, institute
State system control trunk module and ethernet control chip is connected with by substrate management module.
Further, the connector is PCIe connectors, and PCIe connectors quantity is 8 on each single channel server master board
Individual, 8 PCIe connectors are divided into two groups, and every group of 4 PCIe connectors, EYPC processors are connected by one of which PCIe connectors
PCIe device is connect, another group of PCIe connector is interconnected by cable and another single channel server master board.
Further, dual inline memory module quantity is 16.
Further, the cable is the cable using Infinity Fabric protocol communications.
PCIe connectors are x16 PCIe connectors.
Wherein, Infinity fabric are the distinctive mutual contact modes of AMD, and Infinity fabric actual are 64 height
Fast I/O, in single channel server master board, it can regard 64 passages of PCIE 3.0 to use, and processor can be carried out in two-way
Interconnection.
Up to 16 DIMMs DDR4 is supported on single channel server master board EPYC 8 main memory accesses of processor, there is provided up to
2TB total memory size, plus its high core number and 128 High Speed I/O, single channel server is with regard to that can meet the need of certain customers
Ask, now need to only buy single mainboard, reduce expense.If need performance boost, it is not necessary to change server, need to only buy again
One piece of single channel mainboard, you can obtain knockdown two-way server, reach performance requirement.
32 core EPYC processors provide 128 High Speed I/O, are available for PCIe3.0, SATA, NVMe and Infinity
Fabric is used.In the case of double mainboard interconnections, 64 interconnection are used between two processors.
The beneficial effects of the utility model are, are supported on single channel server master board EPYC 8 main memory accesses of processor more
Up to 16 DIMMs DDR4, there is provided up to 2TB total memory size, plus its high core number and 128 High Speed I/O, single channel clothes
Device be engaged in regard to that can meet the needs of certain customers, now need to only buy single mainboard, reduces expense.If needing performance boost, no
Need to change server, need to only buy one piece of single channel mainboard again, two single channel mainboard interconnections can obtain knockdown two-way clothes
Business device, reaches performance requirement.
In addition, the utility model design principle is reliable, and it is simple in construction, there is very extensive application prospect.
As can be seen here, the utility model compared with prior art, has substantive distinguishing features and progress, its beneficial effect implemented
Fruit is also obvious.
Brief description of the drawings
Fig. 1 is a kind of single channel server master board schematic block diagram provided by the utility model.
Fig. 2 is a kind of single channel server master board interconnection architecture connection diagram that the present embodiment provides.
Wherein, 2- processors, 3- systems control trunk module, 4- substrate management modules, 5- Ethernet chips, 6- storages
Module, 7- connectors.
Embodiment
Below in conjunction with the accompanying drawings and the utility model is elaborated by specific embodiment, and following examples are to this
The explanation of utility model, and the utility model is not limited to implementation below.
As shown in figure 1, a kind of single channel server master board that the present embodiment provides, including mainboard body, the mainboard body
Processor 2 is provided with, system control trunk module 3 is provided with the processor 2, the processor 2 is connected with several connections
Device 7, some memory modules 6 is additionally provided with the mainboard body, the memory module 6 is dual inline memory module.
The processor 2 is EYPC processors, and EYPC processors are internally integrated system control trunk module, the system control
Trunk module 3 processed is connected with ethernet control chip 5 by substrate management module 4.
The connector 7 is PCIe connectors, and EYPC processors connect PCIe device by PCIe connectors.
The PCIe connectors quantity is 8；Dual inline memory module quantity is 16.
PCIe connectors are x16 PCIe connectors.
Single channel server master board maximum can be supported to be configured to：The thread of 32 core 64, dominant frequency 2.0GHz can farsighted frequency to 3.0GHz,
8 passage internal memories support maximum 2TB internal memories, 128 passages of PCIe 3.0, power consumption 180W.
As shown in Fig. 2 a kind of single channel server master board interconnection architecture, including single channel server master board, the single channel service
Device mainboard is provided with processor 2, system control trunk module 3 is provided with the processor 2, the processor 2 is connected with some
Individual connector 7, some memory modules 6 is additionally provided with the single channel server master board, the memory module 6 is deposited for dual inline type
Store up module；
The single channel server master board quantity is two, and two single channel server master boards are interconnected by cable.
The processor 2 is EYPC processors, and EYPC processors are internally integrated system control trunk module, the system control
Trunk module processed is connected with ethernet control chip by substrate management module.
The connector is PCIe connectors, and PCIe connectors quantity is 8,8 on each single channel server master board
PCIe connectors are divided into two groups, and every group of 4 PCIe connectors, EYPC processors connect PCIe by one of which PCIe connectors
Equipment, another group of PCIe connector are interconnected by cable and another single channel server master board.
Dual inline memory module quantity is 16.
The cable is the cable using Infinity Fabric protocol communications.
PCIe connectors are x16 PCIe connectors.
Wherein, Infinity fabric are the distinctive mutual contact mode of Advanced Micro Devices, and Infinity fabric actual are 64
Bar High Speed I/O, in single channel server master board, it can regard 64 passages of PCIE 3.0 to use, and can be located in two-way
Manage the interconnection of device.
Up to 16 dual inline memory modules are supported on single channel server master board EPYC 8 main memory accesses of processor
DIMMs DDR4, there is provided up to 2TB total memory size, plus its high core number and 128 High Speed I/O, single channel server is just
Can meet the needs of certain customers, now need to only buy single mainboard, reduce expense.If need performance boost, it is not necessary to more
Server is changed, only need to buy one piece of single channel mainboard again, you can obtain knockdown two-way server, reach performance requirement.
32 core EPYC processors provide 128 High Speed I/O, are available for PCIe3.0, SATA, NVMe and Infinity
Fabric is used.In the case of double mainboard interconnections, 64 interconnection are used between two processors.
Disclosed above is only preferred embodiment of the present utility model, but the utility model is not limited to this, any
What those skilled in the art can think does not have creative change, and is made under the premise of the utility model principle is not departed from
Some improvements and modifications, should all fall in the scope of protection of the utility model.
Claims (7)
1. a kind of single channel server master board, it is characterised in that including mainboard body, the mainboard body is provided with processor, institute
State and system control trunk module is provided with processor, the processor is connected with several connectors, gone back on the mainboard body
Provided with some memory modules, the memory module is dual inline memory module.
2. a kind of single channel server master board according to claim 1, it is characterised in that the processor is EYPC processing
Device, EYPC processors are internally integrated system control trunk module, and the system control trunk module is connected by substrate management module
It is connected to ethernet control chip.
3. a kind of single channel server master board according to claim 2, it is characterised in that the connector quantity is 8；It is double
Row inline memory module quantity is 16.
4. a kind of single channel server master board according to claim 3, it is characterised in that the connector is PCIe connections
Device, EYPC processors connect PCIe device by PCIe connectors.
A kind of 5. single channel server master board interconnection architecture, it is characterised in that including single channel server master board, the single channel service
Device mainboard quantity is two, and two single channel server master boards are interconnected by cable；The single channel server master board is claim
Single channel server master board described in any one of 1-3.
6. a kind of single channel server master board interconnection architecture according to claim 5, it is characterised in that the connector is
PCIe connectors, PCIe connectors quantity is 8 on each single channel mainboard, and 8 PCIe connectors are divided into two groups, every group 4
PCIe connectors, EYPC processors connect PCIe device by one of which PCIe connectors, and another group of PCIe connector passes through
Cable interconnects with another single channel mainboard.
7. a kind of single channel server master board interconnection architecture according to claim 6, it is characterised in that the cable is use
The cable of Infinity Fabric protocol communications.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721032709.5U CN207051795U (en) | 2017-08-17 | 2017-08-17 | A kind of single channel server master board, single channel server master board interconnection architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721032709.5U CN207051795U (en) | 2017-08-17 | 2017-08-17 | A kind of single channel server master board, single channel server master board interconnection architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207051795U true CN207051795U (en) | 2018-02-27 |
Family
ID=61503113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721032709.5U Expired - Fee Related CN207051795U (en) | 2017-08-17 | 2017-08-17 | A kind of single channel server master board, single channel server master board interconnection architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207051795U (en) |
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2017
- 2017-08-17 CN CN201721032709.5U patent/CN207051795U/en not_active Expired - Fee Related
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180227 Termination date: 20180817 |
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| CF01 | Termination of patent right due to non-payment of annual fee |