CN107844433A - A kind of isomery mixing inner server framework - Google Patents
A kind of isomery mixing inner server framework Download PDFInfo
- Publication number
- CN107844433A CN107844433A CN201711191417.0A CN201711191417A CN107844433A CN 107844433 A CN107844433 A CN 107844433A CN 201711191417 A CN201711191417 A CN 201711191417A CN 107844433 A CN107844433 A CN 107844433A
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- Prior art keywords
- chip
- cpu
- nvm
- main fpga
- memory
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0064—Latency reduction in handling transfers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention discloses a kind of isomery mixing inner server framework, including：CPU computing boards and NVM plates；Cpu chip is provided with CPU computing boards, cpu chip is connected with dram chip；Main fpga chip is provided with NVM plates, main fpga chip is connected with dram chip and NVM memory bars；The cpu chip is connected by QPI buses with main fpga chip；The main fpga chip safeguards the global buffer uniformity of nonvolatile memory, realizes that global memory shares.This framework is by regarding the NVM with low-power consumption, Large Copacity as remote memory, and capacity is small, modes of the fireballing DRAM as near-end internal memory, structure Large Copacity, the isomery mixing memory system of low-power consumption；Unified addressing is carried out to isomery internal memory, the coupling of isomery memory system and speeds match is solved the problems, such as, safeguards global data uniformity.This framework memory size is big, low in energy consumption, and CPU access efficiencies are high.
Description
Technical field
The present invention relates to inner server framework field, and in particular to a kind of isomery mixing inner server framework.
Background technology
Active computer from internal memory all by the way of data are read, but along with technologies such as big data, cloud computings
Flourish so that mass data is put into after internal memory by people to be analyzed, calculated, and this just allows memory size under traditional mode to have
Limit, the problems such as power consumption is big, become more and more prominent.Meanwhile also exist between active computer internal memory and external memory due to I/O performances
The problem of data processing speed is low caused by mismatch.
The content of the invention
To solve the above problems, the present invention provides a kind of Large Copacity, the isomery mixing inner server frame of high access efficiency
Structure.
The technical scheme is that：A kind of isomery mixing inner server framework, including：CPU computing boards and NVM plates；
Cpu chip is provided with CPU computing boards, cpu chip is connected with dram chip；
Main fpga chip is provided with NVM plates, main fpga chip is connected with dram chip and NVM memory bars；
The cpu chip is connected by QPI buses with main fpga chip；The main fpga chip safeguards the overall situation of nonvolatile memory
Buffer consistency, realize that global memory shares.
Further, main fpga chip includes the first main fpga chip and the second main fpga chip；
The request of odd even address is evenly distributed to the first main fpga chip and second by the cpu chip by source address decoder
On main fpga chip, address space odd even cutting is realized.
Further, spread F PGA chips and NVM controller are additionally provided between main fpga chip and NVM memory bar；Institute
State main fpga chip to be connected with spread F PGA chips by NI buses, the spread F PAG chips pass through in NVM controller and NVM
Deposit bar.
Further, the spread F PGA chips are also connected with DRAM Cache chips by DDR controller.
Further, at least two cpu chips are set on CPU computing boards, and all cpu chips carry out the full interconnection of annular.
Further, four cpu chips are set on CPU computing boards.
Isomery mixing inner server framework provided by the invention, by the way that the NVM with low-power consumption, Large Copacity is used as far
End memory, capacity is small, modes of the fireballing DRAM as near-end internal memory, structure Large Copacity, the isomery mixing internal memory of low-power consumption
System；Unified addressing is carried out to isomery internal memory, the coupling of isomery memory system and speeds match is solved the problems, such as, safeguards global data one
Cause property.This framework memory size is big, low in energy consumption, and CPU access efficiencies are high.
Brief description of the drawings
Fig. 1 is specific embodiment of the invention configuration diagram.
Embodiment
Below in conjunction with the accompanying drawings and the present invention will be described in detail by specific embodiment, and following examples are to the present invention
Explanation, and the invention is not limited in implementation below.
The present invention is based on DRAM（Dynamic Random Access Memory, memory grain）, one piece to include annular complete
Interconnect CPU computing board and one piece include FPGA, DRAM and NVM（Non-Volatile Memory, nonvolatile storage）Internal memory
The NVM plates of bar, build a kind of Large Copacity, low-power consumption isomery mixing internal memory server architecture, and isomery internal memory is united
One addressing, solve the problems, such as the coupling of isomery memory system and speeds match, safeguard global data uniformity.
As shown in figure 1, this framework includes：CPU computing boards and NVM plates.
It is provided with cpu chip on CPU computing boards, cpu chip is connected with dram chip, and capacity is small, fireballing DRAM makees
For near-end internal memory.
It is provided with main fpga chip on NVM plates, main fpga chip is connected with dram chip and NVM memory bars, low-power consumption, big
The NVM of capacity is as remote memory.
Cpu chip passes through QPI（Quick Path Interconnect, quick interconnecting channels）Bus and main fpga chip
Connection.Wherein main fpga chip is the acp chip of the framework, and it safeguards the global buffer uniformity of nonvolatile memory, is realized complete
Office's memory sharing.
In this framework, odd even cutting can be carried out to system address space, i.e., main fpga chip includes the first main FPGA cores
Piece and second main two fpga chips of fpga chip, two fpga chips are each responsible for the processing of half NVM address spaces.
The request of odd even address is evenly distributed to the first main fpga chip and the second master by CPU ends, cpu chip by source address decoder
On the two fpga chips of fpga chip, each FPGA realizes QPI Home Agent function, and each FPGA realizes one
Individual QPI Home Agent function.NVM memory access can be in the first main fpga chip and second main fpga chip the two FPGA
Parallel processing on chip, effectively to lift long-range memory bandwidth.
Spread F PGA chips and NVM controller are also provided with NVM plates between main fpga chip and NVM memory bars.It is main
Fpga chip is connected by NI buses with spread F PGA chips, and spread F PAG chips pass through NVM controller and NVM memory bars.
In the present embodiment, spread F PGA chips also accordingly include the first spread F PGA chips and the second spread F PGA chips, the first master
Fpga chip passes through NI（National Instruments, industrial communication protocol）Bus is connected with the first spread F PGA chips,
Second main fpga chip is connected by NI buses with the second spread F PGA chips, is entered between main fpga chip and spread F PGA chips
Row high speed transmission of signals, spread F PGA chips can be achieved NVM memory expansion, establish TB levels by the control to NVM memory bars
Isomery mixing inner server system.In addition, it is necessary to explanation, main fpga chip can also assist QPI protocol conversions for NI
View, to realize that the uniformity of nonvolatile memory extends.
Spread F PGA chips are also connected with DRAM Cache chips by DDR controller, and DRAM is served as into NVM chips
Cache, for covering and alleviating nonvolatile storage relative to delay performance poor DRAM.
In the present embodiment, at least two cpu chips are set, all cpu chips carry out the full interconnection of annular on CPU computing boards.
Four cpu chips specifically can be set, this four full interconnections of cpu chip annular.
This framework is for operating system, it is seen that be that there is non-volatile memory headroom by what NVM was formed, they will
It is the location of Installed System Memory data, and DRAM is by as the buffering area of runtime data.For programmer, it is seen
Be a unified addressing, unified management " transparent " isomery mixing memory system.
The present embodiment includes FPGA, DRAM based on DRAM, one piece of computing board for including four totally interconnected CPU of annular and one piece
And the NVM plates of NVM memory bars, build a kind of Large Copacity, low-power consumption isomery mixing internal memory server architecture, and in isomery
Row unified addressing is deposited into, the coupling of isomery memory system and speeds match is solved the problems, such as, safeguards global data uniformity.
Disclosed above is only the preferred embodiment of the present invention, but the present invention is not limited to this, any this area
What technical staff can think does not have creative change, and some improvement made without departing from the principles of the present invention and
Retouching, should all be within the scope of the present invention.
Claims (6)
- A kind of 1. isomery mixing inner server framework, it is characterised in that including：CPU computing boards and NVM plates；Cpu chip is provided with CPU computing boards, cpu chip is connected with dram chip；Main fpga chip is provided with NVM plates, main fpga chip is connected with dram chip and NVM memory bars；The cpu chip is connected by QPI buses with main fpga chip；The main fpga chip safeguards the overall situation of nonvolatile memory Buffer consistency, realize that global memory shares.
- 2. isomery mixing inner server framework according to claim 1, it is characterised in that main fpga chip includes first Main fpga chip and the second main fpga chip；The request of odd even address is evenly distributed to the first main fpga chip and second by the cpu chip by source address decoder On main fpga chip, address space odd even cutting is realized.
- 3. isomery mixing inner server framework according to claim 1 or 2, it is characterised in that main fpga chip and NVM Spread F PGA chips and NVM controller are additionally provided between memory bar；The main fpga chip passes through NI buses and spread F PGA Chip connects, and the spread F PAG chips pass through NVM controller and NVM memory bars.
- 4. isomery mixing inner server framework according to claim 3, it is characterised in that the spread F PGA chips are also DRAM Cache chips are connected with by DDR controller.
- 5. the isomery mixing inner server framework according to claim 1,2 or 4, it is characterised in that set on CPU computing boards At least two cpu chips are put, all cpu chips carry out the full interconnection of annular.
- 6. isomery mixing inner server framework according to claim 5, it is characterised in that set four on CPU computing boards Individual cpu chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201711191417.0A CN107844433A (en) | 2017-11-24 | 2017-11-24 | A kind of isomery mixing inner server framework |
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| CN201711191417.0A CN107844433A (en) | 2017-11-24 | 2017-11-24 | A kind of isomery mixing inner server framework |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109189700A (en) * | 2018-10-19 | 2019-01-11 | 郑州云海信息技术有限公司 | A kind of exented memory device, expanded memory system, exented memory access method |
| CN109684257A (en) * | 2018-12-24 | 2019-04-26 | 广东浪潮大数据研究有限公司 | A kind of long-distance inner expansion management system |
| CN110221985A (en) * | 2019-06-06 | 2019-09-10 | 成都海光集成电路设计有限公司 | The apparatus and method of across chip maintenance buffer consistency strategy |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202093427U (en) * | 2011-05-16 | 2011-12-28 | 曙光信息产业股份有限公司 | Multi-longson No.3 series CPU interconnection device |
| CN103488436A (en) * | 2013-09-25 | 2014-01-01 | 华为技术有限公司 | Memory extending system and memory extending method |
| CN104360963A (en) * | 2014-11-26 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | Heterogeneous hybrid memory method and device oriented to memory computing |
| CN104461941A (en) * | 2014-12-26 | 2015-03-25 | 浪潮电子信息产业股份有限公司 | Memory system structure and management method |
| CN104484021A (en) * | 2014-12-23 | 2015-04-01 | 浪潮电子信息产业股份有限公司 | Server system with expandable memory |
| CN105242761A (en) * | 2015-11-17 | 2016-01-13 | 浪潮(北京)电子信息产业有限公司 | Server framework |
| CN205091735U (en) * | 2015-08-28 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Novel extension module based on QPI bus realizes extend system memory |
| CN105824374A (en) * | 2016-04-01 | 2016-08-03 | 浪潮电子信息产业股份有限公司 | Framework of binary star type server |
| CN106843772A (en) * | 2017-02-14 | 2017-06-13 | 郑州云海信息技术有限公司 | A kind of system and method based on uniformity bus extension nonvolatile memory |
-
2017
- 2017-11-24 CN CN201711191417.0A patent/CN107844433A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202093427U (en) * | 2011-05-16 | 2011-12-28 | 曙光信息产业股份有限公司 | Multi-longson No.3 series CPU interconnection device |
| CN103488436A (en) * | 2013-09-25 | 2014-01-01 | 华为技术有限公司 | Memory extending system and memory extending method |
| CN104360963A (en) * | 2014-11-26 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | Heterogeneous hybrid memory method and device oriented to memory computing |
| CN104484021A (en) * | 2014-12-23 | 2015-04-01 | 浪潮电子信息产业股份有限公司 | Server system with expandable memory |
| CN104461941A (en) * | 2014-12-26 | 2015-03-25 | 浪潮电子信息产业股份有限公司 | Memory system structure and management method |
| CN205091735U (en) * | 2015-08-28 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Novel extension module based on QPI bus realizes extend system memory |
| CN105242761A (en) * | 2015-11-17 | 2016-01-13 | 浪潮(北京)电子信息产业有限公司 | Server framework |
| CN105824374A (en) * | 2016-04-01 | 2016-08-03 | 浪潮电子信息产业股份有限公司 | Framework of binary star type server |
| CN106843772A (en) * | 2017-02-14 | 2017-06-13 | 郑州云海信息技术有限公司 | A kind of system and method based on uniformity bus extension nonvolatile memory |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109189700A (en) * | 2018-10-19 | 2019-01-11 | 郑州云海信息技术有限公司 | A kind of exented memory device, expanded memory system, exented memory access method |
| CN109684257A (en) * | 2018-12-24 | 2019-04-26 | 广东浪潮大数据研究有限公司 | A kind of long-distance inner expansion management system |
| CN109684257B (en) * | 2018-12-24 | 2022-08-12 | 广东浪潮大数据研究有限公司 | Remote memory expansion management system |
| CN110221985A (en) * | 2019-06-06 | 2019-09-10 | 成都海光集成电路设计有限公司 | The apparatus and method of across chip maintenance buffer consistency strategy |
| CN110221985B (en) * | 2019-06-06 | 2021-04-23 | 成都海光集成电路设计有限公司 | Device and method for maintaining cache consistency strategy across chips |
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Application publication date: 20180327 |