WO2023274032A1

WO2023274032A1 - Storage access circuit, integrated chip, electronic device and storage access method

Info

Publication number: WO2023274032A1
Application number: PCT/CN2022/100807
Authority: WO
Inventors: 刘琦; 左丰国; 江喜平
Original assignee: 西安紫光国芯半导体有限公司
Priority date: 2021-07-02
Filing date: 2022-06-23
Publication date: 2023-01-05
Also published as: CN115563052A

Abstract

The present application relates to the technical field of electronic circuits. Disclosed are a storage access circuit, an integrated chip, an electronic device and a storage access method. The storage access circuit comprises a network unit, multiplexers and storage control modules. Each routing node is connected to at least one multiplexer, and each multiplexer is connected to at least two storage control modules, so as to perform multiplexing on the at least two storage control modules, thereby performing storage access on storage units, which are connected to the storage control modules. In this way, high-bandwidth storage access to a high-capacity storage unit can be realized.

Description

Storage access circuit, integrated chip, electronic device and storage access method

This application claims the priority of the Chinese patent application with application number 202110750108.2, the contents of which are incorporated in this application by reference.

【Technical field】

The application relates to the technical field of electronic circuits, in particular to storage access circuits, integrated chips, electronic equipment and storage access methods.

【Background technique】

With the rapid growth of application computing scale, storage access bandwidth and energy consumption have become important factors limiting the development of large-scale computing circuits.

【Content of invention】

The technical problem mainly solved by this application is to provide storage access circuit, integrated chip, electronic equipment and storage access method, which can realize high-bandwidth storage access to large-capacity storage units.

In order to solve the above problems, the first technical solution adopted by the present application is to provide a storage access circuit, the storage access circuit includes: a network unit, the network unit includes at least one routing node; a multiplexer; a storage control module, For connecting storage units; wherein, each routing node is connected to at least one multiplexer, and each multiplexer is connected to at least two storage control modules to multiplex at least two storage control modules, Further, storage access is performed to the storage unit connected to the storage control module.

Wherein, each routing node is connected to at most 4 other routing nodes.

Wherein, at least two routing nodes are distributed in an array in the form of M rows*N columns, and each routing node is connected to other routing nodes adjacent in the row or column direction, wherein M and N are positive integers.

Wherein, M is 3, and N is 3; each routing node is connected to 2 multiplexers, and each multiplexer is connected to 8 storage control modules.

Wherein, M is 4, and N is 4; each routing node is connected to 4 multiplexers, and each multiplexer is connected to 16 storage control modules.

Wherein, the storage control module includes: a first interface unit connected to the multiplexer; a read control unit connected to the first interface unit for controlling the reading of data in the storage unit; a write control unit connected to the first interface unit, It is used to control writing data to the storage unit; the second interface unit is connected to the read control unit, the write control unit and the storage unit.

Wherein, the storage control module further includes a refresh unit connected to the second interface unit, and the refresh unit is used for refreshing the storage unit.

Wherein, the data bit width of the storage control module is 128bit, and the frequency is 400MHz.

Wherein, the storage access circuit also includes: computing engines, and each routing node is connected to at least one computing engine.

Wherein, the distance between the routing node and other routing nodes connected to the routing node is the same.

Wherein, the data transmission time between the routing node and other routing nodes connected to the routing node is the same.

In order to solve the above problems, the second technical solution adopted by this application is to provide an integrated chip, which includes: a logic module and a storage array module; a storage access circuit is integrated on the logic module; the storage access circuit includes: a network unit , the network unit includes at least one routing node; a multiplexer; a storage control module for connecting the storage unit; wherein, each routing node is connected to at least one multiplexer, and each multiplexer is connected to at least two A storage control module, to multiplex at least two storage control modules, and then perform storage access to the storage unit connected to the storage control module; the storage array module is integrated with the storage unit, and the logic module and the storage array module are laminated and bonded connect.

Wherein, the storage array module is a dynamic random storage array module.

Wherein, each routing node is connected to at most 4 other routing nodes; wherein, the distance between the routing node and other routing nodes connected with the routing node is the same; and/or the distance between the routing node and other routing nodes connected with the routing node Data transfer times are the same.

In order to solve the above problems, the third technical solution adopted by the present application is to provide a storage access method, the method includes: a routing node receives a data access instruction, and determines at least one corresponding multiplexer according to the data access instruction; The multiplexer determines at least one corresponding storage control module according to the data access instruction; the storage control module obtains data from the correspondingly connected storage unit according to the data access instruction and sends it to the multiplexer; the multiplexer sends the data to the routing node.

Wherein, the step of the multiplexer sending the data to the routing node includes: the multiplexer synthesizes the data, and sends the synthesized data to the routing node.

Wherein, after the multiplexer sends the data to the routing node, it also includes: the routing node sends the synthesized data to the calculation engine; the calculation engine decodes the synthesized data, and performs corresponding processing based on the decoded data operation.

Wherein, the method further includes: the routing node receives the data write instruction, and determines at least one corresponding multiplexer according to the data write instruction; the multiplexer determines the corresponding at least one storage control module according to the data write instruction ; The storage control module obtains the data to be written according to the data writing instruction, and writes the data to be written into the storage unit connected to the storage control module.

Wherein, before the step of the routing node receiving the data writing instruction, it includes: the computing engine generates the writing instruction, and sends the writing instruction to the routing node.

The beneficial effect of the application is: different from the situation of the prior art, the storage access circuit, integrated chip, electronic equipment and storage access method provided by the application. The storage access circuit utilizes each routing node to connect at least one multiplexer, and each multiplexer is connected to at least two storage control modules, so that at least two storage control modules can be multiplexed, and then Perform storage access to the storage unit connected to the storage control module. During storage access, at least two storage control modules connected to each multiplexer can provide higher bandwidth, so as to realize high-capacity storage unit Bandwidth storage access.

【Description of drawings】

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort. in:

FIG. 1 is a schematic structural diagram of an embodiment of a storage access circuit provided by the present application;

FIG. 2 is a schematic structural diagram of another embodiment of the storage access circuit provided by the present application;

FIG. 3 is a schematic structural diagram of an embodiment of a plurality of routing nodes provided by the present application;

FIG. 4 is a schematic structural diagram of another embodiment of the storage access circuit provided by the present application;

FIG. 5 is a schematic structural diagram of an embodiment of a storage control module provided by the present application;

FIG. 6 is a schematic structural diagram of another embodiment of the storage control module provided by the present application;

FIG. 7 is a schematic structural diagram of an embodiment of an integrated chip provided by the present application;

FIG. 8 is a schematic structural diagram of an embodiment of an electronic device provided by the present application;

FIG. 9 is a schematic flowchart of an embodiment of a storage access method provided by the present application;

Fig. 10 is a schematic flowchart of another embodiment of the storage access method provided by the present application.

【detailed description】

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the specific embodiments described here are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only some structures related to the present application are shown in the drawings but not all structures. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first", "second", etc. in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of an embodiment of a storage access circuit provided in the present application. The storage access circuit 100 includes a network unit 10 , a multiplexer 30 and a storage control module 40 .

Wherein, the network unit 10 includes at least one routing node 101, and each routing node 101 is connected with at least one multiplexer 30, and each multiplexer 30 is connected with at least two storage control modules 40, so as to control at least two storage The control module 40 performs multiplexing, and then performs storage access to the storage units connected to the storage control module 40 .

In some embodiments, network unit 10 may be a network-on-chip. Such as two-dimensional mesh network on chip. Network on chip (NoC) is a new communication method for System on chip (SoC). It is the main component of multi-core technology. The NoC approach brings a new on-chip communication method that significantly outperforms the performance of traditional bus-based systems (bus). NoC-based systems are better suited to globally asynchronous and partially synchronous clocking mechanisms used in future complex multi-core SoC designs.

The multiplexer 30 can receive multiple input signals, synthesize a single output signal in a recoverable manner for each input signal, and select to read or write data from the corresponding channel.

The storage control module 40 is used to connect the storage unit to control the storage unit, such as reading data from the storage unit or writing data to the storage unit.

In some embodiments, the numbers of routing nodes 101, multiplexers 30 and storage control modules 40 may be set according to actual needs. Further, the number of multiplexers 30 connected to each routing node 101 may be the same, for example, each routing node 101 is connected to 1, 2, 3, 4, 5 or 6 multiplexers 30 . In another application scenario, the number of multiplexers 30 connected to each routing node 101 may be different, for example, the first routing node 101 is connected to two multiplexers 30, and the second routing node 101 Three multiplexers 30 are connected, the third routing node 101 is connected to four multiplexers 30 , and the fourth routing node 101 is connected to two multiplexers 30 .

Further, the number of storage control modules 40 connected to each multiplexer 30 may be the same, for example, each multiplexer 30 is connected to 2, 4, 8 or 16 storage control modules 40 . The number of storage control modules 40 connected to each multiplexer 30 can also be different, such as the first multiplexer 30 is connected to 4 storage control modules 40, and the second multiplexer 30 is connected to 8 storage control modules 40, the third multiplexer 30 is connected to 16 storage control modules 40, and the fourth multiplexer 30 is connected to 32 storage control modules 40.

Wherein, the routing node 101 in the storage access circuit 100 is connected to an external processing module. Based on this, the reading process of the entire storage access circuit 100 is described:

The external processing module can generate a data access instruction and send it to the routing node 101, and the routing node 101 determines corresponding multiple or single multiplexers 30 according to the data access instruction, and sends the data access instruction to the multiplexer 30 . The multiplexer 30 allocates according to the data access instruction to determine corresponding multiple or single storage control modules 40 , and sends the data access instruction to the storage control module 40 . The storage control module 40 acquires data from the correspondingly connected storage units according to the data access instruction, and sends the data to the multiplexer 30 . The multiplexer 30 synthesizes the data sent by multiple or single storage control modules 40, and sends the synthesized data to the routing node 101, and the routing node 101 sends the synthesized data to the external processing module. After obtaining the synthesized data, the external processing module decodes the synthesized data to obtain the data before synthesis. Then perform calculations on these data.

The writing process of the entire storage access circuit 100 is described as follows:

The external processing module can generate a data writing instruction and send it to the routing node 101, and the routing node 101 determines corresponding multiple or single multiplexers 30 according to the data writing instruction, and sends the data writing instruction to the multiplexer 30. Use device 30. The multiplexer 30 distributes according to the data write instruction to determine corresponding multiple or single storage control modules 40 , and sends the data write instruction to the storage control module 40 . The storage control module 40 obtains the data to be written according to the data writing instruction, and writes the data to be written into the correspondingly connected storage unit.

In this embodiment, the storage access circuit 100 utilizes the way that each routing node is connected to at least one multiplexer 30, and each multiplexer 30 is connected to at least two storage control modules 40, so that at least two The storage control module 40 performs multiplexing. During storage access, at least two storage control modules 40 connected to each multiplexer 30 can provide higher bandwidth, thereby enabling high-bandwidth storage access to large-capacity storage units.

Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of another embodiment of a storage access circuit provided in the present application. Compared with the above-mentioned first embodiment shown in FIG. 1 , the difference of this embodiment is that a computing engine 20 is also included.

The computing engine 20 may include at least one of a CPU (central processing unit, central processing unit), a DSP (Digital Signal Processor, digital signal processor), and a GPU (graphics processing unit, graphics processor).

Wherein, each routing node is connected to at least one computing engine 20 and at least one multiplexer 30, and each multiplexer 30 is connected to multiple storage control modules 40 to multiplex multiple storage control modules 40 use. Routing node 101 is used to control data transmission. The data output by the multiplexer 30 is transmitted to the calculation engine 20 through the routing node 101, so that the calculation engine 20 performs corresponding calculations based on these data.

In some embodiments, the numbers of routing nodes 101 , computing engines 20 , multiplexers 30 and storage control modules 40 can be set according to actual needs. In an application scenario, the number of computing engines 20 connected to each routing node 101 may be the same, for example, 2, 3, 4, 5 or 6 computing engines 20 connected to each routing node 101 . In another application scenario, the number of computing engines 20 connected to each routing node 101 may be different, for example, the first routing node 101 is connected to 2 computing engines 20, and the second routing node 101 is connected to 3 computing engines 20 , the third routing node 101 is connected to four computing engines 20 , and the fourth routing node 101 is connected to two computing engines 20 .

In an application scenario, the reading process of the entire storage access circuit 100 is described as follows:

The corresponding functional modules in the computing engine 20 can generate data access instructions and send them to the routing node 101. The routing node 101 determines the corresponding multiple or single multiplexers 30 according to the data access instructions, and sends the data access instructions to the multiplexers 30. Multiplexer 30. The multiplexer 30 allocates according to the data access instruction to determine corresponding multiple or single storage control modules 40 , and sends the data access instruction to the storage control module 40 . The storage control module 40 acquires data from the correspondingly connected storage units according to the data access instruction, and sends the data to the multiplexer 30 . The multiplexer 30 synthesizes the data sent by multiple or single storage control modules 40 , and sends the synthesized data to the routing node, and the routing node sends the synthesized data to the computing engine 20 . After obtaining the synthesized data, the corresponding functional modules in the calculation engine 20 decode the synthesized data to obtain the data before synthesis. Then perform calculations on these data.

In an application scenario, the writing process of the entire storage access circuit 100 is described as follows:

The corresponding functional modules in the computing engine 20 can generate a data write instruction and send it to the routing node 101, and the routing node 101 determines corresponding multiple or single multiplexers 30 according to the data writing instruction, and sends the data writing instruction to to the multiplexer 30. The multiplexer 30 distributes according to the data write instruction to determine corresponding multiple or single storage control modules 40 , and sends the data write instruction to the storage control module 40 . The storage control module 40 acquires the data to be written according to the data writing instruction, and writes the data to be written into the correspondingly connected storage unit.

In this embodiment, the storage access circuit 100 utilizes the way that each routing node 101 is connected to at least one multiplexer 30, and each multiplexer 30 is connected to at least two storage control modules 40, so that at least two A storage control module 40 performs multiplexing. During storage access, at least two storage control 40 modules connected to each multiplexer 30 can provide higher bandwidth, thereby enabling high-bandwidth storage access to large-capacity storage units, so that the multiplexer 30 can output high-bandwidth storage access data to routing node 101, and routing node 101 can reasonably allocate storage access data to any one or more computing engines 20 on routing node 101, thereby improving computing performance.

Referring to FIG. 3 , FIG. 3 is a schematic structural diagram of an embodiment of multiple routing nodes provided by the present application. Take the nine routing nodes in Figure 3 as an example for illustration:

Routing nodes include A, B, C, D, E, F, G, H, and I. Among them, routing node A is connected with routing node B and routing node D, routing node B is connected with routing node A, routing node C and routing node E, routing node C is connected with routing node B and routing node F, routing node E is connected with routing node Node A, routing node E and routing node G are connected, routing node E is connected with routing node B, routing node D, routing node F and routing node H, routing node F is connected with routing node C, routing node E and routing node I, Routing node G is connected to routing node D and routing node H, routing node H is connected to routing node E, routing node G and routing node I, and routing node I is connected to routing node H and routing node F.

Wherein, it can be seen that the routing node is connected to 2 other routing nodes, 3 other routing nodes or 4 other routing nodes. It can be understood that due to the positional relationship of the routing nodes, since there are other routing nodes in only some directions of the edge routing nodes, the number of other routing nodes connected to the routing nodes at different positions is different.

Thus, each routing node is connected to at most 4 other routing nodes 101 .

Further, when the network unit includes at least two routing nodes 101, the at least two routing nodes 101 are distributed in an array in the form of M rows*N columns, and each routing node 101 is connected to other routing nodes 101 adjacent in the row or column direction , where M and N are positive integers. It can be understood that if a plurality of routing nodes 101 are distributed in an array of M rows*N columns, each routing node 101 is connected to at most 4 other routing nodes 101, which is more in line with the efficiency of data transmission between routing nodes 101 and routing nodes 101.

Combined with Figure 3 for illustration:

The distances from routing node E to routing node B, routing node D, routing node F, and routing node H are the same, and the data transmission time is the same when the wiring materials are consistent.

If routing node E is also connected to routing node A, the distance between routing node E and routing node A is greater than the distance from routing node E to routing node B, routing node D, routing node F and routing node H, which affects the network unit 10 on the contrary. Global adjustments.

Therefore, at least two routing nodes are arranged in an array of M rows*N columns, so that the distance between every two routing nodes is the same, which can not only reduce the process in the manufacturing process, but also improve the performance of the network unit 10 .

Based on this, please refer to FIG. 4 , which is a schematic structural diagram of another embodiment of the storage access circuit provided by the present application. The network unit includes 9 routing nodes, arrayed in the form of M rows*N columns, where M can be 3, and N can be 3. Routing nodes include A, B, C, D, E, F, G, H, and I.

Each routing node is connected to two multiplexers 30 , and each multiplexer 30 is connected to eight storage control modules 40 . Each routing node is connected to two computing engines 20 . Then the number of storage control modules 40 in the storage access circuit 100 is 144. The number of multiplexers 30 is 18, and the number of computing engines 20 is 18.

Taking the data bit width of the storage control module 40 as 128bit and the frequency as 400MHz as an example, the bandwidth of a single storage control module 40 is (128*400/8)MBps=6.4GB/s. Then the total bandwidth of the storage access circuit 100 is 144*6.4GB/s=921.6GB/s.

In this embodiment, 144 storage control modules 40 can provide a bandwidth of 921.6GB/s, so that the storage access circuit 100 can realize high-bandwidth storage access to large-capacity storage units, so that the multiplexer 30 can output high-bandwidth The stored and accessed data is sent to the routing node, and the routing node can reasonably distribute the stored and accessed data to any one or more computing engines 20 on the routing node, thereby improving computing performance.

In other embodiments, the network unit includes 16 routing nodes, arrayed in the form of M rows*N columns, M may be 4, and N may be 4. Or M can be 2 and N can be 8.

Take M as 4 and N as 4 as an example for illustration:

Each routing node is connected to 4 multiplexers 30, and each multiplexer 30 is connected to 16 storage control modules. Each routing node is connected to 4 computing engines 20 . Then the number of storage control modules 40 in the storage access circuit 100 is 1024. The number of multiplexers 30 is 64, and the number of computing engines 20 is 64.

Taking the data bit width of the storage control module 40 as 128bit and the frequency as 400MHz as an example, the bandwidth of a single storage control module 40 is (128*400/8)MBps=6.4GB/s. Then the total bandwidth of the storage access circuit 100 is 1024*6.4GB/s=6553.6GB/s.

In this embodiment, 1024 storage control modules 40 can provide a bandwidth of 6553.6GB/s, so that the storage access circuit 100 can realize high-bandwidth storage access to large-capacity storage units, so that the multiplexer 30 can output high-bandwidth The stored and accessed data is sent to the routing node, and the routing node can reasonably distribute the stored and accessed data to any one or more computing engines 20 on the routing node, thereby improving computing performance.

In other embodiments, the data bit width of the storage control module 40 may be 64 bits, and the frequency may be 900 MHz.

Referring to FIG. 5 , FIG. 5 is a schematic structural diagram of an embodiment of a storage control module provided by the present application. The storage control module 40 includes a first interface unit 41 , a read control unit 42 , a write control unit 43 and a second interface unit 44 .

Wherein, the first interface unit 41 is connected to the multiplexer 30; the read control unit 42 is connected to the first interface unit 41 for controlling the reading of data in the storage unit; the write control unit 43 is connected to the first interface unit 41 for Control writing data to the storage unit; the second interface unit 44 connects the read control unit 42 , the write control unit 43 and the storage unit.

When multiple storage control modules 40 are applied to the storage access circuit 100 in any of the above-mentioned embodiments, the multiple storage control modules 40 are connected to a multiplexer 30, which can provide higher bandwidth during storage access, and achieve large High-bandwidth storage access for capacity storage units. When there is a computing engine 20 in the storage access circuit 100, the multiplexer 30 can output high-bandwidth storage access data to the routing node, and the routing node can reasonably distribute the storage access data to any one or more computing engines on the routing node 20, thereby improving computing performance.

Further, the storage unit may be a dynamic storage unit, then refer to FIG. 6 , which is a schematic structural diagram of another embodiment of the storage control module provided by the present application. The storage control module 40 includes a first interface unit 41 , a read control unit 42 , a write control unit 43 , a second interface unit 44 and a refresh unit 45 . Wherein, the refresh unit 45 is connected to the second interface unit 44, and the refresh unit 45 is used for refreshing the storage unit. The dynamic storage unit may be a DRAM (Dynamic Random Access Memory, dynamic random access memory) unit.

It can be understood that a dynamic memory cell temporarily stores information by storing charges through a gate capacitance. Because the stored information charge leaks after all, and the charge amount cannot be supplemented by the power supply through the load tube like the static storage element, the information will be lost after a long time. For this reason, the refresh unit 45 is required to refresh the storage unit. That is to charge the gate according to a certain rule, and replenish the information charge of the gate capacitance as needed.

When multiple storage control modules 40 are applied to the storage access circuit 100 in any of the above-mentioned embodiments, multiple storage control modules 40 are connected to a multiplexer 30, which can provide higher bandwidth during storage access, and then storage access The circuit 100 can realize high-bandwidth storage access to large-capacity DRAM units. When there is a computing engine 20 in the storage access circuit 100, the multiplexer 30 can output high-bandwidth storage access data to the routing node, and the routing node 101 can reasonably distribute the storage access data to at least one computing engine 20 on the routing node, Thereby improving computing performance.

Referring to FIG. 7 , FIG. 7 is a schematic structural diagram of an embodiment of an integrated chip provided by the present application. The integrated chip 200 includes a logic module 201 and a storage array module 202 .

Wherein, the logic module 201 is integrated with a storage access circuit. The storage access circuit may be the storage access circuit 100 in any of the foregoing embodiments.

The logic module 201 is connected to the storage array module 202; wherein, the storage array module 202 is integrated with a storage unit.

In some embodiments, the memory array module 202 may be a dynamic random memory array module.

The storage control module 40 in the storage access circuit 100 is connected to the storage unit, and is used for reading and writing operations on the storage unit.

The logic module 201 and the storage array module 202 are stacked, and the storage control module 40 of the storage access circuit 100 is connected to the storage unit integrated on the storage array module 202, so that the wiring between the storage control module 40 and the storage unit is shortened, and the storage capacity can be improved. unit access speed, reducing power consumption and improving overall performance.

It can be understood that, specifically, the stacking manner may be set according to actual sizes of the logic module 201 and the storage array module 202 . When the integrated chip 200 includes a plurality of logic modules 201 and a plurality of storage array modules 202, the logic modules 201 and the storage array modules 202 may be stacked on each other. For example, a storage array module 202 is arranged between two logic modules 201 . For example, a logic module 201 is arranged between two storage array modules 202 . Specifically, the logic module 201 and the storage array module 202 are bonded and connected by 3-dimensional bonding technology, so that the storage access circuit in the logic module 201 can be directly connected with the storage unit in the storage array module 202, realizing high bandwidth, low Power memory access structure.

The above-mentioned logic module 201 and storage array module 202 may be made of a wafer (Wafer) or a die (Die) or a chip (chip).

In this embodiment, when the storage access circuit 100 in the integrated chip 200 is accessing storage, at least two storage control 40 modules connected to each multiplexer 30 can provide higher bandwidth, thereby enabling large-scale High-bandwidth memory access for capacity dynamic random access memory units. When there is a computing engine 20 in the storage access circuit 100, the multiplexer 30 can output high-bandwidth storage access data to the routing node, and the routing node can reasonably distribute the storage access data to at least one computing engine 20 on the routing node, thereby Improve computing performance.

In some embodiments, the integrated chip 200 can be used as a storage device such as a memory stick or a hard disk.

Referring to FIG. 8 , FIG. 8 is a schematic structural diagram of an embodiment of an electronic device provided by the present application. The electronic device 300 includes an integrated chip 200 . The integrated chip 200 is like the integrated chip 200 in any of the above-mentioned embodiments.

The integrated chip 200 includes a logic module and a storage array module, wherein the above-mentioned storage access circuit is integrated on the logic module, and the storage array module is connected to the logic module. In a specific embodiment, the logic module and the storage array module are stacked and bonded. Specifically, the logic module and the storage array module are bonded and connected by 3-dimensional bonding technology, so that the storage access circuit in the logic module can be directly connected with the storage unit in the storage array module, realizing high-bandwidth, low-power storage access structure.

In this embodiment, when the integrated chip 200 in the electronic device 300 is accessing storage, at least two storage control 40 modules connected to each multiplexer 30 can provide higher bandwidth, and then the storage access circuit 100 can realize High-bandwidth storage access to large-capacity dynamic random storage units, so that the multiplexer can output high-bandwidth storage access data to the routing node, and the routing node can reasonably allocate storage access data to at least one computing engine on the routing node, thereby Improve computing performance.

Referring to FIG. 9 , FIG. 9 is a schematic flowchart of an embodiment of a storage access method provided by the present application. The method is implemented based on any of the above storage access circuits 100, and the method includes:

Step 91: the routing node receives the data access instruction, and determines at least one corresponding multiplexer according to the data access instruction.

Wherein, the data access instruction is sent by the computing engine or the external processing module.

Step 92: The multiplexer determines at least one corresponding storage control module according to the data access instruction.

It can be understood that data may be stored in different storage units, so the storage control module corresponding to the connected storage unit needs to be determined before data can be read.

Step 93: The storage control module acquires data from the correspondingly connected storage unit according to the data access instruction and sends it to the multiplexer.

Step 94: The multiplexer sends the data to the routing node.

The multiplexer synthesizes the data sent by each storage control module, and sends the synthesized data to the routing node, and the routing node sends the synthesized data to the computing engine.

Description will be made in conjunction with the storage access circuit 100 in any of the above-mentioned embodiments:

The corresponding functional modules or external processing modules in the computing engine can generate data access instructions and send them to the routing node. The routing node determines the corresponding multiple or single multiplexers according to the data access instructions and sends the data access instructions to the multiplexers. multiplexer. The multiplexer allocates according to the data access instruction to determine corresponding multiple or single storage control modules, and sends the data access instruction to the storage control module. The storage control module acquires data from the correspondingly connected storage unit according to the data access instruction, and sends the data to the multiplexer. The multiplexer synthesizes the data sent by multiple or single storage control modules, and sends the synthesized data to the routing node, and the routing node sends the synthesized data to the computing engine or the external processing module. After the corresponding function module or external processing module in the calculation engine obtains the synthesized data, it decodes the synthesized data to obtain the data before synthesis. Then perform calculations on these data.

In this embodiment, when performing large-capacity storage access, a multiplexer is used to connect at least two storage control modules to provide higher storage access bandwidth, thereby realizing high-speed access to large-capacity DRAM units. Bandwidth storage access, so that the multiplexer can output high-bandwidth storage access data to routing nodes, and routing nodes can reasonably allocate storage access data to computing engines or external processing modules connected to routing nodes, thereby improving computing performance.

Referring to FIG. 10 , FIG. 10 is a schematic flowchart of another embodiment of a storage access method provided by the present application. The method is implemented based on any of the above storage access circuits 100, and the method includes:

Step 101: the routing node receives a data write instruction, and determines at least one corresponding multiplexer according to the data write instruction.

Wherein, the data writing instruction is sent by the computing engine or the external processing module.

Step 102: The multiplexer determines at least one corresponding storage control module according to the data write instruction.

It can be understood that data may need to be written into different storage units, so it is necessary to determine the storage control module correspondingly connected to the storage unit before corresponding writing of data can be performed.

For example, when large-capacity data is written, a single storage unit cannot fully store it, and multiple storage units are needed, so the specific storage unit needs to be determined according to the capacity of the written data.

Step 103: the storage control module obtains the data to be written according to the data writing instruction, and writes the data to be written into the storage unit connected to the storage control module.

At this time, when large-capacity data is written, data can be written simultaneously through multiple storage control modules, and the data to be written can be written into the storage unit connected to the storage control module, which can shorten the time for writing data. time.

The corresponding functional modules or external processing modules in the computing engine can generate data write instructions and send them to the routing node. The routing node determines the corresponding multiple or single multiplexers according to the data write instructions, and sends the data write instructions to to the multiplexer. The multiplexer allocates according to the data writing instruction to determine corresponding multiple or single storage control modules, and sends the data writing instruction to the storage control modules. The storage control module obtains the data to be written according to the data writing instruction, and writes the data to be written into the correspondingly connected storage unit.

In this embodiment, when large-capacity data is written, a multiplexer is used to connect with at least two storage control modules to provide higher storage access bandwidth, thereby realizing the large-capacity DRAM unit High-bandwidth storage access, so that the multiplexer can output high-bandwidth storage access data to routing nodes, and routing nodes can reasonably allocate storage access data to computing engines or external processing modules connected to routing nodes, thereby improving computing performance .

The above is only the implementation mode of this application, and does not limit the scope of patents of this application. Any equivalent structure or equivalent process transformation made by using the description of this application and the contents of the accompanying drawings, or directly or indirectly used in other related technical fields, All are included in the scope of patent protection of the present application in the same way.

Claims

A storage access circuit, characterized in that the storage access circuit includes:

a network element comprising at least one routing node;

multiplexer;

A storage control module, used for connecting the storage unit;

Wherein, each of the routing nodes is connected to at least one of the multiplexers, and each of the multiplexers is connected to at least two of the storage control modules, so as to perform multiplexing on at least two of the storage control modules. multiplexing, and then perform storage access to the storage unit connected to the storage control module.
The storage access circuit according to claim 1, characterized in that,

Each of said routing nodes is connected to at most 4 other routing nodes.
The storage access circuit according to claim 1, characterized in that,

At least two routing nodes are distributed in an array in the form of M rows*N columns, and each routing node is connected to other routing nodes adjacent in the row or column direction, wherein M and N are positive integers.
The storage access circuit according to claim 3, characterized in that,

M is 3, N is 3;

Each of the routing nodes is connected to 2 of the multiplexers, and each of the multiplexers is connected to 8 of the storage control modules.
The storage access circuit according to claim 3, characterized in that,

M is 4, N is 4;

Each of the routing nodes is connected to 4 of the multiplexers, and each of the multiplexers is connected to 16 of the storage control modules.
The storage access circuit according to claim 1, characterized in that,

The storage control module includes:

a first interface unit, connected to the multiplexer;

A read control unit, connected to the first interface unit, for controlling the reading of data in the storage unit;

A write control unit, connected to the first interface unit, for controlling writing data to the storage unit;

The second interface unit is connected to the read control unit, the write control unit and the storage unit.
The storage access circuit according to claim 6, characterized in that,

The storage control module further includes a refresh unit connected to the second interface unit, and the refresh unit is used to refresh the storage unit.
The storage access circuit according to claim 1, characterized in that,

The data bit width of the storage control module is 128bit, and the frequency is 400MHz.
The storage access circuit according to claim 1, further comprising: a computing engine, each of the routing nodes is connected to at least one computing engine.
The storage access circuit according to claim 2, wherein the distance between the routing node and other routing nodes connected to the routing node is the same.
The storage access circuit according to claim 2, wherein the data transmission time between the routing node and other routing nodes connected to the routing node is the same.
An integrated chip, characterized in that the integrated chip includes: a logic module and a storage array module;

The logic module is integrated with a storage access circuit; the storage access circuit includes: a network unit, and the network unit includes at least one routing node;

multiplexer;

A storage control module, used for connecting the storage unit;

Wherein, each of the routing nodes is connected to at least one of the multiplexers, and each of the multiplexers is connected to at least two of the storage control modules, so as to perform multiplexing on at least two of the storage control modules. Multiplexing, and then performing storage access to the storage unit connected to the storage control module;

The storage array module is integrated with the storage unit, and the logic module is connected to the storage array module by stacking and bonding.
The integrated chip according to claim 12, characterized in that,

The storage array module is a dynamic random storage array module.
The integrated chip according to claim 12, characterized in that,

each of said routing nodes is connected to at most 4 other routing nodes;

Wherein, the distance between the routing node and other routing nodes connected to the routing node is the same; and/or

The data transmission time between the routing node and other routing nodes connected to the routing node is the same.
The integrated chip according to claim 12, wherein at least two of the routing nodes are distributed in an array in the form of M rows*N columns, and each of the routing nodes is adjacent to other routing nodes in the row direction or column direction Connection, where M and N are positive integers.
A storage access method, characterized in that the method comprises:

The routing node receives the data access instruction, and determines at least one corresponding multiplexer according to the data access instruction;

The multiplexer determines at least one corresponding storage control module according to the data access instruction;

The storage control module acquires data from the correspondingly connected storage unit according to the data access instruction and sends it to the multiplexer;

The multiplexer sends the data to the routing node.
The method according to claim 16, wherein the step of the multiplexer sending the data to the routing node comprises:

The multiplexer synthesizes the data, and sends the synthesized data to the routing node.
The method according to claim 17, wherein after the step of sending the data to the routing node by the multiplexer, further comprising:

The routing node sends the synthesized data to the computing engine;

The calculation engine decodes the synthesized data, and performs corresponding calculations based on the decoded data.
The method according to claim 16, further comprising:

The routing node receives a data write instruction, and determines at least one corresponding multiplexer according to the data write instruction;

The multiplexer determines at least one corresponding storage control module according to the data write instruction;

The storage control module acquires data to be written according to the data write instruction, and writes the data to be written into the storage unit connected to the storage control module.
The method according to claim 19 is characterized in that, before the step of the routing node receiving the data writing instruction, comprising:

The computing engine generates the write instruction and sends the write instruction to the routing node.