CN215341078U - Memory access circuit, integrated chip and electronic equipment - Google Patents
Memory access circuit, integrated chip and electronic equipment Download PDFInfo
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- CN215341078U CN215341078U CN202121507615.5U CN202121507615U CN215341078U CN 215341078 U CN215341078 U CN 215341078U CN 202121507615 U CN202121507615 U CN 202121507615U CN 215341078 U CN215341078 U CN 215341078U
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Abstract
The application relates to the technical field of electronic circuits, and discloses a storage access circuit, an integrated chip and electronic equipment. The memory access circuit includes a network element, a multiplexer, and a memory control module. Each routing node is connected with at least one multiplexer, each multiplexer is connected with at least two storage control modules to multiplex the at least two storage control modules, and then storage access is carried out on the storage units connected with the storage control modules. By the mode, high-bandwidth storage access to the large-capacity storage unit can be realized.
Description
Technical Field
The present application relates to the field of electronic circuit technology, and more particularly, to a memory access circuit, an integrated chip, and an electronic device.
Background
With the rapid increase of the application computing scale, the bandwidth and power consumption overhead of memory access become important factors limiting the development of the scaled computing circuit.
SUMMERY OF THE UTILITY MODEL
The technical problem that this application mainly solved is to provide storage access circuit, integrated chip and electronic equipment, can realize the high bandwidth storage access to the large capacity memory cell.
In order to solve the above problem, one technical solution adopted by the present application is to provide a memory access circuit, including: a network element comprising at least one routing node; a multiplexer; the storage control module is used for connecting the storage unit; each routing node is connected with at least one multiplexer, each multiplexer is connected with at least two storage control modules to multiplex the at least two storage control modules, and then storage access is carried out on the storage units connected with the storage control modules.
Wherein each routing node is connected to at most 4 other routing nodes.
The routing nodes are distributed in an array mode of M rows by N columns, each routing node is connected with other adjacent routing nodes in the row direction or the column direction, and M and N are positive integers.
Wherein M is 3 and N is 3; each routing node is connected to 2 multiplexers, and each multiplexer is connected to 8 memory control modules.
Wherein M is 4 and N is 4; each routing node is connected to 4 multiplexers, each multiplexer is connected to 16 memory control modules.
Wherein, the storage control module includes: the first interface unit is connected with the multiplexer; the reading control unit is connected with the first interface unit and is used for controlling and reading the data in the storage unit; the writing control unit is connected with the first interface unit and used for controlling the writing of data into the storage unit; and the second interface unit is connected with the read control unit, the write control unit and the storage unit.
The memory control module further comprises a refreshing unit connected with the second interface unit, and the refreshing unit is used for refreshing the memory unit.
The data bit width of the storage control module is 128 bits, and the frequency is 400 MHz.
Wherein the memory access circuit further comprises: and each routing node is connected with at least one operation engine.
In order to solve the above problem, another technical solution adopted by the present application is to provide an integrated chip, including: the logic module is integrated with the storage access circuit provided by the technical scheme; and the logic module is connected with the storage array module.
The storage array module is a dynamic random access storage array module.
In order to solve the above problem, another technical solution adopted by the present application is to provide an electronic device, where the electronic device includes an integrated chip, and the integrated chip includes: the logic module is integrated with the storage access circuit provided by the technical scheme; and the logic module is connected with the storage array module.
The beneficial effect of this application is: the memory access circuit, the integrated chip and the electronic device are different from the prior art. The storage access circuit can multiplex at least two storage control modules by utilizing the mode that each routing node is connected with at least one multiplexer, each multiplexer is connected with at least two storage control modules, and then storage access is carried out on the storage units connected with the storage control modules.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of an embodiment of a memory access circuit provided herein;
FIG. 2 is a schematic diagram of another embodiment of a memory access circuit provided herein;
FIG. 3 is a schematic structural diagram of an embodiment of a plurality of routing nodes provided herein;
FIG. 4 is a schematic diagram of another embodiment of a memory access circuit provided herein;
FIG. 5 is a schematic structural diagram of an embodiment of a storage control module provided herein;
FIG. 6 is a schematic structural diagram of another embodiment of a storage control module provided herein;
FIG. 7 is a schematic structural diagram of an embodiment of an integrated chip provided herein;
FIG. 8 is a schematic structural diagram of an embodiment of an electronic device provided in the present application;
FIG. 9 is a schematic flow chart diagram illustrating an embodiment of a storage access method provided herein;
fig. 10 is a schematic flowchart of another embodiment of a storage access method provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a memory access circuit provided in the present application. The memory access circuit 100 includes a network element 10, a multiplexer 30 and a memory control module 40.
Each routing node is connected to at least one multiplexer 30, and each multiplexer 30 is connected to at least two storage control modules 40, so as to multiplex at least two storage control modules 40, and further perform storage access on the storage units connected to the storage control modules 40.
Wherein the network element 10 comprises at least one routing node.
In some embodiments, the network element 10 may be a network on chip. Such as a two-dimensional mesh network-on-chip. Network on chip (NoC) is a new communication method for System on chip (SoC). It is a major component of multi-core technology. The NoC method brings a brand new on-chip communication method, which is significantly superior to the performance of the traditional bus-type system (bus). The NoC-based system can better adapt to a globally asynchronous locally synchronous clock mechanism used in a future complex multi-core SoC design.
The multiplexer 30 is capable of receiving a plurality of input signals, combining a single output signal in a recoverable manner for each input signal and selecting data read or write from a corresponding channel in accordance with the signal.
The memory control module 40 is used to connect the memory units to control the memory units, such as reading data from the memory units or writing data to the memory units.
In some embodiments, the number of routing nodes, multiplexers 30 and storage control modules 40 may be set according to actual needs. Further, the number of multiplexers 30 connected per routing node may be the same, e.g., 1, 2, 3, 4, 5, or 6 multiplexers 30 are connected per routing node. In another application scenario, the number of multiplexers 30 connected to each routing node may be different, for example, a first routing node is connected to 2 multiplexers 30, a second routing node is connected to 3 multiplexers 30, a third routing node is connected to 4 multiplexers 30, and a fourth routing node is connected to 2 multiplexers 30.
Further, the number of memory control modules 40 connected to each multiplexer 30 may be the same, such as 2, 4, 8, or 16 memory control modules 40 connected to each multiplexer 30. The number of memory control modules 40 connected to each multiplexer 30 may also be different, for example, a first multiplexer 30 is connected to 4 memory control modules 40, a second multiplexer 30 is connected to 8 memory control modules 40, a third multiplexer 30 is connected to 16 memory control modules 40, and a fourth multiplexer 30 is connected to 32 memory control modules 40.
The routing node in the memory access circuit 100 is connected to an external processing module, and based on this, the read flow of the entire memory access circuit 100 will be described:
the external processing module may generate and send data access instructions to the routing node, which determines a corresponding plurality or single multiplexer 30 according to the data access instructions and sends the data access instructions to the multiplexer 30. The multiplexer 30 performs allocation according to the data access instruction to determine a corresponding plurality or single memory control module 40 and sends the data access instruction to the memory control module 40. The memory control module 40 retrieves data from the corresponding connected memory cells according to the data access instruction and transmits the data to the multiplexer 30. The multiplexer 30 combines the data transmitted from the plurality of or single storage control modules 40 and transmits the combined data to the routing node, which transmits the combined data to the external processing module. And after the external processing module acquires the synthetic data, decoding the synthetic data to obtain the data before synthesis. And then performs an operation based on these data.
The write flow of the entire memory access circuit 100 is explained:
the external processing module may generate a data write command and send it to the routing node, which determines a corresponding plurality or single multiplexer 30 according to the data write command and sends the data write command to the multiplexer 30. The multiplexer 30 performs allocation according to the data write command to determine a corresponding plurality or single storage control module 40, and sends the data write command to the storage control module 40. The storage control module 40 acquires data to be written according to the data writing instruction, and writes the data to be written into the correspondingly connected storage unit.
In the present embodiment, the memory access circuit 100 is capable of multiplexing at least two memory control modules 40 by connecting at least one multiplexer 30 to each routing node, and connecting at least two memory control modules 40 to each multiplexer 30. At the time of memory access, at least two memory control modules 40 connected to each multiplexer 30 can provide a higher bandwidth, thereby enabling high bandwidth memory access to mass storage units.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a memory access circuit provided in the present application. The memory access circuit 100 includes a network element 10, an arithmetic engine 20, a multiplexer 30, and a memory control module 40.
Wherein the network element 10 comprises at least one routing node.
The arithmetic engine 20 may include at least one of a CPU (central processing unit), a DSP (Digital Signal Processor), and a GPU (graphics processing unit).
The multiplexer 30 is capable of receiving a plurality of input signals, combining a single output signal in a recoverable manner for each input signal and selecting data read or write from a corresponding channel in accordance with the signal.
The memory control module 40 is used to connect the memory units to control the memory units, such as reading data from the memory units or writing data to the memory units.
Wherein, each routing node is connected with at least one arithmetic engine 20 and at least one multiplexer 30, and each multiplexer 30 is connected with a plurality of storage control modules 40 to multiplex the plurality of storage control modules 40. The routing node is used for controlling data transmission. The data output from the multiplexer 30 is transmitted to the operation engine 20 through the routing node, so that the operation engine 20 performs corresponding operations based on the data.
In some embodiments, the number of routing nodes, arithmetic engine 20, multiplexer 30 and memory control module 40 may be set according to actual needs. In an application scenario, the number of calculation engines 20 connected to each routing node may be the same, such as 2, 3, 4, 5 or 6 calculation engines 20 connected to each routing node. In another application scenario, the number of the operation engines 20 connected to each routing node may be different, for example, a first routing node is connected to 2 operation engines 20, a second routing node is connected to 3 operation engines 20, a third routing node is connected to 4 operation engines 20, and a fourth routing node is connected to 2 operation engines 20.
Further, the number of multiplexers 30 connected per routing node may be the same, e.g., 1, 2, 3, 4, 5, or 6 multiplexers 30 are connected per routing node. In another application scenario, the number of multiplexers 30 connected to each routing node may be different, for example, a first routing node is connected to 2 multiplexers 30, a second routing node is connected to 3 multiplexers 30, a third routing node is connected to 4 multiplexers 30, and a fourth routing node is connected to 2 multiplexers 30.
Further, the number of memory control modules 40 connected to each multiplexer 30 may be the same, such as 2, 4, 8, or 16 memory control modules 40 connected to each multiplexer 30. The number of memory control modules 40 connected to each multiplexer 30 may also be different, for example, a first multiplexer 30 is connected to 4 memory control modules 40, a second multiplexer 30 is connected to 8 memory control modules 40, a third multiplexer 30 is connected to 16 memory control modules 40, and a fourth multiplexer 30 is connected to 32 memory control modules 40.
In an application scenario, the read flow of the entire memory access circuit 100 is described as follows:
the corresponding functional module in the arithmetic engine 20 can generate a data access instruction and send the data access instruction to the routing node, the routing node determines a corresponding plurality or single multiplexer 30 according to the data access instruction, and sends the data access instruction to the multiplexer 30. The multiplexer 30 performs allocation according to the data access instruction to determine a corresponding plurality or single memory control module 40 and sends the data access instruction to the memory control module 40. The memory control module 40 retrieves data from the corresponding connected memory cells according to the data access instruction and transmits the data to the multiplexer 30. The multiplexer 30 synthesizes data transmitted from a plurality of or a single storage control module 40 and transmits the synthesized data to the routing node, which transmits the synthesized data to the arithmetic engine 20. After the corresponding functional module in the operation engine 20 obtains the synthesized data, the synthesized data is decoded to obtain the data before synthesis. And then performs an operation based on these data.
In an application scenario, the write flow of the entire memory access circuit 100 is described:
the corresponding functional module in the arithmetic engine 20 may generate a data write command and send the data write command to the routing node, and the routing node determines a corresponding plurality or single multiplexer 30 according to the data write command and sends the data write command to the multiplexer 30. The multiplexer 30 performs allocation according to the data write command to determine a corresponding plurality or single storage control module 40, and sends the data write command to the storage control module 40. The storage control module 40 acquires data to be written according to the data writing instruction, and writes the data to be written into the correspondingly connected storage unit.
In the present embodiment, the memory access circuit 100 is capable of multiplexing at least two memory control modules 40 by connecting at least one multiplexer 30 to each routing node, and connecting at least two memory control modules 40 to each multiplexer 30. During storage access, at least two storage control 40 modules connected with each multiplexer 30 can provide higher bandwidth, so that high-bandwidth storage access to a large-capacity storage unit can be realized, the multiplexer 30 can output high-bandwidth storage access data to a routing node, and the routing node can reasonably distribute the storage access data to any one or more operation engines 20 on the routing node, so that the operation performance is improved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a plurality of routing nodes provided in the present application. The explanation is given by taking 9 routing nodes in fig. 3 as an example:
routing nodes include A, B, C, D, E, F, G, H and I. The routing node A is connected with a routing node B and a routing node D, the routing node B is connected with the routing node A, the routing node C and a routing node E, the routing node C is connected with the routing node B and a routing node F, the routing node E is connected with the routing node A, the routing node E and a routing node G, the routing node E is connected with the routing node B, the routing node D, the routing node F and a routing node H, the routing node F is connected with the routing node C, the routing node E and a routing node I, the routing node G is connected with the routing node D and the routing node H, the routing node H is connected with the routing node E, the routing node G and the routing node I, and the routing node I is connected with the routing node H and the routing node F.
Therein, it can be seen that there are cases where a routing node connects 2 other routing nodes, 3 other routing nodes, or 4 other routing nodes. It can be understood that, due to the position relationship of the routing nodes, the number of other routing nodes connected to the routing nodes at different positions is different because only part of the routing nodes in the edge have other routing nodes.
Thus, each routing node is connected to at most 4 other routing nodes.
Further, when the network element includes at least two routing nodes, the at least two routing nodes are distributed in an array form of M rows x N columns, and each routing node is connected to other routing nodes adjacent to each other in the row direction or the column direction, where M and N are positive integers. It can be understood that if a plurality of routing nodes are distributed in an array of M rows by N columns, it is more consistent with the efficiency of data transmission between the routing nodes to connect up to 4 other routing nodes to each routing node.
The description is made with reference to fig. 3:
the distances from the routing node E to the routing node B, the routing node D, the routing node F, and the routing node H are the same, and the data transmission time is the same in the case where the wiring materials are the same.
If the routing node E is further connected to the routing node a, the distance between the routing node E and the routing node a is greater than the distances between the routing node E and the routing nodes B, D, F and H, which adversely affects the global adjustment of the network element 10.
Therefore, at least two routing nodes are arrayed and distributed in M rows by N columns, so that the distance between every two routing nodes is the same, and not only can the flow be reduced in the manufacturing process, but also the performance of the network unit 10 can be improved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of another embodiment of a memory access circuit provided in the present application. The network element comprises 9 routing nodes, which are arrayed in M rows by N columns, where M may be 3 and N may be 3. Routing nodes include A, B, C, D, E, F, G, H and I.
Each routing node is connected to 2 multiplexers 30 and each multiplexer 30 is connected to 8 memory control modules 40. Each routing node is connected to 2 arithmetic engines 20. The number of memory control modules 40 in the memory access circuit 100 is 144. The number of multiplexers 30 is 18, and the number of arithmetic engines 20 is 18.
Taking the data bit width of the memory control module 40 as 128 bits and the frequency as 400MHz as an example, the bandwidth of a single memory control module 40 is (128 × 400/8) MBps ═ 6.4 GB/s. The total bandwidth of the memory access circuit 100 is 144 x 6.4GB/s 921.6 GB/s.
In this embodiment, 144 memory control modules 40 can provide 921.6GB/s of bandwidth, so that the memory access circuit 100 can implement high-bandwidth memory access to a large-capacity memory unit, so that the multiplexer 30 can output high-bandwidth memory access data to the routing node, and the routing node can reasonably allocate the memory access data to any one or more operation engines 20 on the routing node, thereby improving the operation performance.
In other embodiments, the network element includes 16 routing nodes, arrayed in M rows by N columns, where M may be 4 and N may be 4. Or M may be 2 and N may be 8.
The following examples are given for M being 4 and N being 4:
each routing node is connected to 4 multiplexers 30 and each multiplexer 30 is connected to 16 memory control modules. Each routing node is connected to 4 arithmetic engines 20. The number of memory control modules 40 in memory access circuit 100 is 1024. The number of multiplexers 30 is 64, and the number of arithmetic engines 20 is 64.
Taking the data bit width of the memory control module 40 as 128 bits and the frequency as 400MHz as an example, the bandwidth of a single memory control module 40 is (128 × 400/8) MBps ═ 6.4 GB/s. The total bandwidth of the memory access circuit 100 is 1024 × 6.4GB/s 6553.6 GB/s.
In this embodiment, 1024 memory control modules 40 can provide 6553.6GB/s of bandwidth, so that the memory access circuit 100 can implement high-bandwidth memory access to a large-capacity memory unit, so that the multiplexer 30 can output high-bandwidth memory access data to the routing node, and the routing node can reasonably allocate the memory access data to any one or more operation engines 20 on the routing node, thereby improving the operation performance.
In other embodiments, the data bit width of the memory control module 40 may be 64 bits with a frequency of 900 MHz.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a memory control module provided in the present application. The storage control module 40 includes a first interface unit 41, a read control unit 42, a write control unit 43, and a second interface unit 44.
Wherein, the first interface unit 41 is connected to the multiplexer 30; the reading control unit 42 is connected with the first interface unit 41 and is used for controlling the reading of the data in the storage unit; the write control unit 43 is connected to the first interface unit 41, and is used for controlling the writing of data into the storage unit; the second interface unit 44 connects the read control unit 42, the write control unit 43, and the storage unit.
When the plurality of memory control modules 40 are applied to the memory access circuit 100 in any of the above embodiments, the plurality of memory control modules 40 are connected to a multiplexer 30, which can provide higher bandwidth during memory access, thereby realizing high bandwidth memory access to mass storage units. When the operation engines 20 exist in the storage access circuit 100, the multiplexer 30 can output high-bandwidth storage access data to the routing node, and the routing node can reasonably distribute the storage access data to any one or more operation engines 20 on the routing node, so that the operation performance is improved.
Further, if the memory cell may be a dynamic memory cell, referring to fig. 6, fig. 6 is a schematic structural diagram of another embodiment of the memory control module provided in the present application. The memory control module 40 includes a first interface unit 41, a read control unit 42, a write control unit 43, a second interface unit 44, and a refresh unit 45. The refreshing unit 45 is connected to the second interface unit 44, and the refreshing unit 45 is used for refreshing the memory unit. The Dynamic Memory cells may be DRAM (Dynamic Random Access Memory) cells.
It is understood that the dynamic memory cell stores charge through the gate capacitor to temporarily store information. Since the stored information charges are leaked, the charges cannot be supplemented by a power supply through a load tube like a static memory cell, and the information is lost after a long time, the memory cell needs to be refreshed by the refreshing unit 45, namely, the grid electrode is charged according to a certain rule, and the information charges of the grid electrode capacitor are supplemented as required.
When the plurality of memory control modules 40 are applied to the memory access circuit 100 in any of the above embodiments, the plurality of memory control modules 40 are connected to the multiplexer 30, so that a higher bandwidth can be provided during memory access, and the memory access circuit 100 can realize high bandwidth memory access to a large-capacity dynamic random access memory unit. When the operation engines 20 exist in the storage access circuit 100, the multiplexer 30 can output high-bandwidth storage access data to the routing node, and the routing node can reasonably distribute the storage access data to at least one operation engine 20 on the routing node, so that the operation performance is improved.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of an integrated chip provided in the present application. The integrated chip 200 includes a logic module 201 and a memory array module 202.
Wherein the logic module 201 has a memory access circuit integrated thereon. The memory access circuitry may be the memory access circuitry 100 in any of the embodiments described above.
The logic module 201 is connected with the storage array module 202; the memory array module 202 has memory cells integrated thereon.
In some embodiments, the memory array module 202 may be a dynamic random access memory array module.
The memory control module 40 in the memory access circuit 100 is connected to the memory cells for performing read and write operations on the memory cells.
The logic module 201 and the storage array module 202 are arranged in a stacked manner, and the storage control module 40 of the storage access circuit 100 is connected with the storage unit integrated on the storage array module 202, so that the wiring between the storage control module 40 and the storage unit is shortened, the access speed to the storage unit can be improved, the power consumption is reduced, and the overall performance is improved.
It is understood that the specific stacking manner may be set according to the actual size of the logic module 201 and the storage array module 202. When a plurality of logic modules 201 and a plurality of memory array modules 202 are included in the integrated chip 200, the logic modules 201 and the memory array modules 202 may be stacked on each other. For example, a memory array module 202 is disposed between two logic modules 201. For example, a logic module 201 is disposed between two storage array modules 202. Specifically, the logic module 201 and the memory array module 202 are bonded and connected by a 3-dimensional bonding technology, so that the memory access circuit in the logic module 201 is directly connected with the memory unit in the memory array module 202, and a memory access structure with high bandwidth and low power consumption is realized.
The logic module 201 and the memory array module 202 may be fabricated from a Wafer (Wafer) or a Die (Die) or a chip (chip).
In the present embodiment, in the memory access circuit 100 of the integrated chip 200, at least two memory control 40 modules connected to each multiplexer 30 can provide higher bandwidth during memory access, so as to implement high bandwidth memory access to the large-capacity dynamic random access memory unit. When the operation engines 20 exist in the storage access circuit 100, the multiplexer 30 can output high-bandwidth storage access data to the routing node, and the routing node can reasonably distribute the storage access data to at least one operation engine 20 on the routing node, so that the operation performance is improved.
In some embodiments, the integrated chip 200 may be applied as a memory bank, a hard disk, or other storage devices.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of an electronic device provided in the present application. The electronic device 300 comprises an integrated chip 200. The integrated chip 200 is the integrated chip 200 in any of the above embodiments.
The integrated chip 200 includes a logic module integrated with the memory access circuit and a memory array module connected to the logic module. In one embodiment, the logic module is stacked and bonded with the memory array module. Specifically, the logic module and the memory array module are bonded and connected through a 3-dimensional bonding technology, so that a memory access circuit in the logic module can be directly connected with a memory unit in the memory array module, and a memory access structure with high bandwidth and low power consumption is realized.
In this embodiment, when the integrated chip 200 in the electronic device 300 performs memory access, at least two memory control modules 40 connected to each multiplexer 30 can provide a higher bandwidth, and the memory access circuit 100 can implement high-bandwidth memory access to a large-capacity dynamic random access memory unit, so that the multiplexers can output high-bandwidth memory access data to the routing node, and the routing node can reasonably allocate the memory access data to at least one operation engine on the routing node, thereby improving the operation performance.
Referring to fig. 9, fig. 9 is a schematic flowchart of an embodiment of a storage access method provided in the present application. The method is implemented based on any one of the memory access circuits 100, and the method comprises the following steps:
step 91: the routing node receives the data access instruction and determines a corresponding at least one multiplexer according to the data access instruction.
Wherein, the data access instruction is sent by the arithmetic engine or the external processing module.
And step 92: the multiplexer determines a corresponding at least one memory control module according to the data access instruction.
It can be understood that data may be stored in different storage units, so that the storage control module corresponding to the connected storage unit needs to be determined to read the data.
Step 93: and the storage control module acquires data from the correspondingly connected storage units according to the data access instruction and sends the data to the multiplexer.
Step 94: the multiplexer sends the data to the routing node.
The multiplexer synthesizes the data sent by each storage control module, sends the synthesized data to the routing node, and the routing node sends the synthesized data to the operation engine.
The description is made in conjunction with the memory access circuit 100 in any of the embodiments above:
the corresponding functional module or external processing module in the operation engine can generate a data access instruction and send the data access instruction to the routing node, the routing node determines corresponding multiple or single multiplexers according to the data access instruction, and the data access instruction is sent to the multiplexers. The multiplexer distributes according to the data access instruction to determine a corresponding plurality of or single storage control modules and sends the data access instruction to the storage control modules. And the storage control module acquires data from the correspondingly connected storage units according to the data access instruction and sends the data to the multiplexer. The multiplexer synthesizes data sent by a plurality of or single storage control modules, sends the synthesized data to the routing node, and the routing node sends the synthesized data to the operation engine or the external processing module. And after the corresponding functional module or external processing module in the operation engine acquires the synthetic data, decoding the synthetic data to obtain the data before synthesis. And then performs an operation based on these data.
In this embodiment, when performing a high-capacity storage access, a mode that the multiplexer is connected to at least two storage control modules is used to provide a higher storage access bandwidth, thereby implementing a high-bandwidth storage access to the high-capacity dynamic random access memory unit, so that the multiplexer can output high-bandwidth storage access data to the routing node, and the routing node can reasonably allocate the storage access data to an operation engine or an external processing module connected to the routing node, thereby improving the operation performance.
Referring to fig. 10, fig. 10 is a schematic flowchart of another embodiment of a storage access method provided in the present application. The method is implemented based on any one of the memory access circuits 100, and the method comprises the following steps:
step 101: and the routing node receives the data writing command and determines at least one corresponding multiplexer according to the data writing command.
The data writing instruction is sent by the operation engine or the external processing module.
Step 102: the multiplexer determines the corresponding at least one storage control module according to the data writing instruction.
It can be understood that data may need to be written into different storage units, so that the storage control module corresponding to the connected storage unit needs to be determined to perform corresponding writing of the data.
For example, when writing large-capacity data, a single memory cell cannot store the data completely, and a plurality of memory cells are required, so that a specific memory cell needs to be determined according to the capacity of the written data.
Step 103: and the storage control module acquires data to be written according to the data writing instruction and writes the data to be written into a storage unit connected with the storage control module.
In this case, when writing large-capacity data, data can be written simultaneously by the plurality of memory control modules, and data to be written is written in the memory cells connected to the memory control modules, which can shorten the time for writing data.
In an application scenario, the write flow of the entire memory access circuit 100 is described:
the corresponding functional module or external processing module in the operation engine can generate a data writing instruction and send the data writing instruction to the routing node, the routing node determines corresponding multiple or single multiplexers according to the data writing instruction, and the data writing instruction is sent to the multiplexers. The multiplexer distributes according to the data writing instruction to determine a plurality of or a single corresponding storage control modules, and sends the data writing instruction to the storage control modules. And the storage control module acquires data to be written according to the data writing instruction and writes the data to be written into the correspondingly connected storage units.
In this embodiment, when writing large-capacity data, a mode of connecting the multiplexer and the at least two storage control modules is used to provide a higher storage access bandwidth, and then high-bandwidth storage access to the large-capacity dynamic random access memory unit is realized, so that the multiplexer can output the high-bandwidth storage access data to the routing node, and the routing node can reasonably allocate the storage access data to an operation engine or an external processing module connected to the routing node, thereby improving the operation performance.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (12)
1. A memory access circuit, the memory access circuit comprising:
a network element comprising at least one routing node;
a multiplexer;
the storage control module is used for connecting the storage unit;
each routing node is connected with at least one multiplexer, each multiplexer is connected with at least two storage control modules, so that the at least two storage control modules are multiplexed, and storage access is performed on the storage units connected with the storage control modules.
2. The memory access circuit of claim 1,
each of said routing nodes is connected to at most 4 other routing nodes.
3. The memory access circuit of claim 2,
at least two routing nodes are distributed in an array mode of M rows by N columns, each routing node is connected with other adjacent routing nodes in the row direction or the column direction, and M and N are positive integers.
4. The memory access circuit of claim 3,
m is 3 and N is 3;
each routing node is connected to 2 multiplexers, and each multiplexer is connected to 8 storage control modules.
5. The memory access circuit of claim 3,
m is 4 and N is 4;
each routing node is connected to 4 of the multiplexers, and each multiplexer is connected to 16 of the storage control modules.
6. The memory access circuit of claim 1,
the storage control module includes:
a first interface unit connected to the multiplexer;
the reading control unit is connected with the first interface unit and used for controlling and reading the data in the storage unit;
the writing control unit is connected with the first interface unit and used for controlling the writing of data into the storage unit;
and the second interface unit is connected with the reading control unit, the writing control unit and the storage unit.
7. The memory access circuit of claim 6,
the memory control module further comprises a refreshing unit connected with the second interface unit, and the refreshing unit is used for refreshing the memory unit.
8. The memory access circuit of any of claims 1-7,
the data bit width of the storage control module is 128 bits, and the frequency is 400 MHz.
9. The memory access circuit of claim 1, further comprising: and each routing node is connected with at least one operation engine.
10. An integrated chip, comprising:
a logic module having integrated thereon the memory access circuitry of any of claims 1-9;
and the logic module is connected with the storage array module.
11. The integrated chip of claim 10,
the storage array module is a dynamic random access storage array module.
12. An electronic device, characterized in that the electronic device comprises:
an integrated chip, the integrated chip comprising:
a logic module having integrated thereon the memory access circuitry of any of claims 1-9;
and the logic module is connected with the storage array module.
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| WO2023274032A1 (en) * | 2021-07-02 | 2023-01-05 | 西安紫光国芯半导体有限公司 | Storage access circuit, integrated chip, electronic device and storage access method |
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| WO2023274032A1 (en) * | 2021-07-02 | 2023-01-05 | 西安紫光国芯半导体有限公司 | Storage access circuit, integrated chip, electronic device and storage access method |
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