CN206922735U - One kind is based on ultrashort high speed width covering frequence synthesizer - Google Patents

Abstract

The utility model discloses the one kind in frequency synthesizer technique field to be based on ultrashort high speed width covering frequence synthesizer, including Direct Digital Frequency Synthesizers, the output end of the Direct Digital Frequency Synthesizers is electrically connected with the input of bandpass filter, the output end of the bandpass filter is electrically connected with the input of phase discriminator, PHASE-LOCKED LOOP PLL TECHNIQUE can ensure that the frequency closes circuit output stabilization, high-resolution, the frequency of low spurious, meet requirement of the High-speed frequency hopping communication to frequency quality；The use of bandpass filter, loop filter, effectively inhibit parasitic modulation and phase demodulation to leak, improve frequency degree of purity, reduce communication system and receive threshold effect, improve launch mass；The varactor group back bias voltage of voltage controlled oscillator is provided using low noise digital regulation resistance, greatly extends frequency coverage, by reasonably adjusting bias value, phase lock loop lock on time can be effectively reduced, improve frequency error factor speed.

Description

One kind is based on ultrashort high speed width covering frequence synthesizer

Technical field

Frequency synthesizer technique field is the utility model is related to, is specially that one kind is based on ultrashort high speed width covering frequence Synthesizer.

Background technology

Frequency synthesizer is to utilize one or more reference clock signals, and a large amount of spuious frequencies are produced by various technologies The establishing of signal；Direct Digital Synthesizer is after frequency analog synthesis and indirect frequency synthesis, with digital integration The development of circuit and microelectric technique and the third generation frequency synthesis technique rapidly to emerge, it is using digital signal processing theory as base Plinth, frequency synthesis is completed from the amplitude-phase relation of signal, direct frequency digital synthesis technology has frequency switching time The advantages that short, high resolution, phase place change are continuous, output waveform is flexible and changeable, but its output band scope is limited to clock frequency Rate, the problems such as output factors are big, therefore, I proposes a kind of to be based on ultrashort high speed width covering frequence synthesizer.

Utility model content

The purpose of this utility model is that providing one kind is based on ultrashort high speed width covering frequence synthesizer, with solution State and the problem of output band scope of existing frequency synthesizer is limited to clock frequency, and output factors are big is proposed in background technology.

To achieve the above object, the utility model provides following technical scheme：One kind is based on the wide covering of ultrashort high speed Frequency synthesizer, including Direct Digital Frequency Synthesizers, the output end of the Direct Digital Frequency Synthesizers are electrically connected with band logical The input of wave filter, the output end of the bandpass filter are electrically connected with the input of phase discriminator, the output of the phase discriminator End is electrically connected with the input of loop filter, and the output end of the loop filter is electrically connected with the input of voltage controlled oscillator The input of buffer amplifier and phase discriminator, the VCO is electrically connected in end, the output end of the voltage controlled oscillator The input of device is electrically connected with the output end of low noise amplifier, and the input of the low noise amplifier is electrically connected with low noise digital regulation resistance Output end, the two-way electric connection field programmable gate array of low noise digital regulation resistance, the field programmable gate array Two-way electric connection phase discriminator and Direct Digital Frequency Synthesizers, the input of the field programmable gate array electrically connect respectively The output end of temperature compensating crystal oscillator and Clock Managing Unit is connect, the output end of the temperature compensating crystal oscillator and Clock Managing Unit is electrically connected with directly Connect the input of digital frequency synthesizer.

Preferably, the temperature compensating crystal oscillator and Clock Managing Unit include VCXO units and S3C6410 chips.

Preferably, the phase discriminator includes ADF4002 chips, LE, DATA, CLK, CE of the ADF4002 chips and REFIN pin distinguish series resistor R361, R345, R346, R317 and electric capacity C393, the other end series resistor of the electric capacity C393 R344, AGND, DGND and CPGND pin of the ADF4002 chips are grounded, RFINA, RFINB of the ADF4002 chips, RSET and MUXOUT pin difference serial capacitance C381, electric capacity C382, resistance C363 and resistance C366, the electric capacity C382 and resistance The R363 other end is grounded, and the VP pin of the ADF4002 chips are simultaneously connected to electric capacity C377, C379 and inductance L319, the electricity The other end for holding C377 and C379 is grounded, and the other end of the inductance L319 is serially connected with+5VA chip input powers, described The DVDD pin of ADF4002 chips and the AVDD pin, electric capacity C365, C348, C394, C372 and inductance for being connected to ADF4002 chips L315, described electric capacity C365, C348, C394 and C372 other end are grounded, and the other end of the inductance L315 is serially connected with+ 3V3R chip input powers.

Compared with prior art, the beneficial effects of the utility model are：The program has the following advantages：First, Direct Digital frequency Rate synthesizer exports the pumping signal as phaselocked loop, Reasonable adjustment driving frequency, can make phaselocked loop in wide frequency ranges With identical high-speed transitions speed, meet requirement of the High-speed frequency hopping communication to Frequency Locking；Second, PHASE-LOCKED LOOP PLL TECHNIQUE can protect Demonstrate,prove the frequency and close circuit output stabilization, high-resolution, the frequency of low spurious, meet requirement of the High-speed frequency hopping communication to frequency quality； Third, the use of bandpass filter, loop filter, effectively inhibits parasitic modulation and phase demodulation to leak, it is pure to improve frequency Degree, reduce communication system and receive threshold effect, improve launch mass；Fourth, provide voltage controlled oscillator using low noise digital regulation resistance Varactor group back bias voltage, greatly extend frequency coverage, by reasonably adjusting bias value, can effectively reduce Phase lock loop lock on time, improve frequency error factor speed.

Brief description of the drawings

Fig. 1 is the utility model principle block diagram；

Fig. 2 is the utility model phase detector circuit figure.

In figure：1 Direct Digital Frequency Synthesizers, 2 bandpass filters, 3 phase discriminators, 4 loop filters, 5 voltage controlled oscillators, 6 buffer amplifiers, 7 low noise amplifiers, 8 low noise digital regulation resistances, 9 field programmable gate arrays, 10 temperature compensating crystal oscillators and Clock management Unit.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment obtained, belong to the scope of the utility model protection.

Fig. 1-2 is referred to, the utility model provides a kind of technical scheme：One kind is based on ultrashort high speed width covering frequence Synthesizer, including Direct Digital Frequency Synthesizers 1, the output end of the Direct Digital Frequency Synthesizers 1 are electrically connected with band logical filter The input of ripple device 2, the output end of the bandpass filter 2 are electrically connected with the input of phase discriminator 3, the phase discriminator 3 it is defeated Go out the input that end is electrically connected with loop filter 4, the output end of the loop filter 4 is electrically connected with voltage controlled oscillator 5 The input of buffer amplifier 6 and phase discriminator 3, the pressure is electrically connected in input, the output end of the voltage controlled oscillator 5 The input of controlled oscillator 5 is electrically connected with the output end of low noise amplifier 7, and the input of the low noise amplifier 7 is electrically connected with low noise The output end of digital regulation resistance 8, the two-way electric connection field programmable gate array 9 of low noise digital regulation resistance 8, the scene Programmable gate array 9 distinguishes two-way electric connection phase discriminator 3 and Direct Digital Frequency Synthesizers 1, the field-programmable gate array The input of row 9 is electrically connected with the output end of temperature compensating crystal oscillator and Clock Managing Unit 10, temperature compensating crystal oscillator and the Clock management list The output end of member 10 is electrically connected with the input of Direct Digital Frequency Synthesizers 1.

Wherein, the temperature compensating crystal oscillator and Clock Managing Unit 10 include VCXO units and S3C6410 chips, the phase discriminator 3 include ADF4002 chips, LE, DATA, CLK, CE and REFIN pin difference series resistor R361 of the ADF4002 chips, R345, R346, R317 and electric capacity C393, the electric capacity C393 other end series resistor R344, the ADF4002 chips AGND, DGND and CPGND pin are grounded, and RFINA, RFINB, RSET and MUXOUT pin of the ADF4002 chips concatenate respectively Electric capacity C381, electric capacity C382, resistance C363 and resistance C366, the other end of the electric capacity C382 and resistance R363 are grounded, institute State the VP pin of ADF4002 chips and be connected to electric capacity C377, C379 and inductance L319, the other end of the electric capacity C377 and C379 is equal Ground connection, the other end of the inductance L319 are serially connected with+5VA chip input powers, and the DVDD pin of the ADF4002 chips are simultaneously connected to The AVDD pin of ADF4002 chips, electric capacity C365, C348, C394, C372 and inductance L315, described electric capacity C365, C348, C394 It is grounded with the C372 other end, the other end of the inductance L315 is serially connected with+3V3R chip input powers.

Operation principle：Temperature compensating crystal oscillator in temperature compensating crystal oscillator and Clock Managing Unit 10 provides Direct Digital Frequency Synthesizers 1 Clean accurate frequency reference, its frequency accuracy directly determine the offset of the circuit output frequency；Field-programmable gate array Row 9 and frequency error factor instruction, parallel to Direct Digital Frequency Synthesizers 1, phase discriminator 3, the renewal frequency of low noise digital regulation resistance 8 Frequency dividing ratio, phase demodulation coefficient, potentiometer parameter；Low noise digital regulation resistance 8 exports the specific volume two of voltage controlled oscillator 5 with low noise amplifier 7 Pole pipe group negative bias, rational bias are set, and can be reduced the phase demodulation time of phase discriminator 3, be reduced locking time；Direct Digital Frequency synthesizer 1 divides output drive according to frequency division of the frequency than the clock reference for inputting temperature compensating crystal oscillator and Clock Managing Unit 10 Signal is into bandpass filter 2；Excitation clock signal enters phase discriminator 3 after bandpass filtering；Phase discriminator 3 can be compiled according to scene The phase demodulation coefficient and excitation clock signal that journey gate array 9 is sent into carry out frequency discrimination, phase demodulation to the feedback signal of voltage controlled oscillator 5, defeated Go out trim voltage into loop filter 4；Trim voltage output after loop filter 4 suppresses noise and phase demodulation leakage is extremely pressed In controlled oscillator 5, the capacitance of the negative bias adjustment varactor group exported with low noise digital regulation resistance 8, change voltage-controlled The output local frequency of oscillator 5；Its local oscillation signal exported exports to phase discriminator 3 as feedback signal input all the way, forms Phase-locked loop, export all the way into buffer amplifier 6, as RF local oscillator signal.

While there has been shown and described that embodiment of the present utility model, for the ordinary skill in the art, It is appreciated that these embodiments can be carried out with a variety of changes in the case where not departing from principle of the present utility model and spirit, repaiied Change, replace and modification, the scope of the utility model are defined by the appended claims and the equivalents thereof.

Claims (3)

1. one kind is based on ultrashort high speed width covering frequence synthesizer, including Direct Digital Frequency Synthesizers (1), its feature exist In：The output end of the Direct Digital Frequency Synthesizers (1) is electrically connected with the input of bandpass filter (2), the band logical filter The output end of ripple device (2) is electrically connected with the input of phase discriminator (3), and the output end of the phase discriminator (3) is electrically connected with loop filter The input of ripple device (4), the output end of the loop filter (4) are electrically connected with the input of voltage controlled oscillator (5), the pressure The input of buffer amplifier (6) and phase discriminator (3), the VCO is electrically connected in the output end of controlled oscillator (5) The input of device (5) is electrically connected with the output end of low noise amplifier (7), and the input of the low noise amplifier (7) is electrically connected with low noise The output end of digital regulation resistance (8), the two-way electric connection field programmable gate array (9) of low noise digital regulation resistance (8), institute Field programmable gate array (9) two-way electric connection phase discriminator (3) and Direct Digital Frequency Synthesizers (1) respectively are stated, it is described existing The input of field programmable gate array (9) is electrically connected with the output end of temperature compensating crystal oscillator and Clock Managing Unit (10), the temperature compensation The output end of crystal oscillator and Clock Managing Unit (10) is electrically connected with the input of Direct Digital Frequency Synthesizers (1).

2. one kind according to claim 1 is based on ultrashort high speed width covering frequence synthesizer, it is characterised in that：It is described Temperature compensating crystal oscillator and Clock Managing Unit (10) include VCXO units and S3C6410 chips.

3. one kind according to claim 1 is based on ultrashort high speed width covering frequence synthesizer, it is characterised in that：It is described Phase discriminator (3) includes ADF4002 chips, LE, DATA, CLK, CE and REFIN pin difference series resistor of the ADF4002 chips R361, R345, R346, R317 and electric capacity C393, the electric capacity C393 other end series resistor R344, the ADF4002 cores AGND, DGND and CPGND pin of piece are grounded, RFINA, RFINB, RSET and MUXOUT pin difference of the ADF4002 chips Serial capacitance C381, electric capacity C382, resistance C363 and resistance C366, the other end of the electric capacity C382 and resistance R363 connect Ground, the VP pin of the ADF4002 chips are simultaneously connected to electric capacity C377, C379 and inductance L319, and the electric capacity C377's and C379 is another One end is grounded, and the other end of the inductance L319 is serially connected with+5VA chip input powers, the DVDD pin of the ADF4002 chips And be connected to the AVDD pin of ADF4002 chips, electric capacity C365, C348, C394, C372 and inductance L315, the electric capacity C365, C348, C394 and C372 other end are grounded, and the other end of the inductance L315 is serially connected with+3V3R chip input powers.