CN206685377U - A kind of dual chip high density frameworks of DFN2020 6 - Google Patents
A kind of dual chip high density frameworks of DFN2020 6 Download PDFInfo
- Publication number
- CN206685377U CN206685377U CN201720510272.5U CN201720510272U CN206685377U CN 206685377 U CN206685377 U CN 206685377U CN 201720510272 U CN201720510272 U CN 201720510272U CN 206685377 U CN206685377 U CN 206685377U
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- chip
- installation portion
- dfn2020
- pin
- framework
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- 230000009977 dual effect Effects 0.000 title claims abstract description 18
- 238000009434 installation Methods 0.000 claims abstract description 85
- 241000276425 Xiphophorus maculatus Species 0.000 claims abstract description 4
- 238000005520 cutting process Methods 0.000 claims description 41
- 238000005260 corrosion Methods 0.000 claims description 23
- 230000007797 corrosion Effects 0.000 claims description 23
- 210000003205 muscle Anatomy 0.000 claims description 16
- 238000000926 separation method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 239000011159 matrix material Substances 0.000 abstract description 6
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 235000020004 porter Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
It the utility model is related to technical field of manufacturing semiconductors, more particularly to a kind of dual chip high density frameworks of DFN2020 6, rectangular frame including platy structure, multiple chip installation portions being adapted with the encapsulating structures of DFN2020 6 are set on framework, 2 chip placing areas are provided with each chip installation portion, the chip installation portion is rectangle, and each chip installation portion is provided with 6 pin grooves, 3 pin grooves are one group and are symmetrically arranged in the both sides in chip placing area, and extend to chip installation portion edge；The lead-foot-line in one of chip placing area is welded in the pin groove of the same side, and the lead-foot-line in another chip placing area is all welded in the pin groove of opposite side.The chip installation portion pin arrangement of the framework is reasonable, noiseless, without the multi-direction arrangement pin around chip installation portion, reduces the distance between adjacent chips installation portion, reaches and improves the utilization rate of framework matrix material, reduces production cost.
Description
Technical field
A kind of semiconductor fabrication is the utility model is related to, particularly a kind of DFN2020-6 dual chips high density framework.
Background technology
Semiconductor refers to material of the electric conductivity between conductor and insulator under normal temperature, its radio, television set with
And had a wide range of applications on thermometric, if diode is exactly the device using semiconductor fabrication.No matter sent out from science and technology or economy
From the perspective of exhibition, the importance of semiconductor is all very huge.
In the manufacturing process of semiconductor, typically semiconductor is integrated on lead frame, allows lead frame as collection
Into the chip carrier of circuit, electric loop is formed, serves the function served as bridge connected with outer lead.Chip package form is：
DFN2020-6 twin-cores（DFN is the chip packaging unit model of miniature electric component, and 2020 represent one single chip installation portion
Size is long 2.0mm, wide 2.0mm square structure, and 6 indicate 6 pins, and twin-core represents can in one single chip installation portion
2 chips are installed）.
Because the pin number of such chip installation portion is more, multiple directions pin need to be arranged around chip installation portion
Groove so that the increase of the distance between chip and chip, reduce utilization rate, the increase production cost of framework matrix material.
Utility model content
Goal of the invention of the present utility model is：It is multi-party around it because needing for the chip installation portion with more pins
Position arrangement pin groove, the problem of arrangement distance between chip and chip increases, stock utilization is low, production cost is high is caused,
A kind of DFN2020-6 dual chips high density framework is provided, the chip installation portion pin arrangement of the framework is reasonable, noiseless, without
The multi-direction arrangement pin around chip installation portion, reduce the distance between adjacent chips installation portion, reach and improve framework matrix
The utilization rate of material, reduce production cost.
To achieve these goals, the technical solution adopted in the utility model is：
A kind of DFN2020-6 dual chips high density framework, include the rectangular frame of platy structure, set on framework it is multiple with
The adaptable chip installation portion of DFN2020-6 encapsulating structures, is provided with 2 chip placing areas, institute on each chip installation portion
It is rectangle to state chip installation portion, and each chip installation portion is provided with 6 pin grooves, and 3 pin grooves are one group and are symmetrically arranged in chip
The both sides of settlement, and extend to chip installation portion edge；The lead-foot-line in one of chip placing area is welded in the same side
In pin groove, the lead-foot-line in another chip placing area is all welded in the pin groove of opposite side.
2 chip placing areas are set in each chip installation portion of the framework, by the way that pin groove is arranged in into chip installation portion
Symmetrical both sides, and the pin in one of chip placing area is all welded in the pin groove of side, another chip peace
Put in the pin welding and opposite side pin groove in area, pin arrangement is reasonable, noiseless, without multi-direction around chip installation portion
Pin is arranged, reduces the distance between adjacent chips installation portion, reaches the utilization rate for improving framework matrix material, reduction is produced into
This.
As preferred scheme of the present utility model, all chip installation portions are arranged in the same direction so that adjacent chip
The pin groove at installation portion edge is corresponding, and the pin groove for making to be in contact on two chip installation portions connects.The pin groove of connection makes
Cutting Road between adjacent chips installation portion is thinning, is easy to cutting operation, reduces blade and framework gold when product is cut after encapsulating
The contact area of category, reduce the caloric value of framework when cutting, ensure the q＆r energy of product.
As preferred scheme of the present utility model, the pin bottom land of connection is half corrosion region, and half corrosion region is ellipse,
The corrosion region of ellipse half is symmetrical arranged centered on the Cutting Road of adjacent two chips installation portion.Adjacent chips installation portion is connected
Half corrosion region afterwards further reduces Cutting Road thickness, is set to ellipsoidal structure, i.e., half corrosion region in pin groove is circular arc
Shape structure, reduce influence of half corrosion region to pin slot structure as far as possible, not influence the bulk strength of chip installation portion.
As preferred scheme of the present utility model, each chip placing area in the chip installation portion include source electrode and
Grid, 3 lead-foot-lines are drawn and are welded in same pin groove from source electrode, and the grid is drawn 1 lead-foot-line and is welded in separately
In the pin groove of one homonymy.The lead point slot welding in each chip placing area is connect, does not influence nothing between polarity distribution and lead
Interference；In addition, pin groove surrounding is the connected structure of all-metal thickness, beneficial to frame strength is improved, make bonding wire more stable.
As preferred scheme of the present utility model, all chip installation portions while with framework while be arranged in parallel, in core
Vertical Cutting Road and transverse cuts road are respectively equipped between piece installation portion, all pin grooves extend to transverse cuts road, vertical
Hollow slots are interval with Cutting Road.The length direction arrangement of the hollow slots vertically Cutting Road, is easy to follow-up cutting separation
Operation, reduce blade heating, effectively reduce cutting layering.
As preferred scheme of the present utility model, the transverse cuts road connects muscle provided with transverse cuts road, for by phase
Adjacent pin groove connection.Adjacent pin groove is connected using even muscle, increases pin groove and whole frame strength, increase structure is steady
It is qualitative.
As preferred scheme of the present utility model, it is half corrosion knot that the vertical Cutting Road and transverse cuts road, which connect muscle,
Structure.Vertical Cutting Road and transverse cuts road connect muscle and are set as half corrosion structure, i.e., Cutting Road is connected to the thickness skiving of muscle, further subtracted
Small cutting difficulty.
As preferred scheme of the present utility model, the framework is provided with unit separation trough, and the unit separation trough is set
Portion in the frame, framework is divided into 2 chip mount units.Framework is increased operation rate in itself, reduces cost, will be traditional
More than 4 chip mount units of every framework are optimized for the design of 2 every, can have more on identical area on every framework
More chip mount units, improve stock utilization, reduce the cost of framework.
As preferred scheme of the present utility model, the lengths of frame is 250 ± 0.1mm, and width is 70 ± 0.05mm,
27 rows, 52 row chip installation portions are arranged with each chip mount unit.Framework has 2 chip mount units, each chip
Installation unit sets 27 rows, 58 row chip installation portions, i.e., 2808 chip installation portions is arranged on whole framework, than existing framework
Utilization rate is higher.
In summary, by adopting the above-described technical solution, the beneficial effects of the utility model are：
1st, the chip installation portion pin arrangement of the framework is reasonable, noiseless, without the multi-direction cloth around chip installation portion
Pin is put, reduces the distance between adjacent chips installation portion, reaches the utilization rate for improving framework matrix material, reduction is produced into
This；
2nd, the pin groove of connection makes the Cutting Road between adjacent chips installation portion thinning, is easy to cutting operation, and will connection
Pin bottom land be half corrosion region, further reduce Cutting Road thickness, reduce blade and frame metal when product after encapsulation is cut
Contact area, the caloric value of framework when reducing cutting, ensure the q＆r energy of product；
3rd, hollow slots are interval with vertical Cutting Road, are easy to subsequently cut lock out operation, reduce blade heating, effectively
Reduce cutting layering；Adjacent pin groove is connected using even muscle, increases pin groove and whole frame strength, increases Stability Analysis of Structures
Property；And vertical Cutting Road and transverse cuts road are connected into muscle and are set as half corrosion structure, i.e., Cutting Road is connected to the thickness skiving of muscle, enters one
Step reduces cutting difficulty；
4th, framework has 2 chip mount units, and each chip mount unit sets 27 rows, 58 row chip installation portions, that is, existed
2808 chip installation portions are arranged on whole framework, it is higher than existing framework utilization rate.
Brief description of the drawings
Fig. 1 is the structural representation of the utility model DFN2020-6 dual chip high density frameworks.
Fig. 2 is distribution map of multiple chip installation portions on framework.
Fig. 3 is the structural representation of one single chip installation portion.
Fig. 4 is the lead layout drawing being arranged on chip on chip installation portion.
Marked in figure：1- frameworks, 101- chip mount units, 2- unit separation troughs, 3- chip installation portions, 301- pins
Groove, half corrosion region in 3011- grooves, 302- chip placings area, the vertical Cutting Roads of 4-, 401- hollow slots, 5- transverse cuts road connect muscle,
6- chips, 7- source leads, 8- gate leads.
Embodiment
Below in conjunction with the accompanying drawings, the utility model is described in detail.
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining this
Utility model, it is not used to limit the utility model.
Embodiment 1
As shown in Figures 1 to 4, the DFN2020-6 dual chip high density frameworks of the present embodiment, the rectangle of platy structure is included
Framework 1, multiple chip installation portions 3 being adapted with DFN2020-6 encapsulating structures are set on framework 1, in each chip installation portion 3
On be provided with 2 chip placing areas 302, the chip installation portion 3 is rectangle, and each chip installation portion 3 is provided with 6 pin grooves
301,3 pin grooves 301 are one group and are symmetrically arranged in the both sides in chip placing area 302, and extend to the edge of chip installation portion 3；
The lead-foot-line in one of chip placing area 302 is welded in the pin groove 301 of the same side, and another chip placing area 302 draws
Payment to a porter is all welded in the pin groove 301 of opposite side.
As shown in figure 3, Liang Ge chip placings area 302 is arranged at the middle part of chip installation portion 3, the pin groove 301 symmetrically divides
The both sides in chip placing area 302 are located at, as shown in FIG., do not set the both sides back gauge chip placing of pin groove on chip installation portion 3
The size in area 302 can reduce, and reach the purpose of more arrangement chip installation portions 3 on framework 1.
In the present embodiment, all chip installation portions 3 are arranged in the same direction so that the adjacent edge of chip installation portion 3
Pin groove 301 is corresponding, and the pin groove 301 for making to be in contact on two chip installation portions 3 connects.The pin groove of connection makes adjacent core
Cutting Road between piece installation portion is thinning, is easy to cutting operation, reduces connecing for blade and frame metal when product after encapsulation is cut
Contacting surface is accumulated, the caloric value of framework when reducing cutting, ensures the q＆r energy of product.
Further, the bottom of pin groove 301 of the present embodiment connection is half corrosion region 3011 in groove, half corrosion region in the groove
3011 is oval, and half corrosion region 3011 is symmetrical arranged centered on the Cutting Road of adjacent two chips installation portion 3 in the groove.By phase
Half corrosion region after adjacent chip installation portion connection further reduces Cutting Road thickness, is set to ellipsoidal structure, i.e., in pin groove
Half corrosion region be arc-shaped structure, reduce influence of half corrosion region to pin slot structure as far as possible, not influence chip installation portion
Bulk strength.
In the present embodiment, each chip placing area 302 in the chip installation portion 3 includes source electrode and grid, 3 roots
Pole pin 7 is drawn and is welded in same pin groove 301 from source electrode, and 1 gate lead 8 of the grid extraction is welded in another
In the pin groove 301 of individual homonymy.The lead point slot welding in each chip placing area is connect, does not influence nothing between polarity distribution and lead
Interference；In addition, pin groove surrounding is the connected structure of all-metal thickness, beneficial to frame strength is improved, make bonding wire more stable.
Further, all chip installation portions 3 while with framework 1 while be arranged in parallel, between chip installation portion 3
Vertical Cutting Road 4 and transverse cuts road are respectively equipped with, all pin grooves 301 extend to transverse cuts road, on vertical Cutting Road 4
It is interval with hollow slots 401.The hollow slots vertically Cutting Road length direction arrangement, be easy to subsequently cut lock out operation,
Reduce blade heating, effectively reduce cutting layering.
Further, the transverse cuts road connects muscle 5 provided with transverse cuts road, for by adjacent pin groove 301
Connection.Adjacent pin groove is connected using even muscle, increases pin groove and whole frame strength, increases structural stability.
In the present embodiment, it is half corrosion structure that the vertical Cutting Road 4 and transverse cuts road, which connect muscle 5,.Vertical Cutting Road
Connect muscle with transverse cuts road and be set as half corrosion structure, i.e., Cutting Road is connected to the thickness skiving of muscle, further reduce cutting difficulty.
In summary, 2 chip placing areas are set in each chip installation portion of the framework of the present embodiment, by by pin groove
The symmetrical both sides of chip installation portion are arranged in, and the pin in one of chip placing area is all welded in the pin groove of side
Interior, in the pin welding in another chip placing area and opposite side pin groove, pin arrangement is reasonable, noiseless, without in chip
Multi-direction arrangement pin around installation portion, reduce the distance between adjacent chips installation portion, reach and improve framework matrix material
Utilization rate, reduce production cost.
Embodiment 2
As shown in Figures 1 to 4, the DFN2020-6 dual chip high density frameworks according to embodiment 1, the present embodiment
Framework 1 is provided with unit separation trough 2, and the unit separation trough 2 is arranged on the middle part of framework 1, and framework 1 is divided into 2 chip peaces
Fill unit 101.Framework is increased operation rate in itself, reduces cost, and traditional more than 4 chip mount units of every framework is excellent
Turn to the design of 2 every, there can be more chip mount units on every framework on identical area, improve material use
Rate, the cost for reducing framework.
Further, the length of framework 1 is 250 ± 0.1mm, and width is 70 ± 0.05mm, is installed in each chip
27 rows, 52 row chip installation portions 3 are arranged with unit 101.Framework has 2 chip mount units, each chip mount unit
27 rows, 58 row chip installation portions are set, i.e., 2808 chip installation portions are arranged on whole framework, than existing framework utilization rate more
It is high.
Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model
All any modification, equivalent and improvement made within the spirit and principle of utility model etc., should be included in the utility model
Protection domain within.
Claims (9)
1. a kind of DFN2020-6 dual chips high density framework, include the rectangular frame of platy structure, it is characterised in that in framework
On set multiple chip installation portions being adapted with DFN2020-6 encapsulating structures, 2 chips are provided with each chip installation portion
Settlement, the chip installation portion are rectangle, and each chip installation portion is provided with 6 pin grooves, and 3 pin grooves are one group symmetrical
The both sides in chip placing area are arranged in, and extend to chip installation portion edge；The pin wire bonding in one of chip placing area
In in the pin groove of the same side, the lead-foot-line in another chip placing area is all welded in the pin groove of opposite side.
2. DFN2020-6 dual chips high density framework according to claim 1, it is characterised in that all chip installation portions
Arrange in the same direction so that the pin groove at adjacent chip installation portion edge is corresponding, makes to connect on two chip installation portions
Tactile pin groove connection.
3. DFN2020-6 dual chips high density framework according to claim 2, it is characterised in that the pin bottom land of connection
For half corrosion region, half corrosion region is ellipse, and the corrosion region of ellipse half is with the Cutting Road of adjacent two chips installation portion
The heart is symmetrical arranged.
4. DFN2020-6 dual chips high density framework according to claim 1, it is characterised in that the chip installation portion
Interior each chip placing area includes source electrode and grid, and 3 lead-foot-lines are drawn and are welded in same pin groove from source electrode,
The grid is drawn 1 lead-foot-line and is welded in the pin groove of another homonymy.
5. the DFN2020-6 dual chip high density frameworks according to one of claim 1-4, it is characterised in that pacify in chip
Vertical Cutting Road and transverse cuts road are respectively equipped between dress portion, all pin grooves extend to transverse cuts road, are vertically cutting
Hollow slots are interval with road.
6. DFN2020-6 dual chips high density framework according to claim 5, it is characterised in that the transverse cuts road
Connect muscle provided with transverse cuts road, for adjacent pin groove to be connected.
7. DFN2020-6 dual chips high density framework according to claim 5, it is characterised in that the vertical Cutting Road
It is half corrosion structure to connect muscle with transverse cuts road.
8. DFN2020-6 dual chips high density framework according to claim 1, it is characterised in that the framework is provided with
Unit separation trough, the unit separation trough are arranged on frame mid portion, and framework is divided into 2 chip mount units.
9. DFN2020-6 dual chips high density framework according to claim 8, it is characterised in that the lengths of frame is
250 ± 0.1mm, width are 70 ± 0.05mm, and 27 rows, 52 row chip installation portions are arranged with each chip mount unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720510272.5U CN206685377U (en) | 2017-05-10 | 2017-05-10 | A kind of dual chip high density frameworks of DFN2020 6 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720510272.5U CN206685377U (en) | 2017-05-10 | 2017-05-10 | A kind of dual chip high density frameworks of DFN2020 6 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206685377U true CN206685377U (en) | 2017-11-28 |
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ID=60405811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720510272.5U Expired - Fee Related CN206685377U (en) | 2017-05-10 | 2017-05-10 | A kind of dual chip high density frameworks of DFN2020 6 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206685377U (en) |
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2017
- 2017-05-10 CN CN201720510272.5U patent/CN206685377U/en not_active Expired - Fee Related
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171128 Termination date: 20180510 |
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| CF01 | Termination of patent right due to non-payment of annual fee |