CN206541157U - Multi-channel data acquisition processing system - Google Patents
Multi-channel data acquisition processing system Download PDFInfo
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- CN206541157U CN206541157U CN201720143964.0U CN201720143964U CN206541157U CN 206541157 U CN206541157 U CN 206541157U CN 201720143964 U CN201720143964 U CN 201720143964U CN 206541157 U CN206541157 U CN 206541157U
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Abstract
The utility model is related to a kind of multi-channel data acquisition processing system, it is based on zynq7000 frameworks, including programmable logic cells and processing unit, the programmable logic cells include the numerical value collection subelement for being used to connecting and gathering outside multiple channel signals, for the conversion process subelement for the numerical value that the numerical value is gathered to form needed for the numerical value of subelement output is converted to the processing unit, the processing unit includes the DDR internal memories subelement for caching the programmable logic cells output numerical value and the numerical value for being stored to DDR internal memories subelement carries out the Data Analysis Services subelement of analysis calculating.The collection of AD numerical value, data conversion are calculated and all handled by programmable logic cells by the utility model, and the load for alleviating processing unit improves the real-time and overall performance of whole equipment.
Description
Technical field
The utility model is related to a kind of multi-channel data acquisition processing system.
Background technology
, it is necessary to AD data of synchronous acquisition multichannel and to each port number during the vibration analysis of mechanical fault diagnosis
According to carrying out substantial amounts of data processing simultaneously, with obtain average required for vibration analysis, peak-to-peak value, virtual value, standard deviation and
The parameters such as kurtosis.
Conventional vibration analysis equipment, as shown in fig. 1, combination is realized using FPGA and ARM software-hardware synergism modes
Scheme, i.e., using the AD data transmission units in FPGA, gather the initial data of each passage AD outputs and by system bus
Be transferred to ARM, carry out the conversion of AD numerical value floating-point and the calculating of square value in ARM, the step for need by n times addition and N
The computing of secondary multiplication, recycles the two numerical value obtained by calculating, passes through virtual value processing unit, kurtosis computing unit, Feng Feng
It is worth computing unit etc., each computing unit is also required to the computing by many sub-additions and multiplication, realizes the subsequent parameter of each passage
The calculating of numerical value, because ARM system bus bandwidth is limited, data transfer to ARM can take the plenty of time, FPGA and ARM's
Data transmission period becomes main bottleneck；Again because ARM is sequential organization, this may result in data processing calculate it is time-consuming compared with
It is long.On the other hand, because FPGA is pure hardware configuration, turned turtle when changing sample frequency or sampling period,
Mean that the problem of facing flexibility.Therefore, prior art is unfavorable for the lifting of the real-time and performance of vibration analysis, and
And substantial amounts of data processing algorithm can make ARM overloads so that requirement of the whole system to ARM performances is higher.
Especially when some high-end equipment intermediary base bearings break down, equipment and personal security can be had a strong impact on, because
This, it would be highly desirable to a kind of reliable, real-time health management device of development, can much occur in advance in failure by vibration analysis
Time point just alarms, it is to avoid the generation of significant trouble accident.The equipment not only needs to carry out the same of high speed to the data of multichannel
Step collection, and the data of the multichannel collected need progress Treatment Analysis simultaneously, using existing vibration analysis equipment, enter
Row so substantial amounts of Data Analysis Services, had both been unfavorable for the real-time and continuity of vibration analysis, and had also been unfavorable for systematic function
Lifting, so as to directly affect the real-time of fault alarm, continuity.
Utility model content
The utility model purpose is that there is provided a kind of easy, efficient multi-channel data acquisition in order to overcome disadvantages mentioned above
Processing system.
The technical scheme in the invention for solving the technical problem is：A kind of multi-channel data acquisition processing system
System, it is based on ZYNQ frameworks, including programmable logic cells and processing unit,
The programmable logic cells include be used for connect and gather outside multiple channel signals numerical value collection subelement,
Conversion process for the numerical value to be gathered to form numerical value needed for the numerical value of subelement output is converted to the processing unit
Unit, the output end of the numerical value collection subelement is connected with the conversion process subelement,
The processing unit includes the DDR internal memories subelement and use for being used to cache the programmable logic cells output numerical value
The Data Analysis Services subelement of analysis calculating, the DDR internal memories subelement are carried out in the numerical value stored to DDR internal memories subelement
Output end be connected with the Data Analysis Services subelement.
The conversion process subelement may include to carry out floating-point turn for the numerical value to be gathered to the numerical value of subelement output
The floating-point conversion subunit changed and the numerical value for the floating-point conversion subunit to be exported carry out the square value of square value calculating
Computation subunit；Corresponding, the DDR internal memories subelement includes being used to cache the floating of the floating-point conversion subunit output numerical value
Point value caches subelement and caches subelement for the square value for caching the square value computation subunit output numerical value.
One control end of the Data Analysis Services subelement can connect the numerical value collection subelement, and control described
Numerical value gathers the sample frequency of subelement.
The utility model utilizes ZYNQ hardware structure, and the collection of AD numerical value, data conversion are calculated and all pass through ZYNQ's
Programmable logic cells processing, the programmable logic cells PL is the work(that processing unit PS has shared significant portion data processing
Can, the load for alleviating processing unit PS of high degree, it is parallel organization to be additionally, since programmable logic cells, also significantly
Algorithm process speed is improved, so processing procedure is very efficient, it is only necessary to several clock cycle, at the same time, this practicality is new
Type gathers subelement by the processing unit PS logarithm values and is controlled, and can change six passage AD according to system actual conditions
The sample frequency of output channel, substantially increases the flexibility of system, therefore effectively raises the real-time of whole equipment, spirit
Activity and overall performance.
Brief description of the drawings
Fig. 1 is the workflow diagram of existing vibration analysis equipment；
Fig. 2 is theory diagram of the present utility model；
Fig. 3 is workflow of the present utility model.
Embodiment
As shown in Figure 2, it is a kind of preferred embodiment of the present utility model, the hardware of the ZYNQ based on Xilinx companies
Framework, including programmable logic cells PL and the processing unit PS two parts for being integrated with ARM Cortex-A9 double-cores：
The programmable logic cells include numerical value collection subelement, conversion process subelement, wherein, the numerical value collection
Subelement is used for the AD output signals for connecting and gathering outside 6 passages (i.e. AD (channel 0)~AD (channel 5)),
In actual applications, the acquisition channel of multiple connection sensors can be expanded to, the conversion process subelement turns including floating-point
Change subelement and square value computation subunit；The floating-point conversion subunit is used for the number that the numerical value is gathered to subelement output
According to floating-point conversion is carried out, real magnitude of voltage is obtained, the square value computation subunit is used to export floating-point conversion subunit
Real voltage value carry out square value calculating, the signal of the floating-point conversion subunit and square value computation subunit output is supplied
Further calculating is handled the processing unit, and is transferred to the processing unit through two AXI high speed bus interfaces HP0, HP2.
The processing unit includes DDR internal memories subelement and Data Analysis Services subelement, corresponding, the DDR internal memories
The floating-point values that subelement includes being used to cache the floating-point conversion subunit output numerical value cache subelement and for caching
The square value caching subelement of square value computation subunit output numerical value is stated, the Data Analysis Services subelement is used for DDR
The floating data and square Value Data of internal memory subelement storage carry out analysis calculating.One of the Data Analysis Services subelement
Control end connects the numerical value by a feedback channel and gathers subelement, and is led to according to the control of system actual conditions and change six
The sample frequency of road AD output signals, substantially increases the flexibility of system.
With reference to accompanying drawing 3, it can be seen from said structure, adopting for AD numerical value is realized in ZYNQ programmable logic cells PL
The calculating process of collection, floating-point conversion and its square value, then the DDR internal memories are uploaded directly into by its internal high-speed bus
In subelement, the Data Analysis Services subelement reading numerical values and the further fortune of continuation from the DDR internal memories subelement
Calculate processing procedure.Due to average, peak-to-peak value, virtual value, standard deviation and other fortune in kurtosis and later stage during vibration analysis
Calculate and be required for the AD numerical value after conversion, and virtual value, standard deviation and kurtosis are required for the quadratic term of AD numerical value after conversion.When
When frequency acquisition is very high, the collection of AD numerical value, floating-point conversion and its square value are calculated to the FPGA all by ZYNQ
Unit PL processing, the programmable unit PL is the function that processing unit PS has shared significant portion data processing, high degree
The load for alleviating processing unit PS, it is parallel organization to be additionally, since programmable logic cells, is also substantially increased at algorithm
Speed is managed, so processing procedure is very efficient, it is only necessary to several clock cycle, therefore the real-time of whole equipment is effectively raised
Property and overall performance.
Simultaneously, newest AXI is used between the programmable unit (PL) and processing unit (PS) of the ZYNQ platforms
HP buses, 4 passage total bandwidths reduce the time of data transfer to greatest extent up to 9600MBps.The processing of ZYNQ platforms
Unit (PS) partly be ARMv7 frameworks Cortex-A9 double-cores, ARMv7 frameworks provide NEON engines, to later stage algorithm realize and
Optimization speed-raising also provides favourable guarantee.And data acquisition is controlled using processing unit (PS) very flexible.When changing
Variable sampling frequency, sampling duration, data processing etc. are all very simple.Contrasted by actual operation, in the case of 200Kbps sample rates
Kurtosis arithmetic speed lifts at least 2 times than traditional approach.
On the other hand, by the way that the calculating process of virtual value and standard deviation is split, it has been found that two parameters
Calculating process has used the square value one of AD numerical value, and the floating-point conversion of AD data is then realized in FPGA PL
And its calculating process of square value, due to FPGA PL be parallel organization, and raw value with its square value respectively by interior
Portion high-speed bus HP0, HP2 are uploaded in the DDR internal memories subelement, and the processing unit PS is while raw value is read
Square value can just be read out, i.e. the calculating of square value is transmitted and is not take up the operation time of the processing unit PS, therefore
This scheme is not only that the processing unit PS has shared the function that floating-point conversion and square value are calculated, and is also the processing unit PS
The operation time of 2N sub-additions and 3N multiplication altogether is saved, arithmetic speed improves at least twice, substantially reduced effectively
The calculating of value and kurtosis takes, and effectively improves the real-time performance of whole system.
Multi-channel data acquisition processing system provided by the utility model is described in detail above, herein should
Principle of the present utility model and embodiment are set forth with specific case, the explanation of above example is only intended to side
Assistant solves method of the present utility model and its core concept；It is new according to this practicality simultaneously for those of ordinary skill in the art
The thought of type, be will change in specific embodiments and applications, in summary, and this specification content should not be managed
Solve as to limitation of the present utility model.
Claims (3)
1. a kind of multi-channel data acquisition processing system, it is characterised in that：It is based on ZYNQ frameworks, including programmable logic cells
And processing unit,
The numerical value that the programmable logic cells include being used to connecting and gathering outside multiple channel signals gathers subelement, is used for
Conversion process of the numerical value of form needed for the numerical value that the numerical value is gathered into subelement output is converted to the processing unit is single
Member,
The processing unit include be used for cache the programmable logic cells output numerical value DDR internal memories subelement and for pair
The numerical value of DDR internal memories subelement storage carries out the Data Analysis Services subelement of analysis calculating.
2. multi-channel data acquisition processing system according to claim 1, it is characterised in that：The conversion process subelement
Including carrying out the floating-point conversion subunit of floating-point conversion and for by institute for the numerical value to be gathered to the numerical value of subelement output
The numerical value for stating the output of floating-point conversion subunit carries out the square value computation subunit of square value calculating；It is corresponding, the DDR internal memories
The floating-point values that subelement includes being used to cache the floating-point conversion subunit output numerical value cache subelement and for caching
State the square value caching subelement of square value computation subunit output numerical value.
3. multi-channel data acquisition processing system according to claim 1 or 2, it is characterised in that：At the data analysis
A control end for managing subelement connects the numerical value collection subelement, and controls the sampling frequency of the numerical value collection subelement
Rate.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147219A (en) * | 2019-05-09 | 2019-08-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of hardware-accelerated method |
| CN110579642A (en) * | 2019-09-20 | 2019-12-17 | 哈尔滨工业大学 | Zynq-based airborne alternating current multi-path parallel acquisition and processing system |
| CN117833935A (en) * | 2024-03-05 | 2024-04-05 | 成都航天通信设备有限责任公司 | Signal frequency conversion processing system and method based on FPGA |
-
2017
- 2017-02-17 CN CN201720143964.0U patent/CN206541157U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147219A (en) * | 2019-05-09 | 2019-08-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of hardware-accelerated method |
| CN110147219B (en) * | 2019-05-09 | 2023-04-07 | 中国航空工业集团公司西安航空计算技术研究所 | Hardware acceleration method |
| CN110579642A (en) * | 2019-09-20 | 2019-12-17 | 哈尔滨工业大学 | Zynq-based airborne alternating current multi-path parallel acquisition and processing system |
| CN117833935A (en) * | 2024-03-05 | 2024-04-05 | 成都航天通信设备有限责任公司 | Signal frequency conversion processing system and method based on FPGA |
| CN117833935B (en) * | 2024-03-05 | 2024-05-07 | 成都航天通信设备有限责任公司 | Signal frequency conversion processing method based on FPGA |
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