CN117833935B - Signal frequency conversion processing method based on FPGA - Google Patents
Signal frequency conversion processing method based on FPGA Download PDFInfo
- Publication number
- CN117833935B CN117833935B CN202410246619.4A CN202410246619A CN117833935B CN 117833935 B CN117833935 B CN 117833935B CN 202410246619 A CN202410246619 A CN 202410246619A CN 117833935 B CN117833935 B CN 117833935B
- Authority
- CN
- China
- Prior art keywords
- signal
- frequency
- fpga
- conversion processing
- generating module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 29
- 238000003672 processing method Methods 0.000 title claims abstract description 7
- 230000008859 change Effects 0.000 claims abstract description 23
- 230000004048 modification Effects 0.000 claims abstract description 12
- 238000012986 modification Methods 0.000 claims abstract description 12
- 101000915470 Homo sapiens Zinc finger MYND domain-containing protein 11 Proteins 0.000 claims abstract description 9
- 102100028551 Zinc finger MYND domain-containing protein 11 Human genes 0.000 claims abstract description 9
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 3
- 238000012545 processing Methods 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 16
- 238000004891 communication Methods 0.000 claims description 11
- 238000011161 development Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 230000003993 interaction Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
Abstract
The invention relates to the technical field of signal frequency conversion, and discloses a signal frequency conversion processing method based on an FPGA, which comprises the following steps: s1, PS receives a frequency change instruction of a frequency mixing signal generating module, PS calculates a register value of the frequency mixing signal generating module according to the frequency change, sets an update mark, and stores the update mark and the register value into BRAM1; s2, PL sets interval first set interval time, takes out the value from the corresponding BRAM1, if the update mark is 1, inputs the register value to the frequency mixing signal generating module through SPI time sequence program; s3, configuring a mixing signal generation module, feeding back a configuration locking mark to PL, and storing a locking mark value into BRAM2; s4, taking the PL locking mark value out of the BRAM2 at the second set interval time of the PS interval, and judging whether the frequency modification is successful or not. The invention solves the problems of poor adaptability, low efficiency, poor robustness and the like in the prior art.
Description
Technical Field
The invention relates to the technical field of signal frequency conversion, in particular to a signal frequency conversion processing method based on an FPGA.
Background
With the rapid development of electronics and mobile interconnect industries in recent years, wireless communications are also continually updating standards and protocols to meet new demands. The flexible requirement of the variable communication system can be met through the reconstruction of the wireless communication software.
The traditional wireless communication system adopts an FPGA+ARM or DSP+ARM scheme, and the system not only has high cost, but also has large system volume. Therefore, xilinx pushes out a ZYNQ series expansion platform, and the FPGA and the multi-core processor are fused, so that the Xilinx is widely applied to wireless software communication. However, in the development and application, most developers still only transplant the original FPGA code or ARM code on the ZYNQ platform, but do not decompose and reconstruct the code function according to the dominant features of the ZYNQ, and cannot effectively exert the advantages thereof.
The prior art has the problems of poor adaptability, low efficiency, poor robustness and the like.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a signal frequency conversion processing method based on an FPGA, which solves the problems of poor adaptability, low efficiency, poor robustness and the like in the prior art.
The invention solves the problems by adopting the following technical scheme:
The signal frequency conversion processing system based on the FPGA comprises a signal control module and a signal processing module which are in communication connection, wherein the signal processing module comprises a mixed signal generating module, and the signal control module is used for sending clock signals and control signals to the mixed signal generating module.
As a preferable technical scheme, the signal control module comprises a ZYNQ-7000 chip, and the ZYNQ-7000 chip comprises PS and PL.
As a preferred solution, PS and PL work separately.
As a preferred solution, PS, PL interwork over AXI bus.
As a preferred solution, PS application C programming language and environment are developed.
As a preferred technical scheme, the PL is developed by applying FPGA development language and environment.
As a preferred embodiment, the mixing signal generating module is an ADF4350 chip.
A signal frequency conversion processing method based on FPGA adopts the signal frequency conversion processing system based on FPGA to carry out signal frequency conversion processing.
As a preferred technical scheme, the method comprises the following steps:
S1, PS receives a frequency change instruction of a frequency mixing signal generating module, PS calculates a register value of the frequency mixing signal generating module according to the frequency change, sets an update mark, and stores the update mark and the register value into BRAM1;
S2, PL sets interval first set interval time, takes out the value from the corresponding BRAM1, if the update mark is 1, inputs the register value to the frequency mixing signal generating module through SPI time sequence program;
S3, configuring a mixing signal generation module, feeding back a configuration locking mark to PL, and storing a locking mark value into BRAM2;
S4, taking the PL locking mark value out of the BRAM2 at a second set interval time of the PS interval, and judging whether the frequency modification is successful or not; if yes, the frequency change configuration is successful; if not, returning to the step S1.
As a preferable technical scheme, the first set interval time is [10ms,30ms ], and the second set interval time is [70ms,90ms ].
Compared with the prior art, the invention has the following beneficial effects:
(1) The architecture of the invention conforms to the wireless communication processing trend, selects ZYNQ-7000 chips, can better exert the wireless communication frequency conversion processing advantages of software, can complete the new communication protocol change only by modifying the software, and has lower cost and stronger adaptability;
(2) According to the invention, for the generation of frequency signals needing mixing, according to the control characteristic of an ADF4350 chip, the PS and PL characteristics of a ZYNQ-7000 platform are fully exerted, the frequency change calculation of the frequency signals and the processing of 6 register change values are written in the PS part of the ZYNQ-7000 by using c codes, and the frequency change calculation and the processing can be modified and debugged at any time, so that the timeliness is high; the SPI control time sequence implementation process is written in the FPGA language in the PL part of ZYNQ-7000, and once the SPI control time sequence verification function is correct, modification is not needed, so that the characteristics of strong robustness of FPGA codes and accurate time sequence are exerted;
(3) The invention has a locking feedback reconfiguration mechanism for the processing flow of chip configuration, so that the architecture design rationality is stronger and the system applicability is stronger.
Drawings
FIG. 1 is a hardware architecture block diagram of a signal conversion processing system based on an FPGA according to the present invention;
FIG. 2 is a diagram illustrating a control signal code design;
FIG. 3 is a flow chart of ADF4350 software control process;
Fig. 4 is a signal conversion processing diagram.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but embodiments of the present invention are not limited thereto.
Example 1
As shown in FIGS. 1-4, the FPGA of the invention adopts a ZYNQ-7000 chip of the Xilinx series, which is a fully programmable capability platform of an embedded ARM hard core processor, comprises a processor system (Processing System, PS) and programmable logic devices (Programmable Logic, PL), and has the capability of programming processor software and FPGA hardware.
PS and PL may operate alone or may operate in conjunction with each other via AXI bus interactions. The PS part is developed by applying the software programming languages and environments such as C and the like, and has high efficiency and instantaneity of function modification. The PL part applies FPGA development language and environment to develop, and the robustness of the function and the accuracy of the time sequence are ensured.
For the processing of wireless signals, frequency conversion is a common way of modulating the signal output to the frequency signal required by the demand. The original signal and the frequency signal are mixed to reach the frequency conversion signal with the frequency conversion requirement.
The invention selects ADF4350 chip, which generates mixing frequency signal for changing original signal. ADF4350 has an integrated Voltage Controlled Oscillator (VCO) with a fundamental output frequency in the range 2200 MHz to 4400 MHz. When used in conjunction with an outer loop filter and an outer reference frequency, a fractional-N or integer-N phase-locked loop (PLL) frequency synthesizer may be implemented, and furthermore, with a 1/2/4/8/16 divide circuit, a user may generate RF output frequencies as low as 137.5 MHz.
ADF4350 is controlled by inputting corresponding values to six control registers via the SPI interface. The clock signal outputs a corresponding frequency signal according to the control register value. The invention is shown in fig. 2 for a control signal code design structure. In practical applications, the frequency signal output by ADF4350 needs to be changed frequently, and 6 corresponding register values also change. While the control timing of inputting the new register value to the ADF4350 through the SPI is unchanged.
It should be noted that, regarding "input of corresponding values to six control registers through SPI interface": the control of the chip ADF4350 is that the chip ADF4350 has 6 registers for control, and control data is externally input to the 6 registers through the SPI interface line.
Thus, exploiting the ZYNQ-7000 platform's superiority places both processes in PS and PL parts designed in ZYNQ-7000, respectively.
The frequency change calculation of the frequency signal and the processing of 6 register change values are written by a c code in the PS part of ZYNQ-7000, the modification and debugging can be carried out at any time, the timeliness is high, if the code is arranged in the PL part, the code is recombined every time the numerical value is changed, the large engineering is integrated, and the large engineering needs to use a plurality of hours, so the applicability is poor.
The SPI control time sequence implementation process is written in the FPGA language in the PL part of ZYNQ-7000, and once the SPI control time sequence verification function is correct, modification is not needed, and the characteristics of strong robustness of FPGA codes and accurate time sequence are exerted.
BRAM is designed for interaction of PS and PL data interaction parts.
The processing flow comprises the following steps:
1. And when receiving an output frequency modification instruction of the ADF4350 to be modified, writing corresponding relation codes of frequency change and register value change by the PS to obtain 6 groups of register values, setting an update flag variable A1 to be 1, and setting 0 if no frequency change A1 exists. Storing the changed 6 groups of register values and the updated variable A1 into a space selected by BRAM 1; wherein BRAM1 refers to a memory on PL for data interaction with PS.
2. The PL code is set to read the A1 value from the corresponding storage space of the BRAM1 every 20ms, and if A1 is 0, no processing is performed; if A1 is 1,6 sets of register values will be read from BRAM1 and input to ADF4350 via the written SPI code.
3. After the ADF4350 chip is reconfigured, PL can read whether the ADF4350 configuration is successful or not and store the locking flag value in a BRAM2 selected space; wherein BRAM2 refers to a memory on PS for data interaction with PL.
4. The PS interval 80ms takes the PL lock flag value A2 from BRAM2 and determines whether the frequency modification was successful. If the success A2 is 1, the successful flow of the frequency change configuration is ended. If the failure is 0, the PS code returns to step1 again, and the process is repeated 3 times according to the starting flow.
Frequency conversion processing principle: the ADF4350 is successfully configured to obtain the frequency signal required for frequency conversion. The original signal and the frequency signal are subjected to mixing processing to obtain a frequency conversion signal, and the frequency conversion processing is completed, as shown in fig. 4.
It should be noted that, the "mixing processing is performed on the original signal and the frequency signal to obtain the frequency-converted signal" belongs to the prior art, and may also be implemented in various manners (for example, mixing is implemented by a mixer, the two signals are multiplied, and then an unnecessary frequency signal is filtered by a filter to obtain the required frequency signal), so this part of the disclosure will not be described in detail.
The invention has the following technical effects:
(1) The architecture of the invention conforms to the wireless communication processing trend, selects ZYNQ-7000 chips, can better exert the wireless communication frequency conversion processing advantages of software, can complete the new communication protocol change only by modifying the software, and has lower cost and stronger adaptability;
(2) According to the invention, the generation of frequency signals to be mixed is carried out, the PS and PL characteristics of the ZYNQ-7000 platform are fully exerted according to the control characteristic of the ADF4350 chip, the frequency change calculation and 6 register change value processing of the frequency signals are written by using a c code in the PS part of the ZYNQ-7000, the modification and debugging can be carried out at any time, the timeliness is high (if the code is arranged in the PL part, the code is recombined every time the numerical value change, and a few hours are needed for large engineering synthesis), and the applicability is poor); the SPI control time sequence implementation process is written in the FPGA language in the PL part of ZYNQ-7000, and once the SPI control time sequence verification function is correct, modification is not needed, so that the characteristics of strong robustness of FPGA codes and accurate time sequence are exerted;
(3) The invention has a locking feedback reconfiguration mechanism for the processing flow of chip configuration, so that the architecture design rationality is stronger and the system applicability is stronger.
As described above, the present invention can be preferably implemented.
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
The foregoing description of the preferred embodiment of the invention is not intended to limit the invention in any way, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the invention.
Claims (7)
1. The signal frequency conversion processing method based on the FPGA is characterized in that a signal frequency conversion processing system based on the FPGA is adopted for signal frequency conversion processing, the system comprises a signal control module and a signal processing module which are in communication connection with each other, the signal processing module comprises a mixed signal generating module, and the signal control module is used for sending clock signals and control signals to the mixed signal generating module;
The signal control module comprises a ZYNQ-7000 chip, and the ZYNQ-7000 chip comprises PS and PL;
the method comprises the following steps:
S1, PS receives a frequency change instruction of a frequency mixing signal generating module, PS calculates a register value of the frequency mixing signal generating module according to the frequency change, sets an update mark, and stores the update mark and the register value into BRAM1;
S2, PL sets interval first set interval time, takes out the value from the corresponding BRAM1, if the update mark is 1, inputs the register value to the frequency mixing signal generating module through SPI time sequence program;
S3, configuring a mixing signal generation module, feeding back a configuration locking mark to PL, and storing a locking mark value into BRAM2;
S4, taking the PL locking mark value out of the BRAM2 at a second set interval time of the PS interval, and judging whether the frequency modification is successful or not; if yes, the frequency change configuration is successful; if not, returning to the step S1.
2. The method for FPGA-based signal conversion processing according to claim 1, wherein PS and PL operate independently.
3. The method for signal conversion processing based on FPGA of claim 1, wherein PS and PL are interworked through AXI bus.
4. The method for signal conversion processing based on the FPGA according to claim 1, wherein the PS application C programming language and environment are developed.
5. The method for FPGA-based signal conversion processing according to claim 1, wherein PL is developed using FPGA development language and environment.
6. The method of claim 1, wherein the mixed signal generating module is an ADF4350 chip.
7. The method according to any one of claims 1 to 6, wherein the first set interval is [10ms,30ms ], and the second set interval is [70ms,90ms ].
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410246619.4A CN117833935B (en) | 2024-03-05 | 2024-03-05 | Signal frequency conversion processing method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410246619.4A CN117833935B (en) | 2024-03-05 | 2024-03-05 | Signal frequency conversion processing method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117833935A CN117833935A (en) | 2024-04-05 |
| CN117833935B true CN117833935B (en) | 2024-05-07 |
Family
ID=90523102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410246619.4A Active CN117833935B (en) | 2024-03-05 | 2024-03-05 | Signal frequency conversion processing method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117833935B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7178117B1 (en) * | 2004-04-08 | 2007-02-13 | Altera Corporation | Apparatus and method for RTL based full chip modeling of a programmable logic device |
| WO2017045338A1 (en) * | 2015-09-18 | 2017-03-23 | 东南大学 | Automatic frequency band calibration method for rapid lock of phase-locked loop system |
| CN206541157U (en) * | 2017-02-17 | 2017-10-03 | 北京天际翔达科技有限公司 | Multi-channel data acquisition processing system |
| CN208691237U (en) * | 2018-12-14 | 2019-04-02 | 成都定为电子技术有限公司 | A kind of broadband numerical model analysis radio-frequency module |
| CN112835829A (en) * | 2021-02-10 | 2021-05-25 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Method for multi-channel DMA transmission measurement and control signal |
| CN112888085A (en) * | 2021-01-13 | 2021-06-01 | 中科华军(北京)科技发展有限公司 | Broadband wireless ad hoc network radio station and broadband wireless ad hoc network system |
| CN113219434A (en) * | 2021-04-27 | 2021-08-06 | 南京理工大学 | Self-adaptive broadband digital zero-setting system and method based on Zynq chip |
| CN113922887A (en) * | 2021-10-22 | 2022-01-11 | 中国科学院西安光学精密机械研究所 | Carrier synchronization method and system for spatial coherent optical communication 2PSK modulation signal |
| CN113971022A (en) * | 2021-12-22 | 2022-01-25 | 成都航天通信设备有限责任公司 | Wireless signal processing method and system applying system on fully programmable chip |
| CN114755630A (en) * | 2022-03-23 | 2022-07-15 | 中山大学 | Frequency modulation continuous wave radar based on SOC |
| CN115632675A (en) * | 2022-12-06 | 2023-01-20 | 成都航天通信设备有限责任公司 | Multi-module wireless signal processing system and method based on FPGA |
| CN116576841A (en) * | 2023-05-19 | 2023-08-11 | 东南大学 | Hemispherical gyro full angle control system and method based on double-frequency carrier wave scheme |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10673469B2 (en) * | 2018-01-03 | 2020-06-02 | Morgan State University | Multi-band multi-mode software defined radio |
| US11610111B2 (en) * | 2018-10-03 | 2023-03-21 | Northeastern University | Real-time cognitive wireless networking through deep learning in transmission and reception communication paths |
| CN216313095U (en) * | 2021-12-29 | 2022-04-15 | 大连海事大学 | Digital-analog hybrid wireless transmission transceiver |
-
2024
- 2024-03-05 CN CN202410246619.4A patent/CN117833935B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7178117B1 (en) * | 2004-04-08 | 2007-02-13 | Altera Corporation | Apparatus and method for RTL based full chip modeling of a programmable logic device |
| WO2017045338A1 (en) * | 2015-09-18 | 2017-03-23 | 东南大学 | Automatic frequency band calibration method for rapid lock of phase-locked loop system |
| CN206541157U (en) * | 2017-02-17 | 2017-10-03 | 北京天际翔达科技有限公司 | Multi-channel data acquisition processing system |
| CN208691237U (en) * | 2018-12-14 | 2019-04-02 | 成都定为电子技术有限公司 | A kind of broadband numerical model analysis radio-frequency module |
| CN112888085A (en) * | 2021-01-13 | 2021-06-01 | 中科华军(北京)科技发展有限公司 | Broadband wireless ad hoc network radio station and broadband wireless ad hoc network system |
| CN112835829A (en) * | 2021-02-10 | 2021-05-25 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Method for multi-channel DMA transmission measurement and control signal |
| CN113219434A (en) * | 2021-04-27 | 2021-08-06 | 南京理工大学 | Self-adaptive broadband digital zero-setting system and method based on Zynq chip |
| CN113922887A (en) * | 2021-10-22 | 2022-01-11 | 中国科学院西安光学精密机械研究所 | Carrier synchronization method and system for spatial coherent optical communication 2PSK modulation signal |
| CN113971022A (en) * | 2021-12-22 | 2022-01-25 | 成都航天通信设备有限责任公司 | Wireless signal processing method and system applying system on fully programmable chip |
| CN114755630A (en) * | 2022-03-23 | 2022-07-15 | 中山大学 | Frequency modulation continuous wave radar based on SOC |
| CN115632675A (en) * | 2022-12-06 | 2023-01-20 | 成都航天通信设备有限责任公司 | Multi-module wireless signal processing system and method based on FPGA |
| CN116576841A (en) * | 2023-05-19 | 2023-08-11 | 东南大学 | Hemispherical gyro full angle control system and method based on double-frequency carrier wave scheme |
Non-Patent Citations (3)
| Title |
|---|
| Hardware Software Co-design of k-means Clustering Algorithm;Avadh Harkishanka等;《2023 9th International Conference on Signal Processing and Communication (ICSC)》;20240226;全文 * |
| 基于Zynq的TDLAS激光器温度控制系统研究;王彪等;《激光杂志》;20231108(第10期);全文 * |
| 基于Zynq的多通道振动信号采集系统设计;王旭东;《中国优秀硕士学位论文全文数据库》;20240215(第2期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117833935A (en) | 2024-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7929935B2 (en) | Wireless data communications using FIFO for synchronization memory | |
| EP1330828A2 (en) | Upscaled clock feeds memory to make parallel waves | |
| US6441667B1 (en) | Multiphase clock generator | |
| KR19990006743A (en) | Data processing device and mobile communication terminal device | |
| CN103023507A (en) | Method and device for generating sampling clock of digital to analog converter (DAC) | |
| CN117833935B (en) | Signal frequency conversion processing method based on FPGA | |
| CN106549667B (en) | Digital decimal frequency divider and its dividing method | |
| CN104049995A (en) | Method and device for configuring FPGA (field programmable gate array) in MCU (microprogrammed control unit) chip | |
| Arnesen et al. | Increasing design productivity through core reuse, meta-data encapsulation, and synthesis | |
| CN108459876B (en) | Method and apparatus for reduced area control register circuit | |
| US10826506B2 (en) | Modulus divider with deterministic phase alignment | |
| JPH04140812A (en) | Information processing system | |
| CN113325918A (en) | Clock management circuit, chip and electronic equipment | |
| CN111736655B (en) | Configuration method applied to clock chip | |
| CN112671403A (en) | Clock frequency division system, method and equipment | |
| AU749870B2 (en) | Plural synthesizer controlling system for personal handyphone system and plural synthesizer controlling method for the same | |
| CN112540642A (en) | Multi-clock domain processing method, device, equipment and medium | |
| JP2002135116A (en) | Pll circuit and frequency-dividing method | |
| US6798257B1 (en) | Method and apparatus for providing multiple clock signals on a chip using a second PLL library circuit connected to a buffered reference clock output of a first PLL library circuit | |
| CN117056268B (en) | SPI interface circuit and SPI communication method for measuring instrument | |
| Philips et al. | Silicon integration of digital user-end mobile communication systems | |
| Lee et al. | A Cell-Based Fractional-N Phase-Locked Loop Compiler | |
| CN112953520A (en) | Phase-locked loop all-digital frequency band switching technology based on successive approximation logic | |
| US20200382131A1 (en) | Waveform synthesizer using multiple digital-to-analog converters | |
| Liao | MIPS-based remote small-step frequency source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |