CN108173733B - FPGA-based miniaturized synchronous time service and data transmission device and application - Google Patents
FPGA-based miniaturized synchronous time service and data transmission device and application Download PDFInfo
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- CN108173733B CN108173733B CN201711458833.2A CN201711458833A CN108173733B CN 108173733 B CN108173733 B CN 108173733B CN 201711458833 A CN201711458833 A CN 201711458833A CN 108173733 B CN108173733 B CN 108173733B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
Abstract
The invention discloses a miniaturized synchronous time service and data transmission device based on FPGA, comprising: the serial deserializer is used for deserializing data on the data \ clock multiplexing bus to obtain a synchronous clock and transmission data and transmitting the synchronous clock and the transmission data to the FPGA; the FPGA is used for forwarding the received synchronous clock and the transmission data to a plurality of slave devices, controlling synchronous sampling of the plurality of devices and packaging the transmission data uploaded by the plurality of slave devices and then forwarding the transmission data to the serial deserializer; the synchronous time service interface is used for realizing the transmission of a synchronous clock between the FPGA and a plurality of slave devices; and the data transceiving interface is used for realizing the transmission of data transmission between the FPGA and the plurality of slave devices. The device reduces the size and complexity of the whole system engineering and improves the system performance under the condition of long-distance transmission.
Description
Technical Field
The invention relates to the field of FPGA technology and data synchronization and transmission technology, in particular to a miniaturized synchronous time service and data transmission device based on FPGA and application thereof.
Background
The collection, transmission and processing of field data have become indispensable links for industrial control, production and scientific research. The data acquisition system mainly completes the acquisition, A/D conversion and processing of data information, and then sends the data information to a computer for further processing and storage or feeds back the processing result to equipment for relevant control.
The data acquisition system is an important component of the Internet of things, can provide real-time data for management and control, and provides important basis for monitoring and performance analysis of equipment by operators. In order to shorten the system development period and avoid repeated design of the system, the design and research of the data acquisition system have important significance. At present, data needing to be collected mainly come from various sensors, the spatial distribution is wide, the data volume is large, the data cannot be obtained in a manual mode under special environments with high risk and high strength, and at the moment, various data of a working site need to be obtained through the sensors, and the collected data are transmitted and processed.
The current data acquisition system has the shortcomings of poor universality, high energy consumption, space waste, weak secondary development capacity and the like, and various interferences are diffused in a working site and an operating environment due to the complexity and the changeability of an engineering environment, so that the data acquisition is deviated, and the consequences of different degrees are caused. Therefore, in order to solve the above problems, the present invention provides a miniaturized synchronous time service and data transmission device, which has important engineering significance.
Disclosure of Invention
In order to reduce the size and complexity of the whole system engineering and improve the system performance under the condition of long-distance transmission, the invention provides a miniaturized synchronous time service and data transmission device based on an FPGA and application thereof.
In order to achieve the purpose, the invention provides the following technical scheme:
a miniaturized synchronous time service and data transmission device based on FPGA, the device includes:
the serial deserializer is used for deserializing data on the data \ clock multiplexing bus to obtain a synchronous clock and transmission data and transmitting the synchronous clock and the transmission data to the FPGA;
the FPGA is used for forwarding the received synchronous clock and the transmission data to a plurality of slave devices, controlling synchronous sampling of the plurality of devices and packaging the transmission data uploaded by the plurality of slave devices and then forwarding the transmission data to the serial deserializer;
the synchronous time service interface is used for realizing the transmission of a synchronous clock between the FPGA and a plurality of slave devices;
and the data transceiving interface is used for realizing the transmission of data transmission between the FPGA and the plurality of slave devices.
The device realizes the decomposition of synchronous clocks and transmission data in a clock/data multiplexing bus on the clock/data bus multiplexing technology, controls the synchronous sampling of a plurality of slave devices connected with the device by utilizing the obtained synchronous clocks, and improves the correctness of data sampling.
Wherein, the FPGA includes:
the clock generation module is used for sending the synchronous clock decoded by the serial deserializer to a slave device as a synchronous clock to complete data beat control of the slave device;
the slave device control module is used for finishing the control logic of the slave device and commanding the currently mounted slave device to upload data;
the forwarding memory controller is used for performing serial-parallel conversion on the data from the slave device and then caching the data, and forwarding the cached data under the scheduling of the forwarding module;
the forwarding module is used for forwarding data packets sent by other synchronous time service and data transmission devices; and meanwhile, the forwarding memory controller is scheduled, the data from the slave device is packaged according to a specified protocol format, and the protocol packet is forwarded.
The FPGA further comprises:
and the clock calibration module is used for measuring the transmission delay among a plurality of devices in the initial power-on stage and carrying out clock calibration on the deserialized synchronous clock when a data/clock multiplexing bus is mounted with a plurality of synchronous time service and data transmission devices.
The clock calibration module can calibrate the synchronous clock on the data \ clock multiplexing bus so as to promote the synchronous sampling of the multiple slave devices controlled by each synchronous time service and data transmission device and further promote the accuracy and the speed of the synchronous sampling of the whole acquisition system.
Specifically, the forwarding memory controller includes:
the interface sub-controller is used for controlling the reading and writing operation of the parallel data in the dual-port RAM;
and the dual-port RAM is used for caching the parallel data in the forwarding memory controller.
Specifically, the device comprises two forwarding modules and two deserializers which correspond to the two forwarding modules one to one. Such an arrangement can satisfy most acquisition system applications and can reduce the volume of the acquisition system.
In the invention, the synchronous time service interface adopts a 485 chip, and the data receiving and transmitting interface adopts a 485 chip. The 485 transmission distance is dozens of meters to thousands of meters, and a plurality of slave devices are allowed to be connected on the bus, so that the application of a large-scale acquisition system is met.
The application of the miniaturized synchronous time service and data transmission device based on the FPGA is used for synchronously sampling a plurality of slave devices, and particularly comprises the following steps:
the serial deserializer deserializes data on the data \ clock multiplexing bus to obtain a synchronous clock and transmission data, and transmits the synchronous clock and the transmission data to the FPGA;
the FPGA sends the received synchronous clock to a plurality of slave devices through a synchronous time service interface, controls synchronous sampling of the plurality of devices, sends the received transmission data to the plurality of slave devices through a data receiving and sending interface, caches and encapsulates the transmission data uploaded by the plurality of slave devices, and forwards the transmission data to the serial deserializer.
Further, synchronously sampling a plurality of slave devices, further comprising the steps of:
when a data/clock multiplexing bus is mounted with a plurality of synchronous time service and data transmission devices, the transmission delay among the devices at the initial power-on stage is measured, and the deserialized synchronous clock is subjected to clock calibration.
In the present invention, the slave device may be any device capable of performing acquisition, such as various sensors.
The device overcomes the defects of large size, high complexity and insufficient long-distance transmission bandwidth of the system in major engineering, effectively improves the working performance of the system, ensures the bandwidth under the condition of long-distance transmission, and ensures that the slave devices cannot work asynchronously under the condition of long-distance transmission by the clock calibration function. Meanwhile, the device designed based on the clock/data bus multiplexing technology greatly reduces the complexity of the system, reduces the size and power consumption of the system due to the type selection of the miniaturized FPGA chip, and has great engineering application value.
Drawings
FIG. 1 is a schematic application diagram of a miniaturized synchronous time service and data transmission device based on an FPGA according to an embodiment;
fig. 2 is a schematic structural diagram of a miniaturized synchronous time service and data transmission device based on an FPGA according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 1 is an application schematic diagram of a miniaturized synchronous time service and data transmission device based on an FPGA according to an embodiment. As shown in fig. 1, three synchronous timing and data transmission devices 120 are connected to one data \ clock multiplexing bus 110, and decompose data on the clock/data multiplexing bus 110 to obtain synchronous clocks and transmission data, and the obtained synchronous clocks are used to control synchronous sampling of a plurality of slave devices 130 connected to the synchronous timing and data transmission devices 120.
In this embodiment, a schematic structural diagram of the synchronous time service and data transmission device 120 is shown in fig. 2, and specifically includes: 2 deserializers 210, an FPGA 220, a 485 chip 230, and a 485 chip 240, wherein the 485 chip 230 is a synchronous time service interface and is used for realizing transmission of a synchronous clock between the FPGA 220 and a plurality of slave devices; the 485 chip 240 is a data transceiving interface and is used for realizing transmission of data transmitted between the FPGA 220 and a plurality of slave devices; the FPGA 220 includes a clock generation module 221, a slave device control module 222, a forwarding memory controller 223, a forwarding module 224, and a clock calibration module 225, and further, the forwarding memory controller 223 includes 3 dual port RAMs 2231 and an interface sub-controller 2232.
The FPGA 220 is connected into a plurality of synchronous time service and data transmission device arrays in a cascading way through two data/clock multiplexing bus interfaces, each interface uses a serial deserializer 210 to separate transmission data from a synchronous clock, and the obtained synchronous clock is subjected to delay adjustment to obtain a synchronous clock of a slave device; the FPGA 220 sends out the obtained synchronous clock through the 485 chip 230 to complete the time service function of the slave device; the 485 chip 240 is used for performing data and command interaction functions with devices mounted below the 485 chip. For the data forwarding function, the FPGA 220 directly forwards the received data packets of other synchronous time service and data transmission devices in the array through the data \ clock multiplexing bus, performs serial-to-parallel conversion on the data uploaded from the device, stores the data into the internal cache RAM 2232, and then encapsulates the cache data according to the rules of the forwarding protocol and sends out the data packets through the data \ clock multiplexing bus interface.
The synchronous time service and data transmission device provided by the embodiment can complete serial deserializing of the data \ clock multiplexing bus, clock delay compensation, time service of the mounted slave module, data receiving and data forwarding.
The application specifically comprises the following contents:
after the fpga 220 is powered on, the clock calibration module 225 measures transmission delay of the data \ clock multiplexing bus, and determines clock calibration parameters;
b. the deserializer 210 deserializes the data on the data \ clock multiplexing bus, distinguishes clocks and transmission data, performs time delay calibration on the clocks according to the calibration parameters determined in the step a to generate synchronous clocks, and performs time service through the 485 chip 230;
c. the forwarding module 224 determines data on the data \ clock multiplexing bus, and forwards a data packet which is not sent to the node;
d. the slave device control module 222 polls all mounted slave modules to determine which slave modules upload data;
e. the slave device control module 222 performs data polling reception on the slave device determined in the step b through the 485 chip 240, performs serial-parallel conversion on the data, and stores the data into the cache RAM 2231;
f. when the RAM2231 is full of a certain amount of data, an interrupt is generated to notify the forwarding module 224 to forward the cached data;
g. the interface sub-controller 2232 reads out the buffered data, encapsulates the buffered data according to the forwarding protocol, and then forwards the buffered data.
The device provided by the embodiment realizes the decomposition of the synchronous clock and the transmission data in the clock/data multiplexing bus on the clock/data bus multiplexing technology, controls the synchronous sampling of a plurality of slave devices connected with the device by using the obtained synchronous clock, and improves the correctness of data sampling.
The above-mentioned embodiments are intended to illustrate the technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only the most preferred embodiments of the present invention, and are not intended to limit the present invention, and any modifications, additions, equivalents, etc. made within the scope of the principles of the present invention should be included in the scope of the present invention.
Claims (9)
1. A miniaturized synchronous time service and data transmission device based on FPGA is characterized by comprising:
the serial deserializer is used for deserializing data on the data \ clock multiplexing bus to obtain a synchronous clock and transmission data and transmitting the synchronous clock and the transmission data to the FPGA;
the FPGA is used for forwarding the received synchronous clock and the transmission data to a plurality of slave devices, controlling synchronous sampling of the slave devices and packaging the transmission data uploaded by the slave devices and forwarding the transmission data to the serial deserializer;
the synchronous time service interface is used for realizing the transmission of a synchronous clock between the FPGA and a plurality of slave devices;
and the data transceiving interface is used for realizing the transmission of data transmission between the FPGA and the plurality of slave devices.
2. The FPGA-based miniaturized synchronous time service and data transfer device of claim 1, wherein said FPGA comprises:
the clock generation module is used for sending the synchronous clock decoded by the serial deserializer to a slave device as a synchronous clock to complete data beat control of the slave device;
the slave device control module is used for finishing the control logic of the slave device and commanding the currently mounted slave device to upload data;
the forwarding memory controller is used for performing serial-parallel conversion on the data from the slave device and then caching the data, and forwarding the cached data under the scheduling of the forwarding module;
the forwarding module is used for forwarding data packets sent by other synchronous time service and data transmission devices; and meanwhile, the forwarding memory controller is scheduled, the data from the slave device is packaged according to a specified protocol format, and the protocol packet is forwarded.
3. The FPGA-based miniaturized synchronous time service and data transfer device of claim 2 wherein said FPGA further comprises:
and the clock calibration module is used for measuring the transmission delay among the plurality of synchronous time service and data transmission devices in the initial power-on stage and carrying out clock calibration on the deserialized synchronous clock when the plurality of synchronous time service and data transmission devices are mounted on one data/clock multiplexing bus.
4. The FPGA-based miniaturized synchronous time service and data transmission device according to claim 2 or 3, wherein the forwarding memory controller comprises:
the interface sub-controller is used for controlling the reading and writing operation of the parallel data in the dual-port RAM;
and the dual-port RAM is used for caching the parallel data in the forwarding memory controller.
5. The FPGA-based miniaturized synchronous time service and data transmission device according to claim 4, wherein the device comprises two forwarding modules and two deserializers corresponding to the two forwarding modules one to one.
6. The FPGA-based miniaturized synchronous timing and data transmission device as defined in claim 1, wherein the synchronous timing interface adopts 485 chips.
7. The FPGA-based miniaturized synchronous time service and data transmission device as defined in claim 1, wherein the data transceiver interface adopts a 485 chip.
8. An application method of a miniaturized synchronous time service and data transmission device based on an FPGA is characterized in that the synchronous time service and data transmission device of any one of claims 1-7 is applied to synchronously sample a plurality of slave devices, and specifically comprises the following steps:
the serial deserializer deserializes data on the data \ clock multiplexing bus to obtain a synchronous clock and transmission data, and transmits the synchronous clock and the transmission data to the FPGA;
the FPGA sends the received synchronous clock to the plurality of slave devices through the synchronous time service interface, controls synchronous sampling of the plurality of slave devices, sends the received transmission data to the plurality of slave devices through the data receiving and sending interface, caches and encapsulates the transmission data uploaded by the plurality of slave devices, and forwards the transmission data to the serial deserializer.
9. The method for applying the miniaturized synchronous time service and data transmission device based on the FPGA of claim 8, wherein the synchronous sampling is performed on a plurality of slave devices, further comprising the following steps:
when a plurality of synchronous time service and data transmission devices are mounted on one data/clock multiplexing bus, the transmission delay between the plurality of synchronous time service and data transmission devices at the initial power-on stage is measured, and the deserialized synchronous clock is subjected to clock calibration.
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| US11003206B1 (en) | 2020-01-03 | 2021-05-11 | Rockwell Collins, Inc. | Field-programmable gate array precision input timing |
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| EP2564530B1 (en) * | 2010-04-27 | 2014-03-26 | Transmode Systems AB | Data transmission involving multiplexing and demultiplexing of embedded clock signals |
| CN103077258B (en) * | 2012-12-30 | 2016-01-20 | 陕西海泰电子有限责任公司 | High-speed synchronous data acquiring card |
| CN103532560B (en) * | 2013-10-14 | 2017-03-08 | 中国科学院空间科学与应用研究中心 | A kind of digital correlator and digital complete polarization microwave radiometer |
| CN204334596U (en) * | 2014-12-24 | 2015-05-13 | 中国船舶重工集团公司第七一五研究所 | The remote high speed transmission system of a kind of low-power consumption based on RS485 and FPGA |
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