CN206532776U

CN206532776U - Multichip stacking encapsulation structure

Info

Publication number: CN206532776U
Application number: CN201720142097.9U
Authority: CN
Inventors: 彭弘; 彭一弘; 杜军
Original assignee: Chengdu Core Technology Co Ltd
Current assignee: Chengdu Core Technology Co Ltd
Priority date: 2017-02-17
Filing date: 2017-02-17
Publication date: 2017-09-29
Anticipated expiration: 2027-02-17

Abstract

The utility model discloses a kind of Multichip stacking encapsulation structure, substrate and multiple chips including rectangle, one of the substrate is while to set, also include two pad groups, the pad group is discontinuously arranged to linear by multiple pads, and two pad groups are located near the setting side of upper surface of base plate, and parallel with setting side, pad in two pad groups, to setting, the orthographic projection on side is not overlapping；The chip multiple-level stack is first positioned at the chip of bottom on substrate, and the projection on the chip to substrate on odd number piece is overlapping, and the projection on chip to substrate on even slice is also overlapping.The utility model can optimize signal arrangement, and same type signal type is come together, makes encapsulated signal integrality more preferable, and more facilitate in system-level PCB design, the height of chip itself can be borrowed, actual gold thread binding is without using chip booster material with interleaved during encapsulation.

Description

Multichip stacking encapsulation structure

Technical field

The utility model is related to a kind of chip-packaging structure, more particularly to a kind of Multichip stacking encapsulation structure.

Background technology

Chip-packaging structure, generally comprises substrate, pad, the multilayer chiop being arranged on pad, isolates multilayer chiop Separator, the separator can be bonding agent, can also be padded body.And chip upper surface is drawn by gold thread, and weld On pad, and the binding of the general gold thread for convenience of chip stack package, there are following several ways.Referring to Fig. 1 to Fig. 3.

As shown in figure 1, the number of plies stacked is more, chip size up is smaller, and shortcoming is：More up heap chip must be more Come smaller；As shown in Fig. 2 the chip stacked is tilted in one direction, shortcoming is：Banking, structure is asymmetric in direction, and And chip can only unilateral extraction signal；As shown in figure 3, adding padded body between stacked die, to facilitate the binding of gold thread, lack Put and be：Padded body is must be added between chip and chip.

And the shared shortcoming of above-mentioned three kinds of structures, it will be unable in the case of the pad in the middle of such as fruit chip using stacking knot There are two pads in the middle of structure, such as Fig. 4, chip, this chip will be unable to use stacked structure.

The content of the invention

The purpose of this utility model is that offer one kind solves the above problems, and to die size no requirement (NR) and need not make With booster material, facilitate the Multichip stacking encapsulation structure of gold thread winding displacement.

To achieve these goals, the technical solution adopted in the utility model is such：A kind of Multichip stacking encapsulation Structure, includes the substrate and multiple chips of rectangle, one of the substrate while to set, in addition to two pad groups are described Pad group is discontinuously arranged to linear by multiple pads, and two pad groups are located near the setting side of upper surface of base plate, and with setting Put that side is parallel, the pad in two pad groups, to setting, the orthographic projection on side is not overlapping；

The chip multiple-level stack is first positioned at the chip of bottom on substrate, and the core on odd number piece Projection on piece to substrate is overlapping, and the projection on the chip on even slice to substrate is also overlapping, and odd number piece and even slice Chip only overlap, overlapping be provided with adhesive linkage, first also is provided with adhesive linkage, chip upper surface between chip and substrate Connected provided with gold thread, and by gold thread with pad.

As preferred：Pad in the pad group is uniformly distributed.

Compared with prior art, the utility model has the advantage of：Any chip can all realize stacked structure, not die Whether centre has pad；Signal arrangement can be optimized, same type signal type is come together, makes encapsulated signal integrality more It is good, and more facilitate in system-level PCB design；The height of chip itself, actual gold thread can be borrowed during encapsulation with interleaved Binding is without using chip booster material.

Brief description of the drawings

Fig. 1 is the first Multichip stacking encapsulation structure in the prior art；

Fig. 2 is second of Multichip stacking encapsulation structure in the prior art；

Fig. 3 is the third Multichip stacking encapsulation structure in the prior art；

Fig. 4 is the structural representation that pad is provided with the middle part of chip；

Fig. 5 is the structural representation of the utility model bond pad arrangement；

Fig. 6 is the utility model structural representation.

In figure：1st, substrate；2nd, plastic packaging material；3rd, chip；4th, adhesive linkage；5th, padded body；6th, gold thread；7th, pad.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Embodiment 1：Referring to Fig. 1 to Fig. 4, in the prior art, the encapsulating structure of chip 3 generally comprises substrate 1, pad 7, set Multilayer chiop 3, the separator of isolation multilayer chiop 3 on pad 7, the separator can be bonding agent, can also be pad High body 5, chip 3 is packaged entirely through plastic packaging material 2 in addition, as shown in figure 1, the number of plies stacked is more, the chi of chip 3 up It is very little smaller, as shown in Fig. 2 the chip 3 stacked is tilted in one direction, as shown in figure 3, plus padded between stacked die 3 Body 5, to facilitate the binding of gold thread 6.There are two pads 7 in the middle of such as Fig. 4, chip 3, this chip 3 will be unable to use stacked structure.

Referring to Fig. 5 to Fig. 6, in the utility model, a kind of stack package structure of multi-chip 3, including the substrate 1 of rectangle and many Individual chip 3, one of the substrate 1 while to set, in addition to two 7 groups of pads, 7 groups of the pad by multiple pads 7 not Continuous to be arranged to linear, two 7 groups of pads are located near the setting side of the upper surface of substrate 1, and parallel with setting side, two pads 7 Pad 7 in group, to setting, the orthographic projection on side is not overlapping；

The multiple-level stack of chip 3 is first positioned at the chip 3 of bottom on substrate 1, and on odd number piece Projection on chip 3 to substrate 1 is overlapping, and the projection on the chip 3 on even slice to substrate 1 is also overlapping, and odd number piece and The chip 3 of even slice only overlaps, and overlapping is provided with adhesive linkage 4, and adhesive linkage also is provided between first chip 3 and substrate 1 4, the upper surface of chip 3 is provided with gold thread 6, and is connected by gold thread 6 with pad 7, and the pad 7 in 7 groups of the pad is uniformly distributed.

The utility model is connected up the pad 7 of chip 3 again before conventional package step is carried out to original surface of chip 3 The arrangement position of pad 7 can be optimized in rearrangement, wiring process；Stacked package is carried out, its structure is by means of chip 3 itself Thickness eliminates padded body 5.

Claims

1. a kind of Multichip stacking encapsulation structure, includes the substrate and multiple chips of rectangle, it is characterised in that：The one of the substrate It is individual while to set, in addition to two pad groups, the pad group is discontinuously arranged to linear, two pad groups by multiple pads Near the setting side of upper surface of base plate, and with set side it is parallel, the pad in two pad groups, to set side orthographic projection not It is overlapping；

The chip multiple-level stack is first positioned at the chip of bottom on substrate, and the chip on odd number piece is arrived Projection on substrate is overlapping, and the projection on the chip on even slice to substrate is also overlapping, and the core of odd number piece and even slice Piece only overlaps, and overlapping is provided with adhesive linkage, and first also is provided with adhesive linkage between chip and substrate, chip upper surface is provided with Gold thread, and connected by gold thread with pad.

2. Multichip stacking encapsulation structure according to claim 1, it is characterised in that：Pad in the pad group is uniform Distribution.