CN109755182A - Chip stack package structure and forming method thereof - Google Patents
Chip stack package structure and forming method thereof Download PDFInfo
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- CN109755182A CN109755182A CN201711085239.3A CN201711085239A CN109755182A CN 109755182 A CN109755182 A CN 109755182A CN 201711085239 A CN201711085239 A CN 201711085239A CN 109755182 A CN109755182 A CN 109755182A
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- chip
- connection terminal
- stacking area
- wafer stacking
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention provides a kind of chip stack structure and forming method thereof, by successively misplace be laminated multiple one end have chip connection terminal chip, and guarantee that the ends exposed of the upper chip in adjacent two layers chip goes out the part of the surface or all surfaces of the chip connection terminal of lower chip in lamination process, traditional adhesive is further used between adjacent two layers chip to replace DAF, thus reduce packaging height and cost.
Description
Technical field
The present invention relates to ic manufacturing technology field more particularly to a kind of chip stack package structure and its formation sides
Method.
Background technique
Stacked package technology, also referred to as 3D or three-dimensional packaging technology are one of multi-chip package technologies of current mainstream,
Can by least two semiconductor wafers (Die, also referred to as bare die, i.e., one piece be cut into from wafer have complete function
Block) or packaging body stack up in vertical direction, be commonly used to manufacture memory chip, logic chip, the electricity such as processor chips
Subcomponent.With the development of electronic industry, high capacity, Gao Gongneng, high speed and the small size of increasingly desirable electronic component, in order to full
The foot demand, needs be incorporated to more multi-wafer in a single package, while also to keep low packaging height, at this time stacked package
The each chip stacked in structure can generally do it is thinner, however, the problems such as relatively thin chip is easy to appear crackle or warpage, shadow
Ring the performance of encapsulating structure.
Summary of the invention
The purpose of the present invention is to provide a kind of chip stack package structures and forming method thereof, can reduce encapsulating structure
Whole height and cost.
To achieve the goals above, the present invention provides a kind of chip stack package structure, comprising:
The upper surface of substrate with upper and lower surfaces, the substrate is equipped with wafer stacking area, the wafer stacking
At least one end in area is provided with substrate connection terminal；
Multiple one end have the chip of chip connection terminal, and successively dislocation is layered in the wafer stacking area, and adjacent
Upper chip in two layer wafers exposes the part of the surface or all surfaces of the chip connection terminal of lower chip；
A plurality of leads connects the substrate connection terminal and corresponding chip connection terminal, or two crystalline substances of connection
Piece connection terminal.
Optionally, the chip stack package structure further includes first adhesive and second adhesive, first bonding
Agent is consolidated between the wafer stacking area and undermost chip and by the wafer stacking area and undermost wafer bonding
Fixed, the second adhesive is fixed between adjacent two layers chip and by the adjacent two layers wafer bonding.
Optionally, the first adhesive is identical with the material of second adhesive, and thickness is respectively less than 10 μm.
Optionally, the chip stack package structure further includes packing colloid and soldered ball, and the packing colloid is located at described
On the upper surface of substrate and all wafers and all leads are covered, the soldered ball is located on the lower surface of the substrate.
Optionally, the both ends in the wafer stacking area are respectively arranged with a substrate connection terminal, the wafer stacking area
In all wafers of upper stacking, projection of the chip connection terminal of at least two layers adjacent chip in the wafer stacking area is lived apart
End where two substrate connection terminals in the wafer stacking area.
Optionally, in all wafers stacked in the wafer stacking area, there is the chip connection terminal of continuous multilayer chip
End where being respectively positioned on the substrate connection terminal in the wafer stacking area in the projection in the wafer stacking area, the continuous multilayer are brilliant
One end that piece is equipped with chip connection terminal constitutes step structure.
Optionally, the chip connection terminal of all wafers stacked in the wafer stacking area is in the wafer stacking area
Projection is respectively positioned on end where the substrate connection terminal in the wafer stacking area, and all wafers stacked in the wafer stacking area are set
There is one end of chip connection terminal to constitute step structure.
Optionally, the both ends in the wafer stacking area are respectively arranged with a substrate connection terminal, the wafer stacking area
In all wafers of upper stacking, the chip connection terminal of the continuous multilayer chip at least one section of stack height is in the chip
The projection of stack region is respectively positioned on end where a substrate connection terminal in the wafer stacking area, and it is high that at least there are also another section of stackings
Projection of the connection terminal of continuous multilayer chip in degree in the wafer stacking area is respectively positioned on the another of the wafer stacking area
End where a substrate connection terminal, one end that every section of continuous multilayer chip is equipped with chip connection terminal constitute a Step-edge Junction
Structure.
The present invention also provides a kind of forming methods of one of above-mentioned chip stack package structure, comprising the following steps:
The substrate with upper and lower surfaces is provided, the upper surface of the substrate is equipped with wafer stacking area, the chip
At least one end of stack region is formed with a substrate connection terminal；
Successively the chip that multiple one end have chip connection terminal, adjacent two layers are laminated in dislocation in the wafer stacking area
The ends exposed of upper chip in chip goes out the part of the surface or all surfaces of the chip connection terminal of lower chip；
It is formed by lead key closing process and connects the substrate connection terminal and corresponding chip connection terminal or two
The lead of chip connection terminal.
Optionally, successively the chip that multiple one end have chip connection terminal is laminated in dislocation in the wafer stacking area
When, first adhesive is stated by coating on wafer stacking area surface with by the wafer stacking area and undermost chip
It is adhesively fixed；By second adhesive being coated on the surface of lower chip mutually to glue lower chip with adjacent upper chip
It closes and fixes.
Optionally, the first adhesive is identical with the material of second adhesive, and thickness is respectively less than 10 μm.
Optionally, the forming method, further includes: after the completing of all leads, formed and be located at the substrate
Upper surface on and cover the packing colloids of all wafers and all leads, and add soldered ball in the lower surface of the substrate
Form entire chip stack package structure.
Optionally, the both ends in the wafer stacking area are respectively arranged with a substrate connection terminal, in the wafer stacking
When successively chip of multiple one end with chip connection terminal is laminated in dislocation in area, the chip connection of at least two layers adjacent chip
Terminal is at end where two substrate connection terminals in the projection separation wafer stacking area in the wafer stacking area.
Optionally, successively the chip that multiple one end have chip connection terminal is laminated in dislocation in the wafer stacking area
When, in all wafers that stack in the wafer stacking area, there is the chip connection terminal of continuous multilayer chip in the stack of wafers
The projection in folded area is respectively positioned on end where the substrate connection terminal in the wafer stacking area, and the continuous multilayer chip connects equipped with chip
One end of connecting terminal constitutes step structure.
Optionally, successively the chip that multiple one end have chip connection terminal is laminated in dislocation in the wafer stacking area
When, projection of the chip connection terminal of all wafers stacked in the wafer stacking area in the wafer stacking area is respectively positioned on institute
The substrate connection terminal place end in wafer stacking area is stated, all wafers stacked in the wafer stacking area are equipped with chip connecting pin
One end of son constitutes step structure.
Optionally, the both ends in the wafer stacking area are respectively arranged with a substrate connection terminal, in the wafer stacking
When successively dislocation is laminated multiple one end and has the chip of chip connection terminal in area, all crystalline substances for being stacked in the wafer stacking area
In piece, projection of the chip connection terminal of the continuous multilayer chip at least one section of stack height in the wafer stacking area is equal
Positioned at end where a substrate connection terminal in the wafer stacking area, at least there are also the continuous multilayers in another section of stack height
Projection of the connection terminal of chip in the wafer stacking area is respectively positioned on another substrate connection terminal in the wafer stacking area
Place end, one end that every section of continuous multilayer chip is equipped with chip connection terminal constitute a step structure.
Compared with prior art, technical solution of the present invention has the advantages that
1, the chip that multiple one end have chip connection terminal is laminated by successively misplacing, the upper layer in adjacent two layers chip
Chip exposes the part of the surface or all surfaces of the chip connection terminal of lower chip, on the one hand, each upper chip is only
Need to misplace the size of very little, can reserve the space of wire bonding, it is ensured that the fastness of chip stack package structure, no
It can collapse；On the other hand, the interlayer spacing of stacked wafer can be substantially reduced, and can guarantee that upper chip bottom will not
The lead for touching lower chip, avoids component failure；
2, traditional adhesive can be used between the chip being laminated to substitute bonding die film (DAF), to substantially reduce encapsulation
Cost；
3, a substrate connection terminal is respectively set at the both ends in wafer stacking area, is stacked in the wafer stacking area
In all wafers, the projection of the chip connection terminal of at least two layers adjacent chip in the wafer stacking area is lived apart the chip
The both ends of stack region constitute snakelike (Snake-Shape) stacked structure, while reducing overall packaging height, additionally it is possible to flat
Distribution of the stress that weighing apparatus stacked offset chip generates in the wafer stacking area, further enhances chip stack package structure
Fastness and reliability, at the same can also balanced packing colloid distribution, avoid that warpage or stripping problem occurs.
Detailed description of the invention
Fig. 1 is a kind of diagrammatic cross-section of chip stack package structure；
Fig. 2A to Fig. 2 F is the diagrammatic cross-section of the chip stack package structure of the specific embodiment of the invention；
Fig. 3 is the forming method flow chart for the chip stack structure that the present invention is embodied.
Specific embodiment
In the world of information explosion now, integrated circuit has inseparable relationship with daily life, no matter in food clothing
Firmly row or amusement aspect, all can often use product composed by integrated circuit component.With the continuous evolution of electronics technology, more
Hommization, functional more complicated electronic product continue to introduce new, many electronic products, such as hand-held class, wearing class etc. are just
Electronic product is taken, is designed towards light, thin, short, small trend, to provide more convenient comfortable use.
In semiconductor technology, the generation of integrated circuit (Integrated Circuits, IC) is broadly divided into three ranks
Section: the manufacture of silicon chip, the production of integrated circuit and encapsulation of integrated circuit (Package) etc..With regard to the encapsulation of integrated circuit
For, this is the final step for completing integrated circuit finished product, and encapsulation is designed to provide chip (Die) and printed circuit board
The medium and protection chip being electrically connected between (Printed Circuit Board, PCB) or other appropriate elements.Stack envelope
Dress technology is one of encapsulation technology of integrated circuit, compares other encapsulation technologies, can be realized more multi-functional, higher capacity
And smaller szie, for example identical memory (Memory) chip is stacked, the appearance of the memory chip finally obtained can be increased
Amount.
Please refer to Fig. 1, a kind of chip stack (Stacked-die) encapsulating structure include: substrate 10, multiple chips 11 and
Bonding wire 13, multiple chips 11 are configured in a stacked fashion on substrate 10, and substrate 10 passes through adhesive phase 12 and the first of stacking
11 fixed engagement of wafer is come by bonding die films (die-attach film, DAF) such as thermal bonding tape between adjacent two layers chip 12
Fixed engagement is drawn on the chip connection terminal 111 at each 11 both ends of chip by wire bonding (Wire Bond) technique
One lead 14 and the substrate connection terminal 101 for being bonded to substrate 10, so that each chip 11 and substrate 10 are electrically connected.It is subsequent
Substrate 10, multiple chips 11 and lead 14 can be covered with packing colloid (Molding Compound), and in the substrate 10
Bottom form entire chip stack package structure plus soldered ball 102 (Solid Ball).
DAF 12 is used in above-mentioned chip stack package structure between two adjacent chips 11, it can be to avoid paste
Adhesive by lead key closing process heating power influence and the problem of soften, be conducive to control the lead thicknesses in wafer surface
(Bond Line Thickness, BLT).The cost of DAF is more expensive than traditional paste adhesive very much, and the thickness usually required
(i.e. the thickness of DAF 12) is 15 μm~20 μm, can provide enough spaces to implement wire bonding operation, otherwise upper layer
Chip 11 bottom can touch lower layer 11 surface of chip lead 14, cause component failure, it is clear that the use of DAF will limit
The reduction of the height and cost of entire encapsulating structure.
In order to reduce the height and cost of entire encapsulating structure, the present invention provides a kind of chip stack package structure and its shape
At method, the core of technical solution is, by successively misplace be laminated multiple one end have chip connection terminal chip, and
Guarantee that the ends exposed of the upper chip in adjacent two layers chip goes out the portion of the chip connection terminal of lower chip in lamination process
Divide surface or all surfaces, further uses traditional adhesive between adjacent two layers chip to replace DAF, to be formed newly
Chip stack structure.
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.
Fig. 2A is please referred to, one embodiment of the invention provides a kind of chip stack package structure, comprising: have upper surface under
The substrate 20 on surface, multiple one end have the chip and a plurality of leads of chip connection terminal.The substrate 20 can be without
Stripe shape (strip level) substrate or template (panel level) substrate of cutting, can also be by cutting stripe shape substrate or
Template substrate and the unit package substrate formed.The substrate 20 can be naked silicon substrate, be also possible to be formed with electronic component
Or the device substrate of the functional block of electronic component integration.The upper surface of the substrate 20 is equipped with one or more wafer stackings
Area, at least one end in each wafer stacking area are equipped with substrate connection terminal 201, substrate connection terminal 201 may include gold, nickel and
At least one of lead.In the present embodiment, by taking a wafer stacking area as an example, the left and right ends in the wafer stacking area are equipped with
One substrate connection terminal 201.
In the present embodiment, the multiple wafer stacking is in the wafer stacking area, and these chips are divided into two types,
As shown in the chip 21a and 21b in Fig. 2A, the chip connection terminal of both chips is located at different ends, the chip in Fig. 2A
The left end of chip 21a is arranged in the chip connection terminal 211 of 21a, i.e. projection of the chip 21a in wafer stacking area is located at stack of wafers
The left end in folded area, in order to be connect subsequently through lead with the substrate connection terminal 201 of the left end in wafer stacking area, in Fig. 2A
The right end of chip 21b is arranged in the chip connection terminal 211 of chip 21b, i.e. projection of the chip 21b in wafer stacking area is located at crystalline substance
The right end of piece stack region, in order to be connect subsequently through lead with the substrate connection terminal 201 of the right end in wafer stacking area.?
The all wafers stacked in the wafer stacking area form snakelike (Snake-Shape) stacking by way of the stacking that successively misplaces
Structure.In the serpentine-shaped stack structure, the chip connection terminal 211 of the continuous multilayer chip at least one section of stack height exists
The projection in the wafer stacking area is respectively positioned on end where a substrate connection terminal in the wafer stacking area 21, and at least there are also another
Projection of the connection terminal of continuous multilayer chip in one section of stack height in the wafer stacking area is respectively positioned on the stack of wafers
End where another substrate connection terminal in folded area, one end that every section of continuous multilayer chip is equipped with chip connection terminal are constituted
One step structure.Such as in Fig. 2A, the chip (chip connection terminal is arranged at left end) of continuous multilayer 21a type successively to
Dextroposition forms continuous multilayer chip 21 ', i.e., the upper chip in continuous multilayer chip 21 ' is with respect to lower chip to dextroposition one
Scale cun, to expose all surfaces or part of the surface of the chip connection terminal of lower chip, in continuous multilayer chip 21 '
The left end (one end that i.e. each chip is equipped with chip connection terminal) of all wafers constitutes a step structure；Continuous multilayer 21b
Successively dislocation forms continuous multilayer chip 21 " to the chip (chip connection terminal is arranged at right end) of type to the left, i.e., continuous more
Upper chip in layer wafer 21 " misplaces certain size to the left with respect to lower chip, to expose the chip connection of lower chip
The all surfaces or part of the surface of terminal, (i.e. each chip is equipped with chip to the right end of all wafers in continuous multilayer chip 21 "
One end of connection terminal) constitute step structure.In the present embodiment, since the upper surface of substrate 20, continuous multilayer chip 21 ' and
Continuous multilayer chip 21 " is alternately stacked until the chip of required stacking is all stacked and finished, wherein each section of continuous multilayer chip
21 ' stacking number can be the same or different, and the stacking number of each section of continuous multilayer chip 21 " can be identical or not
Together, the stacking number of adjacent continuous multilayer chip 21 ' and continuous multilayer chip 21 " can be the same or different, such as Fig. 2A
In, the number of plies of the first segment continuous multilayer chip 21 ' stacked gradually on substrate 20 is 3, the layer of first segment continuous multilayer chip 21 "
Number is 4, and the number of plies of second segment continuous multilayer chip 21 ' is 4, and the number of plies of second segment continuous multilayer chip 21 " is 5, it is possible thereby to
Form the chip-packaging structure of 16 layer wafers stacking.
In order to reduce the difficulty of lead key closing process, shortest lead is used as far as possible, the chip stack package structure is also
Including a plurality of leads 241 and a plurality of leads 242, lead 242 is used to connect the chip connection terminal of upper chip and lower chip
211, lead 241 is for connecting corresponding chip connection terminal 211 and corresponding substrate connection terminal 201.In the present embodiment, respectively
Chip connection terminal 211 in section continuous multilayer chip 21 ' and each section of continuous multilayer chip 21 " passes through corresponding lead respectively
242 are sequentially connected, i.e. the chip connection terminal 211 of upper chip chip that lower chip is connected to by corresponding lead 242
Connection terminal 211, and in every section of continuous multilayer chip 21 ' chip of the bottom chip connection terminal 211 by drawing accordingly
Line 241 is connected in the substrate connection terminal 201 of wafer stacking area left end, the crystalline substance of the bottom in every section of continuous multilayer chip 21 "
The chip connection terminal 211 of piece is connected in the substrate connection terminal 201 of wafer stacking area right end by corresponding lead 241.
In the present embodiment, the chip stack package structure further includes first adhesive 22 and second adhesive 23, described
First adhesive 22 is located between the wafer stacking area and undermost chip of 20 upper surface of substrate, and by the stack of wafers
Folded area and undermost wafer bonding are fixed, i.e., can pass through coating heat when the first wafer 21a is stacked in wafer stacking area
Solidify or the first adhesive 22 of photocuring pastes the first wafer 21a on wafer stacking area surface, first adhesive
22 be liquid, gel or semisolid paste, passes through coating processes film to wafer stacking area surface.The second adhesive
23 be liquid, gel or semisolid paste, is consolidated between adjacent two layers chip and by the adjacent two layers wafer bonding
It is fixed.Optionally, the first adhesive 22 is identical with the material of second adhesive 23, and thickness is respectively less than 10 μm, for example, 5 μm,
To reduce packaging cost and height.The thickness of the second adhesive 23 can be less than or equal to the thickness of the first adhesive 22
Degree.
In the present embodiment, the chip stack package structure further includes packing colloid (not shown) and soldered ball 25, the envelope
Dress colloid is located on the upper surface of substrate 20, and covers the substrate 20, all wafers and all leads, and the soldered ball 25 is located at
On the lower surface of the substrate 20.
The chip stack structure of the present embodiment is used to be alternately stacked by continuous multilayer chip 21 ' and continuous multilayer chip 21 "
The serpentine-shaped stack structure of formation, since the chip connection terminal of every layer wafer in serpentine-shaped stack structure can be all or part of
While being exposed, therefore sufficient operating space can be provided for subsequent lead key closing process, additionally it is possible to reduce lead
Thickness, and then reduce the height of entire encapsulating structure.Simultaneously as continuous multilayer chip 21 ' and continuous multilayer chip 21 " are handed over
For stacking, stress caused by misplacing can on wafer stacking area surface equiblibrium mass distribution, avoid lamination problem caused by stress,
Enhance reliability.Further, since continuous multilayer chip 21 ' and continuous multilayer chip 21 " are alternately stacked, the subsequent encapsulation in coating
The contact relative equilibrium of colloid and 20 surface of substrate avoids causing asking for serious warpage because thermal expansion coefficient (CTE) is mismatched
Topic.
Referring to FIG. 3, the present embodiment also provides a kind of forming method of chip stack structure, comprising the following steps:
S1, provides the substrate with upper and lower surfaces, and the upper surface of the substrate is equipped with wafer stacking area, the crystalline substance
At least one end of piece stack region is formed with a substrate connection terminal；
S2, successively the chip that multiple one end have chip connection terminal is laminated in dislocation in the wafer stacking area, adjacent
The ends exposed of upper chip in two layer wafers goes out the part of the surface or all surfaces of the chip connection terminal of lower chip；
S3 is formed by lead key closing process and is connected the substrate connection terminal and corresponding chip connection terminal or two
The lead of a chip connection terminal.
Fig. 2A is please referred to, the substrate 20 provided in the step S1 of the present embodiment has the upper surface being disposed opposite to each other and following table
Face, upper surface are equipped at least one wafer stacking area, and the both ends in each wafer stacking area are equipped with substrate connection terminal 201,
Illustrate technical solution of the present invention by taking a wafer stacking area as an example in the present embodiment.
Please continue to refer to Fig. 2A, in the step S2 of the present embodiment, multiple chips to be stacked are divided into two classes: chip connecting pin
A kind of chip 21a of left end is arranged in son and a kind of chip 21b of left end is arranged in chip connection terminal.In wafer stacking area
First adhesive 22 is first coated, is then picked up using precision and puts equipment the first wafer 21a of pickup, by itself and wafer stacking Qu Zhongwei
Its reserved reserved location fine registration simultaneously mounts together, so that on its surface for being stacked on substrate 20；Then, second is coated
Adhesive 23 is picked up using precision and puts equipment the second wafer 21a of pickup, it is certain to dextroposition with respect to first wafer 21a
Size is aligned and mounts together so that the part of the surface of its chip connection terminal 211 for exposing the first wafer 21a or
All surfaces；Then be coated with second adhesive 23, picked up using precision and put equipment and pick up third wafer 21a, by its opposite the
Two wafer 21a are aligned to dextroposition certain size and mount together, so that its chip for exposing the second wafer 21a connects
The part of the surface or all surfaces of connecting terminal 211；..., and so on, until the stack height of chip 21a reaches predetermined height
Degree forms first segment continuous multilayer chip 21 '.Then on the surface chip 21a of 21 ' top of first segment continuous multilayer chip
Second adhesive 23 is coated, is picked up using precision and puts equipment the first wafer 21b of pickup, the chip of the relatively described top in left end
The left end of 21a is aligned to dextroposition certain size and mounts together, so that its chip connection for exposing the first wafer 21b
The part of the surface or all surfaces of terminal 211；It is then coated second adhesive 23 and is picked up using precision and put equipment pickup second
Wafer 21b, the right end of the relatively described first wafer 21b of the right end certain size that misplaces to the left are aligned and mount together,
So that the part of the surface or all surfaces of its chip connection terminal 211 for exposing the second wafer 21b；Then it is coated with
Two adhesives 23 and use precision, which are picked up, puts equipment pickup third wafer 21b, the right side of the relatively described second wafer 21b of right end
Dislocation certain size is aligned and mounts together to the left at end, so that its chip connection terminal 211 for exposing the second wafer 21b
Part of the surface or all surfaces；..., and so on, until the stack height of chip 21b reaches predetermined altitude, form the
One section of continuous multilayer chip 21 ".And then second segment continuous multilayer chip 21 ', second segment company are sequentially formed as procedure described above
Continuous multi-layer crystal chip 21 ", third section continuous multilayer chip 21 ', third section continuous multilayer chip 21 " ..., until all wafers heap
It is folded to complete, to form the serpentine-shaped stack structure that continuous multilayer chip 21 ' and continuous multilayer chip 21 " are alternately stacked, wherein occuping
The continuous multilayer chip 21 " of the right end of the bottom chip 21a of the continuous multilayer chip 21 ' of top lower section relatively adjacent thereto
The right end of top chip misplace to the left certain size, to expose the top chip of the continuous multilayer chip 21 " of lower section
Chip connection terminal 211 part of the surface or all surfaces.The wherein thickness of first adhesive 22 and second adhesive 23
It can be 5 μm, be achieved in and more appropriate space is provided for subsequent lead key closing process, while it is high that encapsulation is greatly reduced
Degree.
Please continue to refer to Fig. 2A, in the step S3 of the present embodiment, passes through lead key closing process and formed and connect the substrate and connect
The lead 241 of connecting terminal and corresponding chip connection terminal and the lead 242 for connecting two adjacent chip connection terminals.Specifically
Ground, the chip connection terminal 211 in every section of continuous multilayer chip 21 " pass sequentially through shorter lead 242 and connect, and every section continuous
The chip connection terminal 211 of bottom chip in multi-layer crystal chip 21 " is connected to the base of wafer stacking area right end by lead 241
On plate connection terminal 201；Chip connection terminal 211 in every section of continuous multilayer chip 21 ' passes sequentially through shorter lead 242 and connects
It connects, and the chip connection terminal 211 of the bottom chip in every section of continuous multilayer chip 21 ' is connected to chip by lead 241
In the substrate connection terminal 201 of stack region left end.
It later, can be using wafer scale injection molding (wafer level molding) technique surface and all on the base plate 20
Packing colloid (not shown) is covered on the surface of chip, all wafers and lead package are closed, the wafer scale
Shooting Technique specifically: the substrate that heap folds chip is put into injection molding machine, is carried out with thermosetting property or light solidity injection sealed material
Coating or casting, and further it is formed by curing packing colloid.The material of the packing colloid may include the resins such as epoxy resin
Material.In other embodiments of the invention, it can also carry out squeezing using thermoplastic forming the packing colloid.Later
Soldered ball 25 can also be formed in the lower surface of substrate 20 by soldering process, to complete the encapsulation of chip stack structure.
In other embodiments of the invention, it when the upper surface of substrate 20 is equipped with multiple wafer stacking areas, is being formed
After packing colloid and soldered ball 25, (Die Saw) can be cut along the cutting line of the substrate 20, to realize each core
The separation of piece.
The forming method of the chip stack structure of the present embodiment, by forming serpentine-shaped stack structure, to reduce packaging height,
Distribution of the packing colloid on substrate can be balanced simultaneously, substrate is avoided warpage to occur and because being layered caused by wrong stress
Problem improves encapsulation performance.In addition, also DAF is substituted by second adhesive, to reduce packaging cost.
Fig. 2 B is please referred to, another embodiment of the present invention provides a kind of chip stack structures, including with upper surface and following table
Chip 21a, multiple right end of the substrate 20, multiple left ends in face with chip connection terminal 211, which have, impregnates connection terminal 211
Chip 21b, a plurality of leads 241 and 242.The upper surface of the substrate 20 may include one or more wafer stacking areas, described
The left and right ends in wafer stacking area are equipped with a substrate connection terminal 201.Chip 21a and chip 21b be successively in the present embodiment
It is alternately stacked into the wafer stacking area, forms a kind of serpentine-shaped stack structure, wherein the left end of every layer wafer 21b is with respect to lower section
The left end of the chip 21a of abutting is to dextroposition certain size, to expose the chip connection terminal of the chip 21a of the abutting of lower section
Some or all of 211 surfaces, the right end for the chip 21a that the right end of every layer wafer 21b is close to relatively above misplace centainly to the left
Size, to expose oneself chip connection terminal 211.It is viscous by second between adjacent chip in the serpentine-shaped stack structure
Mixture 23 is adhesively fixed, be bonded by first adhesive 22 between the chip of the bottom and substrate 20 in the serpentine-shaped stack structure
It is fixed.The embodiment of the present invention chip stack package structure further includes a plurality of leads 241 and a plurality of leads 242, and lead 242 is used for
The chip connection terminal 211 of upper chip and lower chip is connected, lead 241 is for connecting corresponding chip connection terminal 211
Pass through the corresponding lead 242 in left side with the chip connection terminal 211 of corresponding substrate connection terminal 201, such as all wafers 21a
It is sequentially connected, the chip connection terminal 211 of all wafers 21b is sequentially connected by the corresponding lead 242 in right side, the snakelike heap
The chip connection terminal 211 of the chip of the bottom and the substrate connection terminal 201 of corresponding end are connected by lead 241 in stack structure
It connects.The chip stack package structure further includes packing colloid (not shown) and soldered ball 25, and the packing colloid is located at substrate 20
Upper surface on and cover the upper surfaces of all wafers and all leads 24 and the substrate 20, the soldered ball 25 is located at described
On the lower surface of substrate 20.
Compared with the chip stack structure of the present embodiment chip stack structure shown in Fig. 2A, shown in actually Fig. 2A
A kind of limiting case of serpentine-shaped stack structure, the every section of continuous multilayer chip 21 ' and every section of continuous multilayer crystalline substance being equivalent in Fig. 2A
The number of plies of piece 21 " is 1.Compared with the present embodiment chip stack structure shown in Fig. 2A, the coating position of second adhesive can
With identical, it is possible thereby to require adjustment substrate position or adhesive spray head position when avoiding coating second adhesive every time
It sets, simplifies operation, while the caused stress that misplaces between chip is more balanced, while reducing identical height, is answered by dislocation
Warpage caused by power and lamination problem can more be improved, and reliability is higher.
The forming method of the chip stack structure of the present embodiment can also refer to Fig. 3, the chip stack structure shape with Fig. 2A
It is at the difference of method, in step S2, needs chip 21a and chip 21b to be spaced apart from each other and be alternately stacked, chip connection terminal
211 chips that the same end is arranged in will not be stacked continuously, remaining process is all the same, and details are not described herein.
Fig. 2 C is please referred to, another embodiment of the present invention provides a kind of chip stack structure, including with upper surface under
Chip 21a, multiple right end of the substrate 20, multiple left ends on surface with chip connection terminal 211, which have, impregnates connection terminal 211
Chip 21b, a plurality of leads 241 and 242, packing colloid and soldered ball 25.The upper surface of the substrate 20 is equipped at least one
Wafer stacking area, the left and right ends in the wafer stacking area are provided with substrate connection terminal 201, and all wafers successively misplace stacking
In the wafer stacking area, and the ends exposed of the upper chip in adjacent two layers chip goes out the chip connecting pin of lower chip
The part of the surface or all surfaces of son, form another serpentine-shaped stack structure.A plurality of leads 242 is for connecting corresponding two
Chip connection terminal 211, a lead 242 connect the substrate connection terminal 201 of bottom chip 21a and left end, a lead
The substrate connection terminal 201 of 242 connection bottom chip 21b and right end, packing colloid are located on the upper surface of the substrate 20
And upper surface, all wafers and the lead of substrate 20 are covered, soldered ball is located on the lower surface of substrate 20.
The chip stack structure of the present embodiment also can be realized reduce packaging height and packaging cost effect, with Fig. 2A and
Chip stack structure shown in Fig. 2 B is compared, a kind of deformation of chip stack structure shown in actually Fig. 2A and Fig. 2 B,
Serpentine-shaped stack structure be substantially shown in Fig. 2 B on the basis of serpentine-shaped stack structure insertion one section by multi-layer crystal chip 21a successively
Dislocation (i.e. the left end of upper chip is staggered certain size to the left with respect to the left end of lower chip) stacks the continuous multilayer crystalline substance formed
Piece 21 ', the position of continuous multilayer chip 21 ' can be at any end height of entire stacked structure, be equivalent in Fig. 2A
Shown in serpentine-shaped stack structure, the number of plies of every section of continuous multilayer chip 21 " is 1, and the layer of each section of continuous multilayer chip 21 '
Number is more than or equal to 1, for example, 1,3,4,5 etc..
The forming method of the chip stack structure of the present embodiment can refer to Fig. 3, be formed with the chip stack structure of Fig. 2A
The difference of method is, in step S2, chip 21a and chip 21b is needed to be spaced apart from each other and be alternately stacked in some stack height,
It needs continuously to be misplaced to the left with continuous stacked multilayer chip 21a in some stack height, remaining process is all the same, no longer superfluous herein
It states.
Fig. 2 D is please referred to, another embodiment of the present invention provides a kind of chip stack structure, including with upper surface under
Chip 21a, multiple right end of the substrate 20, multiple left ends on surface with chip connection terminal 211, which have, impregnates connection terminal 211
Chip 21b, a plurality of leads 241 and 242, packing colloid and soldered ball 25.The upper surface of the substrate 20 is equipped at least one
Wafer stacking area, the left and right ends in the wafer stacking area are provided with substrate connection terminal 201, and all wafers successively misplace stacking
In the wafer stacking area, and the ends exposed of the upper chip in adjacent two layers chip goes out the chip connecting pin of lower chip
The part of the surface or all surfaces of son, form another serpentine-shaped stack structure.A plurality of leads 242 is for connecting corresponding two
Chip connection terminal 211, a lead 242 connect the substrate connection terminal 201 of bottom chip 21a and left end, a lead
The substrate connection terminal 201 of 242 connection bottom chip 21b and right end, packing colloid cover substrate 20, all wafers and draw
Line, soldered ball are located on the lower surface of substrate 20.
The chip stack structure of the present embodiment also can be realized the effect for reducing packaging height and packaging cost, with Fig. 2 C institute
The chip stack structure shown is compared, and the continuous multilayer chip 21 ' in serpentine-shaped stack structure is replaced by continuous multilayer chip
21 ", the position of continuous multilayer chip 21 " can be at any end height of entire stacked structure, be equivalent in Fig. 2A institute
In the serpentine-shaped stack structure shown, the number of plies of every section of continuous multilayer chip 21 ' is 1, and the number of plies of each section of continuous multilayer chip 21 "
More than or equal to 1, for example, 1,3,4,5 etc..
The forming method of the chip stack structure of the present embodiment can refer to Fig. 3, be formed with the chip stack structure of Fig. 2A
The difference of method is, in step S2, chip 21a and chip 21b is needed to be spaced apart from each other and be alternately stacked in some stack height,
It is needed in some stack height continuously to dextroposition with continuous stacked multilayer chip 21b, remaining process is all the same, no longer superfluous herein
It states.
Fig. 2 E is please referred to, another embodiment of the present invention provides a kind of chip stack structure, including with upper surface under
Chip 21a, multiple right end of the substrate 20, multiple left ends on surface with chip connection terminal 211, which have, impregnates connection terminal 211
Chip 21b, a plurality of leads 241 and 242, packing colloid and soldered ball 25.The upper surface of the substrate 20 is equipped at least one
Wafer stacking area, the left and right ends in the wafer stacking area are provided with substrate connection terminal 201, and all wafers successively misplace stacking
In the wafer stacking area, and the ends exposed of the upper chip in adjacent two layers chip goes out the chip connecting pin of lower chip
The part of the surface or all surfaces of son, form another serpentine-shaped stack structure.A plurality of leads 242 is for connecting corresponding two
Chip connection terminal 211, a lead 242 connect the substrate connection terminal 201 of bottom chip 21a and left end, a lead
The substrate connection terminal 201 of 242 connection bottom chip 21b and right end, packing colloid cover substrate 20, all wafers and draw
Line, soldered ball are located on the lower surface of substrate 20.
The chip stack structure of the present embodiment also can be realized the effect for reducing packaging height and packaging cost, the present embodiment
Chip stack structure be chip stack structure shown in Fig. 2A and 2B combination, be equivalent to the serpentine-shaped stack knot shown in Fig. 2 B
Serpentine-shaped stack structure shown in one section of Fig. 2A, or any position insertion of the serpentine-shaped stack structure shown in Fig. 2A are inserted into structure
Serpentine-shaped stack structure shown in one section of Fig. 2 B, is equivalent in the serpentine-shaped stack structure shown in Fig. 2A, each section of continuous multilayer chip
21 ' the number of plies is more than or equal to 1, for example, 1,3,4,5 etc., and the number of plies of each section of continuous multilayer chip 21 ' is not exactly the same, equally
, the number of plies of each section of continuous multilayer chip 21 " is more than or equal to 1, for example, 1,3,4,5 etc..The layer of each section of continuous multilayer chip 21 "
Number is not exactly the same.
The forming method of the chip stack structure of the present embodiment can refer to Fig. 3, be formed with the chip stack structure of Fig. 2A
The difference of method is, in step S2, chip 21a and chip 21b is needed to be spaced apart from each other and be alternately stacked in some stack height,
Need in some stack height continuously to dextroposition with continuous stacked multilayer chip 21b, needed in some stack height continuously to
Left dislocation is with continuous stacked multilayer chip 21a, remaining process is all the same, and details are not described herein.
Fig. 2 F is please referred to, further embodiment of this invention provides a kind of chip stack structure, including with upper surface and following table
Chip 21a or multiple right end of the substrate 20, multiple left ends in face with chip connection terminal 211, which have, impregnates connection terminal
211 chip 21b, a plurality of leads 241 and 242, packing colloid and soldered ball 25.The upper surface of the substrate 20 is equipped at least one
A wafer stacking area, the left end in the wafer stacking area or right end are provided with a substrate connection terminal 201, all wafers according to
Secondary dislocation is layered in the wafer stacking area, and the ends exposed of the upper chip in adjacent two layers chip goes out lower chip
The part of the surface or all surfaces of chip connection terminal, form a kind of step structure.A plurality of leads 242 is corresponding for connecting
Two chip connection terminals 211, a lead 242 connect bottom chip and substrate connection terminal 201, and packing colloid covers base
Plate 20, all wafers and lead, soldered ball are located on the lower surface of substrate 20.
The chip stack structure of the present embodiment also can be realized the effect for reducing packaging height and packaging cost, extremely with Fig. 2A
Chip stack structure shown in 2E is compared, and chip only has a seed type, and substrate connection terminal also only one, the chip of chip
Connection terminal 211 and substrate connection terminal 201 are arranged in the same end, as being only stacked chip connection terminal on substrate 20 in Fig. 2 F
211 are arranged in multiple chip 21a of left end, and the left end of upper chip 21a is certain to dextroposition with respect to the left end of lower chip 21a
Size, the left end of all wafers 21a form step structure, and the chip connection terminal 211 of bottom chip 21a passes through lead 241
The chip connection terminal 211 of connecting substrate connection terminal 201, adjacent two layers chip 21a is connected by lead 242.In the present invention
Other embodiments in, multiple chip 21b that right end is arranged in chip connection terminal 211 can also be only stacked on substrate 20,
The right end of upper chip 21b misplaces certain size to the left with respect to the right end of lower chip 21b, and the right end of all wafers 21b is formed
Step structure, the chip connection terminal 211 of bottom chip 21b is by 241 connecting substrate connection terminal 201 of lead, and adjacent two
The chip connection terminal 211 of layer wafer 21b is connected by lead 242.
The forming method of the chip stack structure of the present embodiment can refer to Fig. 3, be formed with the chip stack structure of Fig. 2A
The difference of method is, in step S2, the chip for needing to stack only has mono- seed type of chip 21a or chip 21b, the root when stacking
End where making the chip connection terminal of upper chip according to chip-type with respect to end where the chip connection terminal of lower chip to
It is left or to dextroposition certain size, to expose some or all of surface of the chip connection terminal of lower chip, remaining
Process is all the same, and details are not described herein.
When comparing chip stack structure and chip stack package structure shown in FIG. 1 of the invention, with 16 layer wafers stacking
For, in the chip stack structure of Fig. 1,20 μm of DAF 13, every layer wafer thickness are generallyd use between adjacent two layers chip 11
Be 40 μm, the adhesive between bottom chip 11 and substrate 10 with a thickness of 5 μm, therefore the 16 layers-chip stack structure of Fig. 1
The overall package height for removing packing colloid is 15*20 μm+16*40 μm+5 μm；And it uses in Fig. 2A to Fig. 2 F of the invention and appoints
The second bonding in the 16 layers-chip stack package structure that a kind of chip stack package structure is formed, between adjacent two layers chip
Agent 23 is 5 μm, and the thickness of each layer wafer is still 40 μm, the thickness of the first adhesive between bottom chip and substrate 200
Degree is 5 μm, therefore it is 15*5 μm of+16*40 that 16 layers-chip stack structure of the invention, which removes the overall package height of packing colloid,
μm+5μm；It can be seen that 16 layers-chip stack structure of the invention is high compared to the encapsulation of 16 layers-chip stack package structure in Fig. 1
Degree can reduce 15* (20-5) μm=225 μm, it is clear that chip-packaging structure and its packaging method of the invention can drop significantly
Low packaging height.
It should be noted that mainly with a stacking in a wafer stacking area of upper surface of base plate in the various embodiments described above
The wafer stacking of position illustrates that wire bonding mode therein is mainly that the chip connection terminal of the upper chip of same type is logical
Cross the chip connection terminal of the lower chip of lead connection same type, it is clear that wire bonding mode may be replaced by its other party
Formula, such as: each chip connection terminal positioned at left end directly passes through the substrate connection terminal of lead Yu wafer stacking area left end
Connection, each chip connection terminal positioned at right end directly passes through lead and the substrate connection terminal of wafer stacking area right end connects
It connects, it, can be more according to dislocation direction setting in the respective end in wafer stacking area according to dislocation utmostly under such mode
A substrate connection terminal, with the wire bonding for facilitating opposite bottom chip to misplace between biggish chip and substrate.
In other embodiments of the invention, when in a wafer stacking area be equipped with multiple stacked positions and each stacked position
Between interval it is more sufficient when, wafer stacking can be carried out respectively to each stacked position, also simultaneously can be to all stackings
Position carries out wafer stacking, to improve the coating effect of each layer second adhesive.When the upper surface of substrate is equipped with multiple chips
When stack region, the wafer stacking of preferred all wafers stack region carries out simultaneously, moreover, the function of all wafers stacked and
Size can be not exactly the same.
In conclusion chip stack structure and forming method thereof of the invention, is laminated multiple one end tools by successively misplacing
Have the chip of chip connection terminal, and in lamination process guarantee adjacent two layers chip in upper chip ends exposed go out under
The part of the surface or all surfaces of the chip connection terminal of layer wafer further use between adjacent two layers chip traditional viscous
Mixture replaces DAF, thus reduces packaging height and cost.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to include these modifications and variations.
Claims (16)
1. a kind of chip stack package structure characterized by comprising
The upper surface of substrate with upper and lower surfaces, the substrate is equipped with wafer stacking area, the wafer stacking area
At least one end is provided with substrate connection terminal；
Multiple one end have the chip of chip connection terminal, and successively dislocation is layered in the wafer stacking area, and adjacent two layers
Upper chip in chip exposes the part of the surface or all surfaces of the chip connection terminal of lower chip；
A plurality of leads connects the substrate connection terminal and corresponding chip connection terminal, or the chip of connection two connects
Connecting terminal.
2. chip stack package structure as described in claim 1, which is characterized in that the chip stack package structure further includes
First adhesive and second adhesive, the first adhesive is between the wafer stacking area and undermost chip and incites somebody to action
The wafer stacking area and undermost wafer bonding are fixed, and the second adhesive is between adjacent two layers chip and by institute
Adjacent two layers wafer bonding is stated to fix.
3. chip stack package structure as claimed in claim 2, which is characterized in that the first adhesive and second adhesive
Material it is identical, thickness is respectively less than 10 μm.
4. chip stack package structure as described in claim 1, which is characterized in that the chip stack package structure further includes
Packing colloid and soldered ball, the packing colloid are located on the upper surface of the substrate and cover all wafers and all leads, institute
Soldered ball is stated to be located on the lower surface of the substrate.
5. chip stack package structure as described in claim 1, which is characterized in that the both ends in the wafer stacking area are set respectively
It is equipped with a substrate connection terminal, in all wafers stacked in the wafer stacking area, the crystalline substance of at least two layers adjacent chip
Piece connection terminal is at end where two substrate connection terminals in the projection separation wafer stacking area in the wafer stacking area.
6. the chip stack package structure as described in any one of claims 1 to 5, which is characterized in that the wafer stacking area
In all wafers of upper stacking, there is projection of the chip connection terminal of continuous multilayer chip in the wafer stacking area to be respectively positioned on institute
End where stating the substrate connection terminal in wafer stacking area, one end that the continuous multilayer chip is equipped with chip connection terminal constitute platform
Stage structure.
7. chip stack package structure as claimed in claim 6, which is characterized in that is stacked in the wafer stacking area is all
Projection of the chip connection terminal of chip in the wafer stacking area is respectively positioned on the substrate connection terminal institute in the wafer stacking area
It is holding, one end that all wafers stacked in the wafer stacking area are equipped with chip connection terminal constitutes step structure.
8. the chip stack package structure as described in any one of claims 1 to 5, which is characterized in that the wafer stacking area
Both ends be respectively arranged with a substrate connection terminal, in all wafers stacked in the wafer stacking area, at least one section
Projection of the chip connection terminal of continuous multilayer chip in stack height in the wafer stacking area is respectively positioned on the stack of wafers
End where one substrate connection terminal in folded area, at least connection terminal there are also the continuous multilayer chip in another section of stack height
End where being respectively positioned on another substrate connection terminal in the wafer stacking area in the projection in the wafer stacking area, described in every section
One end that continuous multilayer chip is equipped with chip connection terminal constitutes a step structure.
9. a kind of forming method of chip stack package structure described in any item of the claim 1 to 8, which is characterized in that packet
Include following steps:
The substrate with upper and lower surfaces is provided, the upper surface of the substrate is equipped with wafer stacking area, the wafer stacking
At least one end in area is formed with a substrate connection terminal；
Successively the chip that multiple one end have chip connection terminal, adjacent two layers chip is laminated in dislocation in the wafer stacking area
In upper chip ends exposed go out lower chip chip connection terminal part of the surface or all surfaces；
It is formed by lead key closing process and connects the substrate connection terminal and corresponding chip connection terminal or two chips
The lead of connection terminal.
10. forming method as claimed in claim 9, which is characterized in that successively dislocation stacking is more in the wafer stacking area
A one end have chip connection terminal chip when, by wafer stacking area surface coat state first adhesive with incite somebody to action
The wafer stacking area and undermost wafer bonding are fixed；By on the surface of lower chip coat second adhesive with incite somebody to action
Lower chip and the bonding fixation of adjacent upper chip.
11. forming method as claimed in claim 10, which is characterized in that the material of the first adhesive and second adhesive
Identical, thickness is respectively less than 10 μm.
12. forming method as claimed in claim 9, which is characterized in that further include: after the completing of all leads, shape
At on the upper surface for being located at the substrate and covering the packing colloids of all wafers and all leads, and under the substrate
Surface forms entire chip stack package structure plus soldered ball.
13. the forming method as described in any one of claim 9 to 12, which is characterized in that the both ends in the wafer stacking area
It is respectively arranged with a substrate connection terminal, successively multiple one end are laminated with chip connection in dislocation in the wafer stacking area
When the chip of terminal, the projection of the chip connection terminal of at least two layers adjacent chip in the wafer stacking area is lived apart the crystalline substance
End where two substrate connection terminals of piece stack region.
14. the forming method as described in any one of claim 9 to 12, which is characterized in that in the wafer stacking Qu Shangyi
When secondary dislocation is laminated multiple one end and has the chip of chip connection terminal, in all wafers that are stacked in the wafer stacking area,
There is projection of the chip connection terminal of continuous multilayer chip in the wafer stacking area to be respectively positioned on the substrate in the wafer stacking area
End where connection terminal, one end that the continuous multilayer chip is equipped with chip connection terminal constitute step structure.
15. forming method as claimed in claim 14, which is characterized in that successively dislocation stacking is more in the wafer stacking area
When a one end has the chip of chip connection terminal, the chip connection terminal of all wafers stacked in the wafer stacking area exists
The projection in the wafer stacking area is respectively positioned on end where the substrate connection terminal in the wafer stacking area, in the wafer stacking area
One end that all wafers of stacking are equipped with chip connection terminal constitutes step structure.
16. the forming method as described in any one of claim 9 to 12, which is characterized in that the both ends in the wafer stacking area
It is respectively arranged with a substrate connection terminal, successively multiple one end are laminated with chip connection in dislocation in the wafer stacking area
When the chip of terminal, in all wafers that are stacked in the wafer stacking area, the continuous multilayer at least one section of stack height
Projection of the chip connection terminal of chip in the wafer stacking area is respectively positioned on a substrate connecting pin in the wafer stacking area
End where sub, at least throwing there are also the connection terminal of the continuous multilayer chip in another section of stack height in the wafer stacking area
Shadow is respectively positioned on end where another substrate connection terminal in the wafer stacking area, and every section of continuous multilayer chip is equipped with chip
One end of connection terminal constitutes a step structure.
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| CN201711085239.3A CN109755182A (en) | 2017-11-07 | 2017-11-07 | Chip stack package structure and forming method thereof |
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| CN201711085239.3A CN109755182A (en) | 2017-11-07 | 2017-11-07 | Chip stack package structure and forming method thereof |
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| WO2024082536A1 (en) * | 2022-10-21 | 2024-04-25 | 长鑫存储技术有限公司 | Packaging structure |
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Application publication date: 20190514 |