CN206353534U - The diode of anti-ESD a kind of and the CMOS protection using integrated circuit circuits comprising it - Google Patents
The diode of anti-ESD a kind of and the CMOS protection using integrated circuit circuits comprising it Download PDFInfo
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- CN206353534U CN206353534U CN201621466189.4U CN201621466189U CN206353534U CN 206353534 U CN206353534 U CN 206353534U CN 201621466189 U CN201621466189 U CN 201621466189U CN 206353534 U CN206353534 U CN 206353534U
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Abstract
The utility model discloses a kind of diode of anti-electrostatic-discharge, including：The Semiconductor substrate of first conduction type；The well region of the second conduction type formed on substrate；The doped region of the first conduction type formed on well region；In the case where the area of doped region is certain, being shaped as of doped region make doped region have high girth/area than shape.In the case of identical diode area, doped region has high girth/area ratio, improves diode current capacity, strengthens diode electrostatic discharge ability, and with small input capacitance, solves the device damage caused by static discharge；The invention also discloses a kind of protection circuit of the CMOS integrated circuits containing anti-electrostatic-discharge diode, input end capacitor is reduced, CMOS integrated circuit anti-static-discharge capabilities are improved.
Description
Technical field
The utility model is related to semiconductor microelectronic technology field.More particularly, to a kind of the anti-of CMOS integrated circuits
ESD diode and the protection circuit comprising it.
Background technology
The actionless electric charge of body surface is referred to as electrostatic, and electrostatic potential typically refers to the current potential between electrical body and the earth
Difference, using the earth as zero potential, the current potential of electrostatic charging body, which obviously has, just negative, and current potential is just band when electrical body is positively charged
Current potential is negative when electric body is negatively charged, and the electrostatic potential generally said refers to its absolute value.Static electrification on object, although institute's carried charge
Seldom, but current potential is very high, several kilovolts arrive volts up to ten thousand.So high voltage can produce Transient Currents in static discharge,
ESD manikins electrostatic potential and transient current relation are as shown in Figure 1.When powered object is contacted with conductive path, these
Electric charge can be lost by conductive path and be put, and damage recurring structure at the high resistant of path, here it is static discharge (Electro-
Static Discharge, ESD) damage.
Static discharge causes the failure mode of device to have two kinds：Catastrophic failure and parameter degradation failure.Catastrophic failure：Through quiet
Big mutation occurs for the one or more parameters of device after discharge of electricity, makes component failure, such as partly leads device PN junction partial breakdown, protects
The melting damage of diode edge, grid break-through etc.；Parameter degradation fails：When electrostatic body electrostatic energy deficiency has made high resistance area such as PN junction
Or gate oxide formation melt channel causes local damage, device parameters is degenerated, to being caused a hidden trouble during device use.
Static discharge can cause damage to device, and statistics shows in MOS device ineffective part that 20-50% is put by electrostatic
Electricity is caused.CMOS integrated circuit input ends are the common connecting points of the grid lead of two MOS transistors.Each MOS transistor
Grid and raceway groove interval layer of silicon dioxide layer, the critical breakdown electric field intensity of silicon dioxide layer is (7-10) × 106v/cm。
Standard radiation hardening cmos circuit gate oxide thickness is 50nm or so.Breakdown voltage is 35V-50V.Equivalent inpnt resistance reaches
To 1010Ω or so.Input capacitance is 5pf or so.If manufacturing process is defective, breakdown voltage will also be reduced, for this
The input of high input impedance, as long as the extraneous charge inducing for having a very little, all may in input, rapid stored charge and set up
At a relatively high voltage.If the magnitude of voltage set up bears breakdown voltage value beyond silica, may occur medium
Puncture, cause circuit by permanent damage.
Static discharge (ESD) ineffective part analysis is found：Most of is all protection diode damage over the ground, damages damage
Mechanism is that diode marginal portion excessively stream is burnt.It is integrated with the raising of metal-oxide semiconductor (MOS) (MOS) device integration
Circuit chip is faced with serious static discharge (ESD) and threatened, and the esd protection circuit used at present is due to edge-crowding effect of current
Etc. reason, the problems such as generally existing limited antistatic effect, occupancy larger chip area.
Accordingly, it would be desirable to which a kind of carry out the diode of anti-electrostatic discharging (ESD) to CMOS integrated circuits and include the diode
Protection circuit.
The content of the invention
A purpose of the present utility model is to provide a kind of diode of anti-electrostatic-discharge.
To reach above-mentioned purpose, the utility model uses following technical proposals：
A kind of diode of anti-electrostatic-discharge, including：
The Semiconductor substrate of first conduction type；
The well region of the second conduction type formed on substrate；
The doped region of the first conduction type formed on well region；
In the case where the area of doped region is certain, being shaped as of doped region make doped region have high girth/area than
Shape；The Zhou Changwei 4 of the square doped region of unit area is defined, the girth that doped region has/area ratio is 4, and girth/area is than big
It is high girth/area ratio in 4；
Wherein the first conduction type is opposite with the second conduction type.
Preferably, in well region formation fairlead, it is used as the positive pole of diode；In doped region formation fairlead, two poles are used as
The negative pole of pipe；Substrate formation fairlead, for positive source VDDIt is connected, the PN junction of substrate and well region formation is in reversely partially
Pressure condition, buffer action is played to diode；Fairlead size is 8 μm.
Preferably, doped region is shaped as strip structure.
Preferably, doped region is shaped as finger-like structure.
It is further preferred that doped region is shaped as finger-like structure, finger-like structure include a horizontal strip structure and with horizontal stroke
To strip structure one and positioned at least two vertical strip structures of horizontal strip structure homonymy/heteropleural.
Preferably, strip structure width is 12 μm.
Preferably, the length of bar shaped/finger-like structure is 5~12 times of width；Adulterating, section length is oversize to cause pressure drop to increase
Greatly, the distribution of electric current is influenceed, design strip structure length is length when electric current drops to 1/e.
According to Semiconductive Theory, diode forward pressure drop reduces KT/q (0.026V), and electric current declines 1/e times, and pressure drop is got over
Greatly, electric current is smaller.
Wherein, K is Boltzmann constant 8.62 × 10-5Electron volts；T is absolute temperature 300K；Q is electron charge.
Preferably, well region is doped to boron, and surface concentration is 8 × 1015/cm3~1 × 1016/cm3；Doped region is doped to phosphorus,
Surface concentration is more than 1 × 1020/cm3。
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second leads
Electric type is p-type.
Another purpose of the present utility model is to provide a kind of protection electricity including the anti-ESD diode of CMOS integrated circuits
Road.
A kind of protection circuit of the anti-electrostatic-discharge of CMOS integrated circuits, wherein：
The input of CMOS integrated circuits is connected with input protection resistor as protection circuit input；
The positive pole of the negative pole of first diode and the second diode is with protective resistance close to one end of protection circuit input
It is connected；The negative pole of 3rd diode and the positive pole of the 4th diode and one end phase of the protective resistance away from protection circuit input
Even；The negative pole of 5th diode and the positive pole of the 6th diode are connected with protection circuit output end；
Firstth, the plus earth of the 3rd and the 5th diode；Secondth, the negative pole and positive source of the 4th and the 6th diode
VDDIt is connected；
First and second diodes are the diode of anti-electrostatic-discharge.
The beneficial effects of the utility model are as follows：
A kind of diode of anti-electrostatic-discharge in the utility model, in the case of identical diode area, increase
Diode girth, makes the doped region have high girth/area ratio, improves diode current capacity, and enhancing diode electrostatic is put
Electric energy power, and with small input capacitance, solve the device damage caused by static discharge (ESD)；One kind is put containing antistatic
The protection circuit of the CMOS integrated circuits of electric diode, reduces input end capacitor, improves that CMOS integrated circuits are antistatic to be put
Electric (ESD) ability.
Brief description of the drawings
Embodiment of the present utility model is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 shows ESD manikins electrostatic potential and transient current relation.
Fig. 2 shows protection diode plan in the prior art.
Fig. 3 shows protection diode profile in the prior art.
Fig. 4 shows the diode facet figure of anti-electrostatic-discharge in example.
Fig. 5 shows the diode facet figure of anti-electrostatic-discharge in example.
Fig. 6 shows the protection circuit figure of the CMOS integrated circuits containing anti-electrostatic-discharge diode.
Embodiment
In order to illustrate more clearly of the utility model, the utility model is done into one with reference to preferred embodiments and drawings
The explanation of step.Similar part is indicated with identical reference in accompanying drawing.It will be appreciated by those skilled in the art that below
Specifically described content is illustrative and be not restrictive, and protection domain of the present utility model should not be limited with this.
In order to overcome the deficiencies in the prior art, there is provided a kind of raising CMOS integrated circuits anti-electrostatic discharging (ESD) ability
Diode structure, solves the device damage caused by static discharge (ESD), reduces input end capacitor, improves CMOS integrated circuits
Anti-electrostatic discharging (ESD) ability, the utility model proposes a kind of diode of the anti-electrostatic-discharge of CMOS integrated circuits, including：
The Semiconductor substrate of first conduction type；The well region of the second conduction type formed on substrate；First formed on well region
The doped region of conduction type；In the case where the area of doped region is certain, being shaped as of doped region make doped region have high girth/
Area than shape；The Zhou Changwei 4 of the square doped region of unit area is defined, the girth that doped region has/area ratio is 4, girth/
It is high girth/area ratio that area ratio, which is more than 4,；Wherein the first conduction type is opposite with the second conduction type.
In the utility model, in well region formation fairlead, the positive pole of diode is used as；In doped region formation fairlead, make
For the negative pole of diode；Substrate formation fairlead, for positive source VDDIt is connected, is in the PN junction that substrate is formed with well region
Reverse bias condition, buffer action is played to diode；Fairlead size is 8 μm.
In the utility model, doped region is shaped as strip structure or is finger-like structure.Wherein, finger-type includes a Cross slat
Shape structure and with horizontal bar shaped structural integrity and positioned at least two vertical bar shaped knots of horizontal strip structure homonymy/heteropleural
Structure.According to Semiconductive Theory, diode forward pressure drop reduces KT/q (0.026V), and electric current declines 1/e times, and pressure drop is bigger, electricity
Stream is smaller.Wherein, K is Boltzmann constant 8.62 × 10-5Electron volts；T is absolute temperature 300K；Q is electron charge.This practicality
In new, strip structure width is 12 μm.The length of bar shaped/finger-like structure is 5~12 times of width；Section length of adulterating is oversize
Pressure drop can be caused to increase, influence the distribution of electric current, design strip structure length is length when electric current drops to 1/e.
In the utility model, well region is doped to boron, and surface concentration is 8 × 1015/cm3~1 × 1016/cm3；Doped region adulterates
For phosphorus, surface concentration is more than 1 × 1020/cm3.First conduction type is p-type, and the second conduction type is N-type；Or first conductive-type
Type is N-type, and the second conduction type is p-type.
Another purpose of the present utility model is to provide a kind of protection electricity including the anti-ESD diode of CMOS integrated circuits
Road.A kind of protection circuit of the anti-electrostatic-discharge of CMOS integrated circuits, wherein：The input of CMOS integrated circuits is protected with input
Shield resistance, which is connected, is used as protection circuit input；The positive pole of the negative pole of first diode and the second diode and protective resistance are close
One end of protection circuit input is connected；The negative pole of 3rd diode and the positive pole of the 4th diode are with protective resistance away from protection
One end of circuit input end is connected；The negative pole of 5th diode and the positive pole of the 6th diode are connected with protection circuit output end；
Firstth, the plus earth of the 3rd and the 5th diode；Secondth, the negative pole and positive source V of the 4th and the 6th diodeDDIt is connected；
First and second diodes are the diode of anti-electrostatic-discharge.
Illustrated with reference to an example.In example, doped region is shaped as finger-like structure, and the quantity preferably referred to is
3；First conduction type is N-type, and the second conduction type is p-type.
As shown in Figure 2 and Figure 3, during diode of the prior art is device manufacturing processes, while formed, it is not necessary to increase
Process skill.The diode includes：The Semiconductor substrate N of first conduction type-Area, the second conduction type for being formed on substrate
Well region P-Area and the doped region N of the first conduction type formed on well region+Area.N-Area is device substrate, forms diode
Isolation structure, P-Area is device p-well, N+Area forms N simultaneously with NMOS source-drain areas+P-Form protection diode.The structure is equivalent
In NPN transistor, the just extremely P of diode-Area.Equivalent to transistor base.Diode current flows to surface by base
Electrode.Because base width is very narrow, only several microns, lateral resistance is very big, electric current by when form voltage drop, electricity
Stream is bigger, and pressure drop is bigger, due to voltage drop reason, causes diode current marginal portion bigger than center section, more by middle electricity
Stream is smaller, when voltage drop is more than 0.7 volt, electric current vanishing, and this phenomenon is edge-crowding effect of current, diode center section,
No current by when form invalid.
As shown in Figure 4, Figure 5, a kind of diode of anti-electrostatic-discharge, the diode includes：First conduction type is partly led
Body substrate N-Area, the well region P of the second conduction type formed on substrate-Area and the first conduction type for being formed on well region
Doped region N+Area.In the case where the area of doped region is certain, being shaped as of doped region makes doped region have high girth/area ratio
Shape.In this example, doped region is shaped as finger-like structure, and the quantity referred to is 3, and finger-like structure width is 12 μm.Finger-type knot
The length of structure is 5~12 times of width.N-Area is device substrate, forms the isolation structure of diode, P-Area is device p-well, N+
Area is formed simultaneously with NMOS source-drain areas, N+P-Form protection diode.The general-purpose diode sense of current be it is vertical, due to this two
The P of pole pipe-Region electrode is drawn by surface, therefore electric current is by N+Area is to P-By long narrow horizontal P behind area-Qu Houzai is arrived
Surface electrode.Horizontal P- areas are very narrow, and only several microns, resistance is very big, and pressure drop can be formed when electric current passes through.
Static discharge (ESD) characteristic is Transient Currents, and, intermediate current is small or even does not have close to PN junction edge current greatly
There is electric current process, this phenomenon is edge-crowding effect of current.Conventional square protection diode center section no current, is invalid face
Product, edge current is concentrated, once beyond the limit of current density, diode will be damaged.Diode junction of the present utility model
Structure N+Area is rack type structure, and this structure can substantially eliminate edge-crowding effect of current, for this structure two of same diode area
Pole pipe girth doubles the above, and current capacity is also accordingly increased.
Diode of the present utility model is manufactured simultaneously in CMOS ic processings, it is not necessary to increased
Technique.
In this example, N-type (100) silicon single crystal flake, electricalresistivityρ=2~4 Ω/cm.In well region formation fairlead, two are used as
The positive pole of pole pipe；In doped region formation fairlead, the negative pole of diode is used as；Substrate formation fairlead, is used for and positive source
VDDIt is connected, substrate and the PN junction of well region formation is in reverse bias condition, buffer action is played to diode；Due to CMOS electricity
Road design size is relatively wide, and fairlead size is 8 μm.P-Area is formed simultaneously with cmos circuit manufacturing process p-well region, is doped to
Boron, surface concentration is 8 × 1015/cm3~1 × 1016/cm3；N+Area and the NMOS source-drain areas of CMOS integrated circuits are formed simultaneously, are mixed
Miscellaneous area is doped to phosphorus, and surface concentration is more than 1 × 1020/cm3.First conduction type is P types, and the second conduction type is N-type；Or the
One conduction type is N-type, and the second conduction type is p-type.
It should be noted that the doped region of finger-type can not it is oversize, can not be too thin.If because too long of as doped region
Words, will produce pressure drop in the longitudinal direction of doped region, cause the Injection Current of finger-like structure longitudinal direction uneven；If too carefully,
Pressure drop can be laterally produced in the finger-like structure of doped region, cause horizontal Injection Current uneven.In other words, if finger-like structure
If oversize or too thin, whole doped region all can not be effectively utilized, it is difficult to increase total electric current.Certainly, the injection of doped region
Current density can not be excessive, i.e., otherwise the electric current of doped region unit perimeter just makes diode no more than certain capacity
Overall performance declines.
Note that the conduction type of each layer in above-mentioned example can uniformly be changed into opposite type, can also realize this
The anti-electrostatic-discharge function of utility model.
It should be noted that N+Represent N-type conduction type heavy doping, N-Represent N-type conduction type to be lightly doped, P-Represent p-type
Conduction type is lightly doped.Here, heavy doping and to be lightly doped be relative concept, represents that the doping concentration of heavy doping is more than and is lightly doped
Doping concentration, and the not restriction to specific doping concentration scope.
Static discharge (ESD) protects the major function of network：It is that there is provided one in the case of each pin static discharge
The individual high current network limited with suitable voltage.Under the limitation of suitable voltage, device is in static discharge (ESD) time-domain
In voltage to be limited within pulse safety operation area.So static discharge (ESD) protection network should not only provide electrostatic and put
Electric current path, and to ensure to limit this voltage, less than each pin, it is allowed to bare maximum.
As shown in fig. 6, in order to realize above-mentioned functions, the utility model also proposes that a kind of antistatic of CMOS integrated circuits is put
The protection circuit of electricity, wherein：The input of CMOS integrated circuits is connected as protection circuit input with input protection resistor R；
First diode D1 negative pole and the second diode D2 positive pole are connected with protective resistance close to one end of protection circuit input；
3rd diode D3 negative pole and the 4th diode D4 positive pole are connected with the one end of protective resistance away from protection circuit input；
5th diode D5 negative pole and the 6th diode D6 positive pole are connected with protection circuit output end；Firstth, the the 3rd and the 5th 2
The plus earth of pole pipe (D1, D3, D5)；Secondth, the negative pole and positive source V of the 4th and the 6th diode (D2, D4, D6)DDPhase
Even.
Static discharge (ESD) ineffective part analysis is found：Most of is all that first or second protection diode are damaged
Wound, it is that diode marginal portion excessively stream is burnt to damage micromechanism of damage.In the utility model, the first and second diodes (D1, D2)
For the diode of anti-electrostatic-discharge.
Obviously, above-described embodiment of the present utility model is only intended to clearly illustrate the utility model example, and
It is not the restriction to embodiment of the present utility model, for those of ordinary skill in the field, in described above
On the basis of can also make other changes in different forms, all embodiments can not be exhaustive here,
It is every to belong to obvious changes or variations that the technical solution of the utility model extends out still in of the present utility model
The row of protection domain.
Claims (9)
1. a kind of diode of anti-electrostatic-discharge, it is characterised in that including：
The Semiconductor substrate of first conduction type；
The well region of the second conduction type formed over the substrate；
The doped region of the first conduction type formed on the well region；
In the case where the area of the doped region is certain, being shaped as of the doped region make the doped region have high girth/
Area than shape；
Wherein the first conduction type is opposite with the second conduction type.
2. diode according to claim 1, it is characterised in that in well region formation fairlead, be used as two pole
The positive pole of pipe；In doped region formation fairlead, the negative pole of the diode is used as；The substrate formation fairlead, is used for
With positive source VDDIt is connected.
3. diode according to claim 1, it is characterised in that the doped region is shaped as strip structure.
4. diode according to claim 1, it is characterised in that the doped region is shaped as finger-like structure.
5. the diode according to claim 3 or 4, it is characterised in that the doped region shape width is 12 μm.
6. the diode according to claim 3 or 4, it is characterised in that the length of the bar shaped/finger-like structure is width
5 ~ 12 times.
7. diode according to claim 1, it is characterised in that the well region is doped to boron, surface concentration is 8 × 1015/
cm3~1×1016/cm3；The doped region is doped to phosphorus, and surface concentration is more than 1 × 1020/cm3。
8. diode according to claim 1, it is characterised in that
First conduction type is p-type, and the second conduction type is N-type；Or
First conduction type is N-type, and the second conduction type is p-type。
9. a kind of protection circuit of the anti-electrostatic-discharge of CMOS integrated circuits, it is characterised in that
The input of CMOS integrated circuits is connected with input protection resistor as protection circuit input；
The positive pole of the negative pole of first diode and the second diode is with the protective resistance close to one end of protection circuit input
It is connected；The negative pole of 3rd diode and the positive pole of the 4th diode and the one end of the protective resistance away from protection circuit input
It is connected；The negative pole of 5th diode and the positive pole of the 6th diode are connected with the protection circuit output end；
The plus earth of the diode of described first, the 3rd and the 5th；The negative pole and power supply of the diode of described second, the 4th and the 6th
Positive pole VDDIt is connected；
First and second diode is the diode any one of claim 1-8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201621466189.4U CN206353534U (en) | 2016-12-29 | 2016-12-29 | The diode of anti-ESD a kind of and the CMOS protection using integrated circuit circuits comprising it |
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| CN201621466189.4U CN206353534U (en) | 2016-12-29 | 2016-12-29 | The diode of anti-ESD a kind of and the CMOS protection using integrated circuit circuits comprising it |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653747A (en) * | 2016-12-29 | 2017-05-10 | 北京宇翔电子有限公司 | Anti-ESD diode and protection circuit of CMOS integrated circuit comprising same |
| CN110888517A (en) * | 2019-10-08 | 2020-03-17 | 深圳市稳先微电子有限公司 | System on chip |
-
2016
- 2016-12-29 CN CN201621466189.4U patent/CN206353534U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653747A (en) * | 2016-12-29 | 2017-05-10 | 北京宇翔电子有限公司 | Anti-ESD diode and protection circuit of CMOS integrated circuit comprising same |
| CN110888517A (en) * | 2019-10-08 | 2020-03-17 | 深圳市稳先微电子有限公司 | System on chip |
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