CN106653747A - Anti-ESD diode and protection circuit of CMOS integrated circuit comprising same - Google Patents
Anti-ESD diode and protection circuit of CMOS integrated circuit comprising same Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 230000001681 protective effect Effects 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 208000033999 Device damage Diseases 0.000 abstract description 3
- 230000002829 reductive effect Effects 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 238000005421 electrostatic potential Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 206010059875 Device ineffective Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000007786 electrostatic charging Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005510 radiation hardening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Semiconductor Integrated Circuits (AREA)
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Abstract
The invention discloses am an anti-ESD (Electrostatic Discharge) diode. The anti-ESD diode comprises a semiconductor substrate of a first conductive type; a well region of a second conductive type formed on the substrate; and a doping region of a first conductive type formed on the well region. The doping region has the shape with a high perimeter/area ratio under the condition of a certain area of the doping region. The doping region has high perimeter/area ratio under the condition of the same diode area, so that the diode current capacity is improved, the diode electrostatic discharge capacity is enhanced, a small input capacitance is provided, and device damage caused by electrostatic discharge is solved. The invention also discloses a protection circuit of a CMOS integrated circuit having the anti-ESD diode. The input-end capacitance is reduced, and the electrostatic discharge capacity of the CMOS integrated circuit is improved.
Description
Technical field
The present invention relates to semiconductor microelectronic technology field.More particularly, to a kind of anti-ESD's of CMOS integrated circuits
Diode and the protection circuit comprising it.
Background technology
The actionless electric charge of body surface is referred to as electrostatic, and electrostatic potential typically refers to the current potential between electrical body and the earth
Difference, will be greatly as zero potential, and the current potential of electrostatic charging body obviously has and just having negative, and current potential is just band when electrical body is positively charged
Current potential is negative when electric body is negatively charged, and the electrostatic potential generally said refers to its absolute value.Static electrification on object, although institute's carried charge
Seldom, but current potential is very high, there are several kilovolts to volts up to ten thousand.So high voltage can produce Transient Currents in static discharge,
ESD manikins electrostatic potential is as shown in Figure 1 with transient current relation.When powered object is contacted with conductive path, these
Electric charge can be lost by conductive path and be put, and damage recurring structure at the high resistant of path, here it is static discharge (Electro-
Static Discharge, ESD) damage.
Static discharge causes the failure mode of device to have two kinds：Catastrophic failure and parameter degradation fail.Catastrophic failure：Jing is quiet
After discharge of electricity there is big mutation in one or more parameters of device, make component failure, such as partly lead device PN junction partial breakdown, protect
The melting of diode edge is damaged, grid break-through etc.；Parameter degradation fails：When electrostatic body electrostatic energy deficiency has made high resistance area such as PN junction
Or gate oxide forms melt channel and causes local damage, makes device parameters degenerate, to causing a hidden trouble during device use.
Static discharge can cause to damage to device, and statistics shows in MOS device ineffective part that 20-50% is put by electrostatic
Electricity is caused.CMOS integrated circuit input ends are the common connecting points of the grid lead of two MOS transistors.Each MOS transistor
Grid and raceway groove be spaced layer of silicon dioxide layer, the critical breakdown electric field intensity of silicon dioxide layer is (7-10) × 106v/cm。
Standard radiation hardening cmos circuit gate oxide thickness is 50nm or so.Breakdown voltage is 35V-50V.Equivalent inpnt resistance reaches
To 1010Ω or so.Input capacitance is 5pf or so.If manufacturing process is defective, breakdown voltage will also be reduced, for this
The input of high input impedance, as long as there is the charge inducing of very little in the external world, all may in input, rapid stored charge and set up
At a relatively high voltage.If the magnitude of voltage set up bears breakdown voltage value beyond silica, medium may occur
Puncture, cause circuit to suffer permanent damage.
Static discharge (ESD) ineffective part analysis is found：Major part is all that over the ground protection diode is damaged, and damages and damages
Mechanism is burnt for diode marginal portion excessively stream.With the raising of metal-oxide semiconductor (MOS) (MOS) device integration, integrated electricity
Road chip is faced with serious static discharge (ESD) and threatens, and the esd protection circuit for adopting at present is due to edge-crowding effect of current etc.
Reason, generally existing antistatic effect it is limited, take larger chip area the problems such as.
Accordingly, it would be desirable to a kind of diode that anti-electrostatic discharging (ESD) is carried out to CMOS integrated circuits and comprising the diode
Protection circuit.
The content of the invention
It is an object of the present invention to provide a kind of diode of anti-electrostatic-discharge.
To reach above-mentioned purpose, the present invention adopts following technical proposals：
A kind of diode of anti-electrostatic-discharge, including：
The Semiconductor substrate of the first conduction type；
The well region of the second conduction type formed on substrate；
The doped region of the first conduction type formed on well region；
In the case where the area of doped region is certain, being shaped as of doped region makes doped region have high girth/area ratio
Shape；The Zhou Changwei 4 of the square doped region of unit area is defined, the girth that doped region has/area ratio is 4, and girth/area is than big
It is high girth/area ratio in 4；
Wherein the first conduction type is contrary with the second conduction type.
Preferably, fairlead is formed in well region, as the positive pole of diode；Fairlead is formed in doped region, as two poles
The negative pole of pipe；Substrate formed fairlead, for positive source VDDIt is connected, makes the PN junction that substrate is formed with well region in reversely partially
Pressure condition, to diode buffer action is played；Fairlead size is 8 μm.
Preferably, doped region is shaped as strip structure.
Preferably, doped region is shaped as finger-like structure.
It is further preferred that doped region is shaped as finger-like structure, finger-like structure include a horizontal strip structure and with horizontal stroke
To strip structure one and positioned at least two vertical strip structures of horizontal strip structure homonymy/heteropleural..
Preferably, strip structure width is 12 μm.
Preferably, the length of bar shaped/finger-like structure is 5～12 times of width；Adulterating, section length is oversize to cause pressure drop to increase
Greatly, affect the distribution of electric current, design strip structure length that length during 1/e is dropped to for electric current.
According to Semiconductive Theory, diode forward pressure drop reduces KT/q (0.026V), and electric current declines 1/e times, and pressure drop is got over
Greatly, electric current is less.
Wherein, K is Boltzmann constant 8.62 × 10-5Electron volts；T is absolute temperature 300K；Q is electron charge.
Preferably, well region is doped to boron, and surface concentration is 8 × 1015/cm3～1 × 1016/cm3；Doped region is doped to phosphorus,
Surface concentration is more than 1 × 1020/cm3。
Preferably, the first conduction type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, second leads
Electric type is p-type.
Further object is that providing a kind of protection circuit including the anti-ESD diode of CMOS integrated circuits.
A kind of protection circuit of the anti-electrostatic-discharge of CMOS integrated circuits, wherein：
The input of CMOS integrated circuits is connected as protection circuit input with input protection resistor；
The positive pole of the negative pole of the first diode and the second diode is with protective resistance near one end of protection circuit input
It is connected；One end phase of the negative pole of the 3rd diode and the positive pole of the 4th diode and protective resistance away from protection circuit input
Even；The negative pole of the 5th diode and the positive pole of the 6th diode are connected with protection circuit output end；
Firstth, the plus earth of the 3rd and the 5th diode；The negative pole and positive source of the second, the 4th and the 6th diode
VDDIt is connected；
First and second diodes are the diode of anti-electrostatic-discharge.
Beneficial effects of the present invention are as follows：
A kind of diode of the anti-electrostatic-discharge in the present invention, in the case of identical diode area, increases two
Pole pipe girth, makes doped region have high girth/area ratio, improves diode current capacity, strengthens diode electrostatic discharge energy
Power, and with little input capacitance, solve the device damage caused because of static discharge (ESD)；One kind contains anti-electrostatic-discharge two
The protection circuit of the CMOS integrated circuits of pole pipe, reduces input end capacitor, improves CMOS integrated circuit anti-electrostatic dischargings
(ESD) ability.
Description of the drawings
The specific embodiment of the present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 illustrates ESD manikins electrostatic potential and transient current relation.
Fig. 2 illustrates protection diode plan in prior art.
Fig. 3 illustrates protection diode profile in prior art.
Fig. 4 illustrates the diode facet figure of anti-electrostatic-discharge in example.
Fig. 5 illustrates the diode facet figure of anti-electrostatic-discharge in example.
Fig. 6 illustrates the protection circuit figure of the CMOS integrated circuits containing anti-electrostatic-discharge diode.
Specific embodiment
In order to be illustrated more clearly that the present invention, the present invention is done further with reference to preferred embodiments and drawings
It is bright.Similar part is indicated with identical reference in accompanying drawing.It will be appreciated by those skilled in the art that below institute is concrete
The content of description is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
In order to overcome the deficiencies in the prior art, there is provided one kind improves CMOS integrated circuit anti-electrostatic discharging (ESD) abilities
Diode structure, solves the device damage caused because of static discharge (ESD), reduces input end capacitor, improves CMOS integrated circuits
Anti-electrostatic discharging (ESD) ability, the present invention proposes a kind of diode of the anti-electrostatic-discharge of CMOS integrated circuits, including：First
The Semiconductor substrate of conduction type；The well region of the second conduction type formed on substrate；First formed on well region is conductive
The doped region of type；In the case where the area of doped region is certain, being shaped as of doped region makes doped region have high girth/area
The shape of ratio；The Zhou Changwei 4 of the square doped region of unit area is defined, the girth that doped region has/area ratio is 4, girth/area
Than being high girth/area ratio more than 4；Wherein the first conduction type is contrary with the second conduction type.
In the present invention, fairlead is formed in well region, as the positive pole of diode；Fairlead is formed in doped region, as two
The negative pole of pole pipe；Substrate formed fairlead, for positive source VDDIt is connected, makes the PN junction that substrate is formed with well region in reverse
Bias state, to diode buffer action is played；Fairlead size is 8 μm.
In the present invention, doped region is shaped as strip structure or for finger-like structure.Wherein, finger-type includes a horizontal bar shaped knot
Structure and with horizontal bar shaped structural integrity and positioned at least two vertical strip structures of horizontal strip structure homonymy/heteropleural.Root
According to Semiconductive Theory, diode forward pressure drop reduces KT/q (0.026V), and electric current declines 1/e times, and pressure drop is bigger, and electric current is got over
It is little.Wherein, K is Boltzmann constant 8.62 × 10-5Electron volts；T is absolute temperature 300K；Q is electron charge.In the present invention,
Strip structure width is 12 μm.The length of bar shaped/finger-like structure is 5～12 times of width；Doping section length is oversize to cause pressure
Drop increase, affects the distribution of electric current, design strip structure length that length during 1/e is dropped to for electric current.
In the present invention, well region is doped to boron, and surface concentration is 8 × 1015/cm3～1 × 1016/cm3；Doped region is doped to
Phosphorus, surface concentration is more than 1 × 1020/cm3.First conduction type is p-type, and the second conduction type is N-type；Or first conduction type
For N-type, the second conduction type is p-type.
Further object is that providing a kind of protection circuit including the anti-ESD diode of CMOS integrated circuits.
A kind of protection circuit of the anti-electrostatic-discharge of CMOS integrated circuits, wherein：The input of CMOS integrated circuits and input protection electricity
Resistance is connected as protection circuit input；The positive pole of the negative pole of the first diode and the second diode is with protective resistance near protection
One end of circuit input end is connected；The negative pole of the 3rd diode and the positive pole of the 4th diode are with protective resistance away from protection circuit
One end of input is connected；The negative pole of the 5th diode and the positive pole of the 6th diode are connected with protection circuit output end；Firstth,
The plus earth of the 3rd and the 5th diode；The negative pole and positive source V of the second, the 4th and the 6th diodeDDIt is connected；First He
Second diode is the diode of anti-electrostatic-discharge.
Illustrate with reference to an example.In example, doped region is shaped as finger-like structure, and the quantity for preferably referring to is
3；First conduction type is N-type, and the second conduction type is p-type.
As shown in Figure 2 and Figure 3, diode of the prior art is in device manufacturing processes, while formed, it is not necessary to increase
Plus technique.The diode includes：Semiconductor substrate N of the first conduction type-Area, second conduction type formed on substrate
Well region P-Area and the doped region N of the first conduction type formed on well region+Area.N-Area is device substrate, formed diode every
From structure, P-Area be device p-well, N+Area forms N simultaneously with NMOS source-drain areas+P-Form protection diode.The structure is equivalent to
NPN transistor, the just extremely P of diode-Area.Equivalent to transistor base.Diode current flows to the electricity on surface by base
Pole.Because base width is very narrow, only several microns, lateral resistance is very big, and voltage drop, electric current are formed when electric current passes through
Bigger, pressure drop is bigger, due to voltage drop reason, causes diode current marginal portion bigger than mid portion, more by intermediate current
It is less, when voltage drop is more than 0.7 volt, electric current vanishing, this phenomenon is edge-crowding effect of current, diode mid portion, nothing
Invalid is formed when electric current passes through.
As shown in Figure 4, Figure 5, a kind of diode of anti-electrostatic-discharge, the diode includes：First conduction type is partly led
Body substrate N-Area, the well region P of the second conduction type formed on substrate-Area and first conduction type formed on well region
Doped region N+Area.In the case where the area of doped region is certain, being shaped as of doped region makes doped region have high girth/area ratio
Shape.In this example, doped region is shaped as finger-like structure, and the quantity for referring to is 3, and finger-like structure width is 12 μm.Finger-type is tied
The length of structure is 5～12 times of width.N-Area is device substrate, forms the isolation structure of diode, P-Area be device p-well, N+Area
Formed simultaneously with NMOS source-drain areas, N+P-Form protection diode.The general-purpose diode sense of current is vertical, due to two pole
The P of pipe-Region electrode is drawn by surface, therefore electric current is by N+Area is to P-Through long narrow horizontal P behind area-Qu Houzai is to table
Face electrode.Horizontal P- areas are very narrow, and only several microns, resistance is very big, and pressure drop can be formed when electric current is passed through.
Static discharge (ESD) characteristic is Transient Currents, and, intermediate current is little or even does not have near PN junction edge current greatly
There is electric current to pass through, this phenomenon is edge-crowding effect of current.Conventional square protection diode mid portion no current, is invalid face
Product, edge current is concentrated, once beyond the limit of current density, diode will be damaged.The diode structure N of the present invention+
Area is rack type structure, and this structure can substantially eliminate edge-crowding effect of current, for this structure diodes of same diode area
Girth doubles the above, and current capacity is also accordingly increased.
The diode of the present invention is manufactured simultaneously in CMOS ic processings, it is not necessary to increase work
Skill.
In this example, N-type (100) silicon single crystal flake, electricalresistivityρ=2～4 Ω/cm.Fairlead is formed in well region, as two
The positive pole of pole pipe；Fairlead is formed in doped region, as the negative pole of diode；Substrate formed fairlead, for positive source
VDDIt is connected, makes the PN junction that substrate is formed with well region in reverse bias condition, buffer action is played to diode；Due to CMOS it is electric
Road design size is relatively wide, and fairlead size is 8 μm.P-Area is formed simultaneously with cmos circuit manufacturing process p-well region, is doped to
Boron, surface concentration is 8 × 1015/cm3～1 × 1016/cm3；N+Area is formed simultaneously with the NMOS source-drain areas of CMOS integrated circuits, is mixed
Miscellaneous area is doped to phosphorus, and surface concentration is more than 1 × 1020/cm3.First conduction type is p-type, and the second conduction type is N-type；Or the
One conduction type is N-type, and the second conduction type is p-type.
It should be noted that the doped region of finger-type can not it is oversize, can not be too thin.If because too long of as doped region
Words, will produce pressure drop in the longitudinal direction of doped region, cause the Injection Current of finger-like structure longitudinal direction uneven；If too carefully,
Pressure drop can be laterally produced in the finger-like structure of doped region, cause horizontal Injection Current uneven.In other words, if finger-like structure
If oversize or too thin, whole doped region all can not be effectively utilized, it is difficult to increase total electric current.Certainly, the injection of doped region
Current density can not be excessive, i.e., the electric current of doped region unit perimeter otherwise just makes diode no more than certain capacity
Overall performance declines.
Note that the conduction type of each layer in above-mentioned example can unify to be changed into contrary type, it is also possible to realize this
The anti-electrostatic-discharge function of invention.
It should be noted that N+Represent N-type conduction type heavy doping, N-Represent N-type conduction type to be lightly doped, P-Represent p-type
Conduction type is lightly doped.Here, heavy doping and to be lightly doped be relative concept, represents heavily doped doping content more than being lightly doped
Doping content, and not to the restriction of concrete doping content scope.
Static discharge (ESD) protects the major function of network：It is in the case of each pin static discharge, there is provided one
The individual high current network limited with suitable voltage.In the case where suitable voltage is limited, device is in static discharge (ESD) time-domain
In voltage to be limited within pulse safety operation area.So static discharge (ESD) protection network should not only provide electrostatic and put
Electric current path, and to ensure to limit this voltage, less than each pin, it is allowed to bare maximum.
As shown in fig. 6, in order to realize above-mentioned functions, the present invention also proposes a kind of anti-electrostatic-discharge of CMOS integrated circuits
Protection circuit, wherein：The input of CMOS integrated circuits is connected as protection circuit input with input protection resistor R；First
The positive pole of the negative pole of diode D1 and the second diode D2 is connected with protective resistance near one end of protection circuit input；3rd
The one end of the positive pole of the negative pole of diode D3 and the 4th diode D4 with protective resistance away from protection circuit input is connected；5th
The positive pole of the negative pole of diode D5 and the 6th diode D6 is connected with protection circuit output end；Firstth, the 3rd and the 5th diode
The plus earth of (D1, D3, D5)；The negative pole and positive source V of the second, the 4th and the 6th diode (D2, D4, D6)DDIt is connected.
Static discharge (ESD) ineffective part analysis is found：Major part is all that first or second protection diode are damaged
Wound, damages micromechanism of damage and burns for diode marginal portion excessively stream.In the present invention, the first and second diodes (D1, D2) are anti-
The diode of static discharge.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not right
The restriction of embodiments of the present invention, for those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms, all of embodiment cannot be exhaustive here, it is every to belong to this
Obvious change that bright technical scheme is extended out changes row still in protection scope of the present invention.
Claims (9)
1. a kind of diode of anti-electrostatic-discharge, it is characterised in that include：
The Semiconductor substrate of the first conduction type；
The well region of the second conduction type for being formed over the substrate；
The doped region of the first conduction type formed on the well region；
In the case where the area of the doped region is certain, being shaped as of the doped region make the doped region have high girth/
The shape of area ratio；
Wherein the first conduction type is contrary with the second conduction type.
2. diode according to claim 1, it is characterised in that fairlead is formed in the well region, as two pole
The positive pole of pipe；Fairlead is formed in the doped region, as the negative pole of the diode；The substrate forms fairlead, is used for
With positive source VDDIt is connected.
3. diode according to claim 1, it is characterised in that the doped region is shaped as strip structure.
4. diode according to claim 1, it is characterised in that the doped region is shaped as finger-like structure.
5. according to the diode described in claim 3 or 4, it is characterised in that the strip structure width is 12 μm.
6. according to the diode described in claim 3 or 4, it is characterised in that the length of the bar shaped/finger-like structure is width
5～12 times.
7. diode according to claim 1, it is characterised in that the well region is doped to boron, surface concentration is 8 × 1015/
cm3～1 × 1016/cm3；The doped region is doped to phosphorus, and surface concentration is more than 1 × 1020/cm3。
8. diode according to claim 1, it is characterised in that
First conduction type is p-type, and the second conduction type is N-type；Or
First conduction type is N-type, and the second conduction type is p-type.
9. a kind of protection circuit of the anti-electrostatic-discharge of CMOS integrated circuits, it is characterised in that
The input of CMOS integrated circuits is connected as protection circuit input with input protection resistor；
The positive pole of the negative pole of the first diode and the second diode is with the protective resistance near one end of protection circuit input
It is connected；The one end of the negative pole of the 3rd diode and the positive pole of the 4th diode and the protective resistance away from protection circuit input
It is connected；The negative pole of the 5th diode and the positive pole of the 6th diode are connected with the protection circuit output end；
The plus earth of the diode of described first, the 3rd and the 5th；The negative pole and power supply of the diode of described second, the 4th and the 6th
Positive pole VDDIt is connected；
First and second diode is the diode any one of claim 1-9.
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| CN201611246224.6A CN106653747A (en) | 2016-12-29 | 2016-12-29 | Anti-ESD diode and protection circuit of CMOS integrated circuit comprising same |
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| CN201611246224.6A CN106653747A (en) | 2016-12-29 | 2016-12-29 | Anti-ESD diode and protection circuit of CMOS integrated circuit comprising same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Application publication date: 20170510 |