CN206353192U - A kind of safety circuit for chip testing - Google Patents
A kind of safety circuit for chip testing Download PDFInfo
- Publication number
- CN206353192U CN206353192U CN201621306544.1U CN201621306544U CN206353192U CN 206353192 U CN206353192 U CN 206353192U CN 201621306544 U CN201621306544 U CN 201621306544U CN 206353192 U CN206353192 U CN 206353192U
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- circuit
- chip
- fuse
- internal logic
- test pattern
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Abstract
The utility model provides a kind of safety circuit for chip testing.The safety circuit includes internal logic circuit and fuse circuit, and internal logic circuit connects fuse circuit, and fuse circuit is a weak pull-up resistor, and the output end of fuse circuit is connected to the ground wire of outside Wafer Dicing groove；During chip testing, the electric fuse signal of fuse circuit output is sent to internal logic circuit, and internal logic circuit is judged according to the level of electric fuse signal, if electric fuse signal is low level, allows chip to enter test pattern；If electric fuse signal is high level, chip is not allowed to enter test pattern.The utility model carries out chip testing as a result of the fuse circuit of weak pull-up resistor, chip is dispatched from the factory and enters test pattern when testing, chip testing is consigned to before user after finishing, being capable of effective blockade test pattern, data are not changed by mistake in NVM to ensure user, improve secure user data.
Description
Technical field
The utility model is related to smart card chip testing technical field, more particularly to chip testing safety circuit.
Background technology
Intelligent card chip generally has two mode of operations：The test pattern tested for chip volume production, for users to use just
Normal mode of operation.After the completion of chip production, advanced test pattern carries out test of dispatching from the factory to chip, to filter out technical indicator symbol
The chip of conjunction.Chip after test screen, meets under intelligent card chip application environment as long as being placed on, you can enter normal
Mode of operation.The purpose of test pattern is in order to be able to test chip, to screen the core for filtering out failure in intelligent card chip
NVM (Non Volatile Memory, nonvolatile storage) in piece, the most typically chip of failure.In chip testing
Under pattern, various reading and writing are carried out to NVM, wipes and tests, to screen out bad piece.If user enters core using error during the chip
Built-in testing pattern, is just likely to user data in destruction NVM.
Existing entrance chip detecting method, conventional is all that special instruction is sent from chip exterior I/O port, this to do
The advantage of method be realize it is simple, as long as but the shortcoming of the method for testing is to occurring the special instruction on outside port IO, with regard to energy
Into test pattern, so as to modification user data by mistake, it is unfavorable for data safety；Moreover, existing chip testing mode does not have
There is any shielding or protection physically, once the special instruction is compromised, then any third party can send out the special instruction
Chip is given so that chip enters test pattern, so as to cause user data by malicious modification or be not intended to change.
Utility model content
For above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide a kind of for chip testing
Safety circuit so that chip dispatches from the factory can smoothly enter test pattern when testing, and chip testing is consigned to before user after finishing, energy
Enough effective blockade test patterns, to ensure that data are not changed by mistake in user NVM, improve secure user data.
In order to reach above-mentioned technical purpose, the technical solution adopted in the present invention is：
A kind of safety circuit for chip testing, the safety circuit includes internal logic circuit and fuse circuit, interior
Portion's logic circuit connection fuse circuit, fuse circuit is a weak pull-up resistor, and the output end of fuse circuit is connected to outside wafer
The ground wire of scribe line；During chip testing, the electric fuse signal of fuse circuit output is sent to internal logic circuit, internal logic circuit
Judged according to the level of electric fuse signal, if electric fuse signal is low level, allow chip to enter test pattern；Such as
Fruit electric fuse signal is high level, then does not allow chip to enter test pattern.
Preferably, the fuse circuit, when wafer does not carry out reduction scribing, the outside Wafer Dicing groove of its output end connection
Ground wire, its export electric fuse signal be low level；When wafer carries out reduction scribing, its output end and outside Wafer Dicing
The ground wire connection of groove is disconnected, and its electric fuse signal exported is high level.
The utility model carries out chip testing as a result of the fuse circuit of above-mentioned weak pull-up resistor, and what is obtained is beneficial
Effect is so that chip dispatch from the factory test when can enter test pattern, chip testing be consigned to before user after finishing, can effectively sealed
Lock data in test pattern, the NVM to ensure user not changed by mistake, improve secure user data.
The utility model is described further with reference to the accompanying drawings and detailed description.
Brief description of the drawings
Fig. 1 is safety circuit structure chart of the present utility model.
Fig. 2 is the safety circuit structure chart of the utility model specific implementation.
Embodiment
It is safety circuit structure chart of the present utility model referring to Fig. 1.The safety circuit general diagram is intelligent card chip；It is molten
Silk circuit is common fuse (fuse) circuit implementations, and wherein R1 is weak pull-up resistor；Internal logic circuit is referred to
Other logic circuits in intelligent card chip in addition to fuse circuit；RST, CLK, I/O are the signal port of intelligent card chip；Electricity
Fuse signal is the electric signal of fuse circuit output, for model selection in chip.
It is the safety circuit structure chart of the utility model specific implementation referring to Fig. 2.A built-in weak pull-up electricity in chip
Road, the weak pull-up circuit output is connected in wafer (wafer) scribe line.After chip testing starts, wafer do not subtract draw when, by
It is weak pull-up in itself in the circuit, now the output end is connected with the ground wire in scribe line, therefore the circuit output is low level；
Once wafer reduction scribing, the connection of the circuit and scribe line ground wire is disconnected, the circuit output is high level.According to the circuit
The different conditions of output, chip can enter different mode of operations.Fuse circuit utilizes chip internal circuits and Wafer Dicing
The mutual cooperation of groove so that its output state can subtract in chip draws front and rear change.Test is normally entered before chip scribing
Pattern is tested, after the completion of test, and there is provided carry out normal mode work to user for reduction scribing.Shape is exported with fuse circuit
State can allow chip to enter test pattern, not allow chip to enter test pattern after scribing as foundation before scribing.It is logical
Cross this mode, it is ensured that user data will not be changed by mistake.
The implementation of the outside Wafer Dicing groove of safety circuit connection of the present utility model is not limited to reality discussed above
Apply mode.The obvious conversion or replacement enlightened based on the utility model should also be as being considered within guarantor of the present utility model
Protect scope.Embodiment above is used for disclosing optimal implementation of the present utility model, to cause the common of this area
Technical staff can reach mesh of the present utility model using numerous embodiments of the present utility model and a variety of alternatives
's.
Claims (2)
1. a kind of safety circuit for chip testing, it is characterised in that the safety circuit includes internal logic circuit and molten
Silk circuit, internal logic circuit connection fuse circuit, fuse circuit is a weak pull-up resistor, and the output end of fuse circuit is connected to
The ground wire of outside Wafer Dicing groove；
During chip testing, the electric fuse signal of fuse circuit output is sent to internal logic circuit, and internal logic circuit is according to electric smelting
The level of silk signal is judged, if electric fuse signal is low level, allows chip to enter test pattern；If electric fuse
Signal is high level, then does not allow chip to enter test pattern.
2. it is used for the safety circuit of chip testing as claimed in claim 1, it is characterised in that the fuse circuit, in wafer
When not carrying out reduction scribing, the ground wire of the outside Wafer Dicing groove of its output end connection, its electric fuse signal exported is low level；
When wafer carries out reduction scribing, its output end is connected with the ground wire of outside Wafer Dicing groove and is disconnected, its electric fuse exported
Signal is high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621306544.1U CN206353192U (en) | 2016-12-01 | 2016-12-01 | A kind of safety circuit for chip testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621306544.1U CN206353192U (en) | 2016-12-01 | 2016-12-01 | A kind of safety circuit for chip testing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206353192U true CN206353192U (en) | 2017-07-25 |
Family
ID=59347760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621306544.1U Active CN206353192U (en) | 2016-12-01 | 2016-12-01 | A kind of safety circuit for chip testing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206353192U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
| CN112749419A (en) * | 2020-12-31 | 2021-05-04 | 广州万协通信息技术有限公司 | Protection device and method for security chip test mode |
| CN114814531A (en) * | 2022-03-30 | 2022-07-29 | 上海先楫半导体科技有限公司 | Chip safety test circuit and logic chip |
-
2016
- 2016-12-01 CN CN201621306544.1U patent/CN206353192U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
| CN112749419A (en) * | 2020-12-31 | 2021-05-04 | 广州万协通信息技术有限公司 | Protection device and method for security chip test mode |
| CN112749419B (en) * | 2020-12-31 | 2023-11-21 | 广州万协通信息技术有限公司 | Protection device and method for safety chip test mode |
| CN114814531A (en) * | 2022-03-30 | 2022-07-29 | 上海先楫半导体科技有限公司 | Chip safety test circuit and logic chip |
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