CN106445560A - Testing method for chip operation system - Google Patents
Testing method for chip operation system Download PDFInfo
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- CN106445560A CN106445560A CN201610925050.XA CN201610925050A CN106445560A CN 106445560 A CN106445560 A CN 106445560A CN 201610925050 A CN201610925050 A CN 201610925050A CN 106445560 A CN106445560 A CN 106445560A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/10—Requirements analysis; Specification techniques
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/20—Software design
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- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a testing method for a chip operation system. The method includes the following steps that firstly, acceptance testing design is conducted by reviewing requirements for acceptance testing; if errors occur during acceptance testing, regression testing is conducted, and the fourth step is repeated for repeated testing; secondly, by means of testing requirement analysis and system testing design, system testing is conducted; if errors occur during system testing, regression testing is conducted, and the fourth step is repeated for repeated testing; thirdly, integration testing is prepared and conducted; if errors occur during integration testing, regression testing is conducted, and the fourth step is repeated for repeated testing; fourthly, detailed design is conducted, wherein unit testing is prepared and carried out; fifthly, codes are obtained. The chip testing method guarantees the quality of software in the development process, and aims at finding errors occurring in the program execution process, guaranteeing high quality in the user requirement development process, improving software development efficiency and shortening the development cycle.
Description
Technical field
The invention belongs to hardware development technical field, more particularly to a kind of method of testing for chip operating system.
Background technology
Increase rapidly in the application of every field with smart card, the requirement to its chip operating system quality is also increasingly
High.Software test is a particularly important ring in software life-cycle, is the critical stage of software quality assurance.It is that software is set
Meter and the final inspection of coding.Due to software product no form itself, it is complicated, knowledge highly dense logical product,
Not having a kind of software approach can ensure that does not have mistake during the design and realization of software, according to statistics, opens in software at present
Send out in totle drilling cost, the cost in test will account for 30%-40%.
Content of the invention
It is an object of the invention to provide a kind of method of testing for chip operating system, by the chip testing providing
Method ensure that software quality on stream it is therefore intended that the mistake occurring in discovery procedure implementation procedure, guarantee are used
High-quality during the requirement developing of family, improves the efficiency of software development, reduces the construction cycle.
The present invention is achieved by the following technical solutions：
The present invention is a kind of method of testing for chip operating system, comprises the steps：
Step one, user's request：By evaluating to demand, carry out an acceptance inspection test design, and carry out an acceptance inspection test；If check and accept surveying
Try out existing mistake and carry out regression test, separate regression steps four retest；
Step 2, demand analyses and design：By testing requirement analysis, system test designs, and carries out system test；If being
Unified test tries out existing mistake and carries out regression test, separate regression steps four retest；
Step 3, Outline Design：Integration testing prepares, and carries out integration testing；If mistake in integration testing being returned
Test, separate regression steps four retest；
Step 4, detailed design：Unit testing prepares, and carries out unit testing；
Step 5, is encoded.
Preferably, described system test adopts COS to test, and described COS test includes Basic function testing, the recovery of COS
Property test, durability test, performance test and HIST.
Preferably, the Basic function testing of described COS includes command functions test, file management test, command response survey
Examination and safety management test.
Preferably, described restorative test for test terminal and smart card in the communications only when, checking system self
Recovery capability.
The invention has the advantages that：
The chip detecting method that the present invention provides ensure that software quality on stream it is therefore intended that discovery procedure
The mistake occurring in implementation procedure, the high-quality ensureing in user's request development process, improve the efficiency of software development, and reduction is opened
The cycle of sending out.
Certainly, the arbitrary product implementing the present invention it is not absolutely required to reach all the above advantage simultaneously.
Brief description
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below by use required for embodiment description
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, can also be obtained other attached according to these accompanying drawings
Figure.
Fig. 1 is a kind of flow chart of method of testing for chip operating system of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is all other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of protection of the invention.
Refer to shown in Fig. 1, the present invention is a kind of method of testing for chip operating system, comprises the steps：
Step one, user's request：By evaluating to demand, carry out an acceptance inspection test design, and carry out an acceptance inspection test；If check and accept surveying
Try out existing mistake and carry out regression test, separate regression steps four retest；
Step 2, demand analyses and design：By testing requirement analysis, system test designs, and carries out system test；If being
Unified test tries out existing mistake and carries out regression test, separate regression steps four retest；
Step 3, Outline Design：Integration testing prepares, and carries out integration testing；If mistake in integration testing being returned
Test, separate regression steps four retest；
Step 4, detailed design：Unit testing prepares, and carries out unit testing；
Step 5, is encoded.
Wherein, system test adopts COS to test, described COS test include the Basic function testing of COS, restorative test,
Durability test, performance test and HIST.
Wherein, the Basic function testing of COS includes command functions test, file management test, command response test and pacifies
Full management test.Command functions test to as if basic command defined in IS07816 and the order related to industry, test
Can the function of card order meet demand.File management test includes file selection method test, representation of file is tested, proprietary
The property test of file test, constituent instruments and constituent instruments.Command response is tested by should test, blocking and return to bad command
State byte test two aspect returned is constituted.The main contents of safety management test have authentication functions and security access mechanism to survey
Examination.
Wherein, restorative test for test terminal and smart card in the communications only when, the self-recovery energy of checking system
Power.
If cos is long to the process time of instruction, easily can lead to its trading function that unexpected mistake occurs, cos's
Performance test concern is primarily with the response time of cos instruction sent to terminal.
HIST, also referred to as compatibility test, predominantly detect the interoperability of smart card and different pins eventually, with normal
As a example S1M card, what interoperability referred to is exactly that can SIM normally use in the mobile phone of different brands.
Carry out carrying out again system detectio after performance detection to the physical arrangement of chip.
Whether the working condition that object properties test is primarily referred to as card under different operating environment can keep with related protocol
Concordance, mainly includes the following aspects：
Physical characteristics：Including card outward appearance (as the size of card, contact size etc.), ultraviolet radiation, X-radiation, electric shock
The mechanical strength of surface section, card and chip and chip and contact, contact resistance, electromagnetic field, electrostatic, heat consumption, card power up secondary
Whether number etc. meets the regulation to it for the 1S07816.
Electrical characteristic：Under the Vcc value of chip normal work and Icc value, normal operating conditions, to Vcc, I/O, CLK, RST
The test of test point, the test under the idle, state such as full rate is idle, clock stops, to Icc.
Operating process：Interface equipment connects and contact activation, card reset, whether the release of contact meets related protocol.
Reset answer：Whether the S position answer ATR in asynchronous transmission is consistent with respective protocol.
Host-host protocol：Smart card and terminal are entered to follow identical agreement and are to ensure that both carry out the premise of proper communication.Transmission
Protocol test is also requisite.
It should be noted that in said system embodiment, included unit simply carries out drawing according to function logic
Point, but it is not limited to above-mentioned division, as long as being capable of corresponding function；In addition, each functional unit is concrete
Title also only to facilitate mutual distinguish, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that realizing all or part of step in the various embodiments described above method
The program that can be by complete come the hardware to instruct correlation, and corresponding program can be stored in an embodied on computer readable storage and be situated between
In matter, described storage medium, such as ROM/RAM, disk or CD etc..
Present invention disclosed above preferred embodiment is only intended to help illustrate the present invention.Preferred embodiment is not detailed
Describe all of details, also do not limit the specific embodiment that this invention is only described.Obviously, the content according to this specification,
Can make many modifications and variations.This specification is chosen and is specifically described these embodiments, is to preferably explain the present invention
Principle and practical application so that skilled artisan can be best understood by and utilize the present invention.The present invention is only
Limited by claims and its four corner and equivalent.
Claims (4)
1. a kind of method of testing for chip operating system is it is characterised in that comprise the steps：
Step one, user's request：By evaluating to demand, carry out an acceptance inspection test design, and carry out an acceptance inspection test；If Acceptance Test goes out
Existing mistake carries out regression test, separate regression steps four retest；
Step 2, demand analyses and design：By testing requirement analysis, system test designs, and carries out system test；If system is surveyed
Try out existing mistake and carry out regression test, separate regression steps four retest；
Step 3, Outline Design：Integration testing prepares, and carries out integration testing；If mistake in integration testing carries out regression test,
Separate regression steps four retest；
Step 4, detailed design：Unit testing prepares, and carries out unit testing；
Step 5, is encoded.
2. a kind of method of testing for chip operating system according to claim 1 is it is characterised in that described system is surveyed
Pilot production is tested with COS, and described COS test includes the Basic function testing of COS, restorative test, durability test, performance test
And HIST.
3. a kind of method of testing for chip operating system according to claim 2 is it is characterised in that described COS
Basic function testing includes command functions test, file management test, command response test and safety management test.
4. a kind of method of testing for chip operating system according to claim 2 is it is characterised in that described restorative
Test for test terminal and smart card in the communications only when, the self-recovery ability of checking system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610925050.XA CN106445560A (en) | 2016-10-30 | 2016-10-30 | Testing method for chip operation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610925050.XA CN106445560A (en) | 2016-10-30 | 2016-10-30 | Testing method for chip operation system |
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| CN106445560A true CN106445560A (en) | 2017-02-22 |
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| CN201610925050.XA Pending CN106445560A (en) | 2016-10-30 | 2016-10-30 | Testing method for chip operation system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920362A (en) * | 2018-05-30 | 2018-11-30 | 邵阳学院 | A kind of test macro of computer software |
| CN111399805A (en) * | 2020-03-13 | 2020-07-10 | 云南云电同方科技有限公司 | Software development management system and method |
| CN111488290A (en) * | 2020-04-28 | 2020-08-04 | 南方电网数字电网研究院有限公司 | Thread testing method and device based on intelligent electric meter operating system |
| CN112052184A (en) * | 2020-09-29 | 2020-12-08 | 北京智芯微电子科技有限公司 | Automatic generation method and device for test script and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615117A (en) * | 2008-06-23 | 2009-12-30 | 株式会社日立制作所 | Software development process modeling and method |
| CN101882104A (en) * | 2009-05-08 | 2010-11-10 | 北京正辰科技发展有限责任公司 | Test information management system |
| US20120102450A1 (en) * | 2010-10-22 | 2012-04-26 | Infosys Technologies Limited | Method and system for determining performance parameters of software project based on software-engineering tools usage |
-
2016
- 2016-10-30 CN CN201610925050.XA patent/CN106445560A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615117A (en) * | 2008-06-23 | 2009-12-30 | 株式会社日立制作所 | Software development process modeling and method |
| CN101882104A (en) * | 2009-05-08 | 2010-11-10 | 北京正辰科技发展有限责任公司 | Test information management system |
| US20120102450A1 (en) * | 2010-10-22 | 2012-04-26 | Infosys Technologies Limited | Method and system for determining performance parameters of software project based on software-engineering tools usage |
Non-Patent Citations (3)
| Title |
|---|
| 周学海 等: "软件测试过程模型的改进——并行V模型", 《计算机工程与应用》 * |
| 宁咏梅: "智能卡操作系统（COS）的系统测试方法的设计与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
| 庞灵: "嵌入式软件测试V模型的研究", 《测试测量技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108920362A (en) * | 2018-05-30 | 2018-11-30 | 邵阳学院 | A kind of test macro of computer software |
| CN111399805A (en) * | 2020-03-13 | 2020-07-10 | 云南云电同方科技有限公司 | Software development management system and method |
| CN111488290A (en) * | 2020-04-28 | 2020-08-04 | 南方电网数字电网研究院有限公司 | Thread testing method and device based on intelligent electric meter operating system |
| CN112052184A (en) * | 2020-09-29 | 2020-12-08 | 北京智芯微电子科技有限公司 | Automatic generation method and device for test script and storage medium |
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Application publication date: 20170222 |
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