CN102567202A - Double-interface intelligent card simulator based on field programmable gata array (FPGA) - Google Patents
Double-interface intelligent card simulator based on field programmable gata array (FPGA) Download PDFInfo
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- CN102567202A CN102567202A CN2011104361344A CN201110436134A CN102567202A CN 102567202 A CN102567202 A CN 102567202A CN 2011104361344 A CN2011104361344 A CN 2011104361344A CN 201110436134 A CN201110436134 A CN 201110436134A CN 102567202 A CN102567202 A CN 102567202A
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Abstract
The invention discloses a double-interface intelligent card simulator based on a field programmable gata array (FPGA), which is high in efficiency and reliability, low in cost and high in performance and comprises a simulation antenna, a contact type card surface, an analog front end and a simulation unit. The analog front end is in non-contact type communication with the simulation antenna through a wireless passage, communication between the analog front end and the simulation antenna follows an international standardization organization (ISO)/ international electrotechnical commission (IEC) 14443 TypeA international standard, contact type communication between the contact type card surface and the analog front end is achieved through a wire passage, communication between the analog front end and the contact type interface follows an ISO/IEC 7816 international standard, the simulation unit is communicated with the analog front end through the wire passage, and the analog front end and the simulation unit follow a universal serial bus (USB) v 2.0 communication protocol. The simulation antenna and the contact type card surface simulate communication modes with a reader under two working modes, the simulation unit is achieved through an FPGA chip, the analog front end is achieved through a radio frequency chip, and the priority of the communication mode between the analog front end and the contact type interface is higher than that of the communication mode between the analog front end and the simulation antenna.
Description
Technical field
The present invention relates to a kind of intelligent card emluator, specifically, relate to a kind of double-interface smart card simulation device based on FPGA.
Background technology
Smart card (Smart Card) is a kind of common name that is embedded with the plastic clip of IC chip; Difference by embedded chip type; IC-card can be divided three classes: storage card; Logic encryption card; The CPU card, but have only the just smart card of real at last meaning of CPU card, the integrated circuit in the smart card (CPU card) comprises central processing unit (CPU), EEPROM (EEPROM), random access memory (RAM) and is solidificated in the card internal operating system COS (Chip Operating System) in the ROM (read-only memory) (ROM).The general employing is integrated with the overhead control unit of the customization microcontroller (MCU) of CPU, storer and peripheral hardware as smart card.
FPGA (Field Programmable Gate Array); It is field programmable gate array; Be the highest a kind of of integrated level in the special IC (ASIC); The user can reconfigure the logic module and the I/O module of FPGA inside, with realization user's logic, thereby also is used to the simulation to CPU.The user is placed in Flash or the eeprom chip the programming data of FPGA; Be loaded among the FPGA through powering on, it is carried out initialization, also can be online to its programming; Realization system on-line reorganization, this characteristic can make up a MCU who customizes in real time according to the calculation task difference.
Double-interface smart card (CPU card) chip refers to the chip internal contact and same microprocessor, operating system and EEPROM are shared in contactless interface.The contact interface meets the ISO/IEC7816 international standard; Contactless interface meets ISO/IEC 14443 TypeA international standards; Microcontroller compatibility standard MCS-51 instruction set; Built in hardware 3DES coprocessor and real random number generator can provide the attack protection function of high security mechanism, can be applicable to every field such as finance, social security, mobile payment, stored value card, electronic certificate, public transport, city all-purpose card and government utility charge.
Cost has high input because design of integrated circuit has, the R&D cycle is long and throw characteristics such as sheet has a big risk; Therefore in R&D process; Chip emulator is of crucial importance; The double-interface smart card chip emulator is the software and hardware IDE that designs to the double-interface smart card technical characterstic, mainly contains two big functions: the emulation experiment platform of the IDE of software and hardware.
Two interface C PU the core of the card sheets are to have contact and contactless intelligent CPU card concurrently, and dual mode needs the different supporting exploitations of hardware environment, and therefore, the research and development of two interface C PU the core of the card sheets have very harsh requirement to emulator:
1. emulator software IDE; Can provide COS program (assembly language, C language etc.) the code editing environment and with the COS program code be compiled as the translation and compiling environment of the machine instruction code that two interface C PU cards can carry out and can will compile after machine instruction code download to emulator, carry out by emulator;
2. emulator simulation hardware experiment porch can carry out complete simulation to the hardware system of two kinds of working methods of two interface C PU cards, can accomplish the work of various pairs of interface C PU card correlated performance testing researches by the simulation hardware experiment porch;
3. emulator can not take user resources, and promptly two interface C PU card functions of hardware simulation system are identical with real card, the efficient of while emulator systems, and like program download efficiency, debug efficient, promptly traffic efficiency and debug feedback efficiency want high.
Existing deficiency: at present existing numerous two interface C PU the core of the card sheet emulators of using based on RFID; Usually can not satisfy or can not all satisfy of the harsh requirement of two interface C PU the core of the card sheets to emulator; Therefore, existing pair of interface C PU the core of the card sheet emulator is difficult to directly apply to the two interface C PU card fields of RFID.
Summary of the invention
To above deficiency; The invention provides a kind of easy and simple to handle; High-level efficiency, highly reliable, realize the low high performance double-interface smart card simulation device of cost based on FPGA; It comprises phantom antenna; Realize the AFE(analog front end) of contactless communication with said phantom antenna through radio channel, and it comprises also and said AFE(analog front end) is realized the contact card face of contact communication through wired passage with the simulation unit of said AFE(analog front end) through wired channel communications, said AFE(analog front end) adopts radio frequency chip to realize; ISO/IEC 14443 TypeA international standards are followed in communication between AFE(analog front end) and the phantom antenna, and ISO/IEC 7816 international standards are followed in the communication between AFE(analog front end) and the contact interface.
The priority of the communication modes between said AFE(analog front end) and the contact interface is higher than the communication modes between AFE(analog front end) and the phantom antenna.
Said simulation unit adopts fpga chip to realize, follows the USBv2.0 communications protocol between said AFE(analog front end) and the simulation unit.
Said simulation unit comprises digital baseband and customization MCU two parts.
Said digital baseband is made up of miller-decoded unit, Manchester's cde unit, CRC check unit, data register, odd-even check unit, map unit, anticollision unit and host state machine; Said customization MCU is made up of randomizer, ROM (read-only memory), RAS, electricallyerasable ROM (EEROM), central processing unit and 3DES coprocessor.
Beneficial effect of the present invention is:
1) operability of the present invention: the present invention the software end integrated FPGA file and COS file routine source code is write, editing interface; Source program compiling interface; Program code is downloaded the interface; Source program operation, tracking, debugging interface, and get final product coil antenna or be connected corresponding with reader of contact card face at hardware end, the developer can download to the FPGA development board to the FPGA file in the integrated software system of PC; And realize and accomplish each process of COS program development, debugging, can realize emulation so hold to two interface C PU cards at PC.
2) high efficiency of the present invention: the present invention has realized program download efficiency, debug efficient at the software end, i.e. the raising of traffic efficiency and debug feedback efficiency; At hardware end, the CPU of analogue system realizes that function is in full accord with two interface C PU cards, so can not take user's system resource.
3) high reliability of the present invention: the present invention has adopted the proven technique module at the soft or hard end.Software aspect, machine code compile based on the MCS-51 instruction set, and communication protocol adopts the USBv2.0 agreement; And hardware simulation system is based on FPGA and radio frequency chip is realized; FPGA and radio frequency chip technology maturation, itself has high reliability, and the digital baseband and customization MCU that utilize FPGA to build; Its inner structure is in full accord with two interface C PU cards, can realize the emulation to two interface C PU cards fully.
4) low-cost design of the present invention: the double-interface smart card simulation device based on FPGA of the present invention is realizing aspect the simulation hardware that simply module is succinct.FPGA device, radio frequency chip and reader all are the products of technology maturation, do not need to design and develop hardware module again, thereby have reduced R&D costs.But and inner logic module and the I/O module repeated configuration of FPGA, so FPGA can realize recycle, reduced cost.
Description of drawings
Fig. 1 is the double-interface smart card simulation device functional framework figure based on FPGA of the present invention;
Fig. 2 is the double-interface smart card simulation device schematic diagram of the function based on FPGA of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is further set forth.
Double-interface smart card simulation device based on FPGA of the present invention is made up of software integration development system and hardware simulation system; Software integration development system comprises that FPGA file and COS file routine source code are write, editing interface; Source program compiling interface; Program code is downloaded interface and source program operation, follows the tracks of, is debugged the interface, and the developer can download to the FPGA development board to the FPGA file through this software integration development system, and realizes and accomplish each process of COS program development, debugging.Double-interface smart card is divided into AFE(analog front end) and digital baseband two parts; And can operate as normal under two kinds of mode of operations, therefore, hardware simulation system with fpga chip simulated digital base band with customize CPU; With radio frequency chip analogue simulation front end; Peripheral circuit is configured to coil antenna and contact card face respectively, but the complete contactless mode of operation of emulation after the coil antenna in the connection, but the complete contact mode of operation of emulation in contact card face to the reader in the connection; Through above implementation method, hardware simulation system can the complete two interface C PU cards of emulation.
As depicted in figs. 1 and 2; Double-interface smart card simulation device based on FPGA of the present invention comprises phantom antenna 40, contact card face 50, AFE(analog front end) 10 and simulation unit 3; Realize contactless communication through radio channel between AFE(analog front end) 10 and the phantom antenna 40; ISO/IEC 14443 TypeA international standards are followed in communication between AFE(analog front end) 10 and the phantom antenna 40; Realize the contact communication through wired passage between contact card face 50 and the AFE(analog front end) 10, ISO/IEC 7816 international standards are followed in the communication between AFE(analog front end) 10 and the contact interface 50, pass through wired channel communications between simulation unit 3 and the AFE(analog front end) 10; Follow the USBv2.0 communications protocol between AFE(analog front end) 10 and the simulation unit 3, through under phantom antenna 40 and two kinds of mode of operations of contact card face 50 emulation with the communication modes of reader.Wherein, simulation unit 3 adopts fpga chip to realize, AFE(analog front end) 10 adopts radio frequency chip to realize that the priority of the communication modes between AFE(analog front end) 10 and the contact interface 50 is higher than the communication modes between AFE(analog front end) 10 and the phantom antenna 40.
Simulation unit 3 comprises digital baseband 20 and customization MCU30 two parts; These two parts adopt existing current techique, and promptly digital baseband 20 is made up of miller-decoded unit 21, Manchester's cde unit 22, CRC check unit 23, data register 24, odd-even check unit 25, map unit 26, anticollision unit 27 and host state machine 28; Said customization MCU30 is made up of randomizer 31, ROM (read-only memory) 32, RAS 33, electricallyerasable ROM (EEROM) 34, central processing unit 35 and 3DES coprocessor 36.
Double-interface smart card simulation device of the present invention is a software and hardware IDE; Make detailed description with regard to its concrete operations below; Wherein the USBv2.0 communications protocol is adopted in communication between hardware simulation system and the PC end software integration development system, and the ISO-IEC-14443 agreement is observed in the communication between hardware simulation system and the card reader.
At first be to accomplish the writing, compile, verify and download on the eeprom chip of FPGA of FPGA file on the software integration development system, this software integration development system provides two kinds of FPGA file downloading modes, JTAG pattern and EPCS patterns.Both differences are: the former data download will disappear in FPGA development board outage back automatically, and the latter then can preserve lastingly.When doing the COS exploitation, recommend to use the latter.
Be the writing compiling and the COS file downloaded to the ROM (read-only memory) 32 (ROM) of FPGA emulator of setting and COS file of on software integration development system, accomplishing the COS environment then.Reader is connected with PC, with the FPGA emulator of having downloaded FPGA file and COS file respectively through connecting coil antenna end and contact card face to realize under two kinds of mode of operations and the communication between the reader.The pattern of asking, replying is taked in communication between software integration development system and the hardware simulation system; Be that each operational order all is to send a request or order by the software end; The simulation hardware termination is promptly carried out corresponding operation after receiving corresponding request or order, then with the execution result loopback to the software end.Open the emulation interface of software integration development system, click SR, can be in the order output window viewing command sequence, returned content and return state.Clicking increases order button, in the dialog box that ejects, imports custom instruction, will in the order output window, see returned content and return state.
The above is merely preferred embodiments of the present invention; The present invention is not limited to above-mentioned embodiment; In implementation process, possibly there is local small structural modification; If various changes of the present invention or modification are not broken away from the spirit and scope of the present invention, and belong within claim of the present invention and the equivalent technologies scope, then the present invention also is intended to comprise these changes and modification.
Claims (5)
1. based on the double-interface smart card simulation device of FPGA; It comprises phantom antenna; Realize the AFE(analog front end) of contactless communication with said phantom antenna through radio channel, and with the simulation unit of said AFE(analog front end) through wired channel communications, it is characterized in that; It also comprises the contact card face of realizing the contact communication with said AFE(analog front end) through wired passage; Said AFE(analog front end) adopts radio frequency chip to realize that ISO/IEC 14443 TypeA international standards are followed in the communication between AFE(analog front end) and the phantom antenna, and ISO/IEC 7816 international standards are followed in the communication between AFE(analog front end) and the contact interface.
2. the double-interface smart card simulation device based on FPGA according to claim 1 is characterized in that the priority of the communication modes between said AFE(analog front end) and the contact interface is higher than the communication modes between AFE(analog front end) and the phantom antenna.
3. the double-interface smart card simulation device based on FPGA according to claim 1 is characterized in that, said simulation unit adopts fpga chip to realize, follows the USBv2.0 communications protocol between said AFE(analog front end) and the simulation unit.
4. the double-interface smart card simulation device based on FPGA according to claim 2 is characterized in that, said simulation unit comprises digital baseband and customization MCU two parts.
5. the double-interface smart card simulation device based on FPGA according to claim 4; It is characterized in that said digital baseband is made up of miller-decoded unit, Manchester's cde unit, CRC check unit, data register, odd-even check unit, map unit, anticollision unit and host state machine; Said customization MCU is made up of randomizer, ROM (read-only memory), RAS, electricallyerasable ROM (EEROM), central processing unit and 3DES coprocessor.
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| CN2011104361344A CN102567202A (en) | 2011-12-22 | 2011-12-22 | Double-interface intelligent card simulator based on field programmable gata array (FPGA) |
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| CN2011104361344A CN102567202A (en) | 2011-12-22 | 2011-12-22 | Double-interface intelligent card simulator based on field programmable gata array (FPGA) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106407064A (en) * | 2016-10-31 | 2017-02-15 | 上海华虹集成电路有限责任公司 | Double-interface smart card chip simulator |
| CN106547691A (en) * | 2016-10-31 | 2017-03-29 | 福建联迪商用设备有限公司 | A kind of POS terminal method of testing and system for running on PC ends |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1858752A (en) * | 2006-04-29 | 2006-11-08 | 中山大学 | Radio communication simulation device based on FPGA and USB storage device |
| CN101131665A (en) * | 2006-08-25 | 2008-02-27 | 上海华虹集成电路有限责任公司 | General smart card simulator |
| CN102096725A (en) * | 2009-12-11 | 2011-06-15 | 无锡华润矽科微电子有限公司 | Field programmable gate array (FPGA)-based simulator |
| CN201993747U (en) * | 2011-04-13 | 2011-09-28 | 广州中大微电子有限公司 | Non-contact intelligent card emulator |
-
2011
- 2011-12-22 CN CN2011104361344A patent/CN102567202A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1858752A (en) * | 2006-04-29 | 2006-11-08 | 中山大学 | Radio communication simulation device based on FPGA and USB storage device |
| CN101131665A (en) * | 2006-08-25 | 2008-02-27 | 上海华虹集成电路有限责任公司 | General smart card simulator |
| CN102096725A (en) * | 2009-12-11 | 2011-06-15 | 无锡华润矽科微电子有限公司 | Field programmable gate array (FPGA)-based simulator |
| CN201993747U (en) * | 2011-04-13 | 2011-09-28 | 广州中大微电子有限公司 | Non-contact intelligent card emulator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106407064A (en) * | 2016-10-31 | 2017-02-15 | 上海华虹集成电路有限责任公司 | Double-interface smart card chip simulator |
| CN106547691A (en) * | 2016-10-31 | 2017-03-29 | 福建联迪商用设备有限公司 | A kind of POS terminal method of testing and system for running on PC ends |
| CN106407064B (en) * | 2016-10-31 | 2018-10-26 | 上海华虹集成电路有限责任公司 | Double interface intelligent card chip emulator |
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Application publication date: 20120711 |