CN206178791U

CN206178791U - PCIE bus bridge interface based on FPGA

Info

Publication number: CN206178791U
Application number: CN201621015221.7U
Authority: CN
Inventors: 黄伟
Original assignee: SHANGHAI PROPHET ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: SHANGHAI PROPHET ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2016-08-31
Filing date: 2016-08-31
Publication date: 2017-05-17
Anticipated expiration: 2026-08-31

Abstract

The utility model discloses a PCIE bus bridge interface based on FPGA, including the CPU module, the PCIE bus is passed through to the CPU module and programmable chip links to each other, programmable chip links to each other through different buses and corresponding external equipment, be equipped with pull -up regulating electrical resistance, drop -down regulating electrical resistance in programmable chip and external equipment's the connection bus or match electric capacity, different buses include I2C bus, SPI bus, UART bus, CAN bus and/or PCI bus, programmable chip is FPGA module or CPLD module. The utility model discloses passing through PCIE bus and programmable chip with the CPU module and linking to each other, utilize programmable chip to pass through different buses and various non - PCIE equipment links to each other, has replaced original PCIE switching integrated circuit board and switching chip, connect conveniently and easily extension.

Description

A kind of PCIE bus bridge interfaces based on FPGA

Technical field

This utility model is related to a kind of board switching interface, more particularly to a kind of PCIE bus bridge interfaces based on FPGA.

Background technology

In embedded systems, in order to increasingly meet bandwidth requirement of the external equipment to bus, PCI-Express (with Lower abbreviation PCIE) it is widely used as bus and interface of new generation, it is high, simultaneous that it is mainly characterized by data transmission rate Capacitive is good, possess plurality of specifications.On the market some main flow processors (such as DSP, ARM, PowerPC) can be supported well PCIE.But in Embedded System Design, with the requirement to cost, the requirement to integrated level and requirement of real-time Raising.Can mainly face following problem at present：1st, by PCIE bus access, some do not support that PCIE's is outer to processor During portion's equipment, extra PCIE switching boards or PCIE switching chips is generally required, as shown in Figure 1.2nd, it is embedded at some In system design, the dedicated bus interface (I2C/SPI/UART/CAN etc.) of processor is often not enough, needs extra extension. This is also required to the function (bus bridge) that can support to be transferred between different bus, realizes that signaling transfer point is typically required special switching Plate or switching chip, can increase to a certain extent the complexity of design, can also improve the cost of design, while being also unfavorable for producing The debugging of product and maintenance.

Utility model content

Technical problem to be solved in the utility model is to provide a kind of PCIE bus bridge interfaces based on FPGA, can replace Original PCIE switching boards and switching chip are changed, has been connected with various non-PCIE devices by different buses, it is easy to connect And be easy to extend.

This utility model is to provide a kind of PCIE based on FPGA to solve the technical scheme that above-mentioned technical problem is adopted Bus bridge interface, including CPU module, wherein, the CPU module is connected by PCIE buses with programmable chip, described to compile Journey chip is connected by different buses with corresponding external equipment, the connection bus of the programmable chip and external equipment Be provided with pull-up and adjust resistance, drop-down regulation resistance or matching capacitance, the different bus include I2C buses, spi bus, UART buses, CAN and/or pci bus.

The above-mentioned PCIE bus bridge interfaces based on FPGA, wherein, the programmable chip is FPGA module or CPLD moulds Block, the CPU module is dsp controller, ARM controller or PowerPC controllers.

This utility model contrast prior art has following beneficial effect：The PCIE based on FPGA that this utility model is provided Bus bridge interface, CPU module is connected by PCIE buses with programmable chip, using programmable chip by different buses It is connected with various non-PCIE devices, substituted for original PCIE switching boards and switching chip；It is easy to connect and be easy to extension.

Description of the drawings

Fig. 1 is existing PCIE versabus bridge switching board circuitry block schematic diagram；

Fig. 2 is PCIE bus bridge interface circuitry block schematic diagram of this utility model based on FPGA；

Fig. 3 manages schematic diagram for the internal connection of this utility model FPGA；

Fig. 4 is that matching capacitance schematic diagram is arranged in the connection bus of this utility model FPGA and external equipment；

Fig. 5 is that upper pull down resistor schematic diagram is arranged in the connection bus of this utility model FPGA and external equipment.

In figure：

The non-PCIE device of 1CPU modules 2FPGA module 3

Specific embodiment

With reference to the accompanying drawings and examples the utility model will be further described.

Fig. 2 is PCIE bus bridge interface circuitry block schematic diagram of this utility model based on FPGA；Fig. 3 is this utility model The internal connection reason schematic diagram of FPGA.

Fig. 2 and Fig. 3, the PCIE bus bridge interfaces based on FPGA that this utility model is provided, including CPU module 1 are referred to, The CPU module 1 be dsp controller, ARM controller or PowerPC controllers, wherein, the CPU module 1 by PCIE it is total Line is connected with programmable chip, and the programmable chip is connected by different buses with corresponding external equipment, it is described can The connection bus of programming chip and external equipment is provided with pull-up and adjusts resistance, drop-down regulation resistance or matching capacitance, it is described not Same bus includes I2C buses, spi bus, UART buses, CAN and/or pci bus.The programmable chip is FPGA Module 2 or CPLD modules, by different buses various non-PCIE devices 3 are connected.

This utility model utilizes programmability, motility, concurrency, the high-speed computation of data and the transmission of FPGA module 2 Property completes the bridging functionality of PCIE buses.Each non-PCIE device 3 is connected by respective bus with FPGA module 2, and these are total Wire protocol can be I2C/SPI/UART/CAN/PCI etc..According to different application requirements, spirit can be realized by FPGA programmings Configuration living；The PCIE bus bridge functions of being realized using the abundant programmable resource in FPGA inside.

FPGA has programmable input/output pin unit (abbreviation I/O pins), is fpga chip and external circuitry connects Oral area point, complete under different electrical characteristics to the driving of input and output signal with match requirement.These I/O pins of FPGA inside Classified by group, the different I/O electrical standards of support that can be independent per group can be flexibly adapted to not using FPGA developing instruments With electrical equipment standard and I/O physical characteristics, it is also possible to the pull-up in connection bus of harmonizing adjust resistance, drop-down regulation resistance or With electric capacity, as shown in Figure 4 and Figure 5；It is connected without extra interface circuit such that it is able to match one by one.

Concrete advantage of the present utility model is as follows：Firstth, the PCIE bus bridge work(realized using programmable chip FPGA Can, PCIE switching boards and the special switching chips of some PCIE can be saved in constructing system, it is only necessary to a piece of FPGA cores Piece, so as to eliminate design cost.Secondth, FPGA possesses high programmability, and those skilled in the art can be different according to PCIE Specification, the different bus protocol of the quantity of non-PCIE device and external equipment flexibly configured.3rd, FPGA is carried Perfect development environment is supplied, has possessed scene scalable.Facilitate the upgrading and maintenance of product on stream.4th, profit The PCIE bus bridge interfaces built with the FPGA of high-speed parallel computing, compare some are general on market PCIE switching boards or core Piece can at utmost play the switching efficiency of bus bridge.

Although this utility model is disclosed as above with preferred embodiment, so it is not limited to this utility model, any Those skilled in the art, in without departing from spirit and scope of the present utility model, when a little modification and perfect, therefore this can be made The protection domain of utility model is when by being defined that claims are defined.

Claims

1. a kind of PCIE bus bridge interfaces based on FPGA, including CPU module, it is characterised in that the CPU module passes through PCIE Bus is connected with programmable chip, and the programmable chip is connected by different buses with corresponding external equipment, described The connection bus of programmable chip and external equipment is provided with pull-up and adjusts resistance, drop-down regulation resistance or matching capacitance, described Different buses includes I2C buses, spi bus, UART buses, CAN and/or pci bus.

2. PCIE bus bridge interfaces based on FPGA as claimed in claim 1, it is characterised in that the programmable chip is FPGA module or CPLD modules, the CPU module is dsp controller, ARM controller or PowerPC controllers.