CN110362525A - A kind of method, system and board for realizing Multi-serial port switching based on CPLD - Google Patents
A kind of method, system and board for realizing Multi-serial port switching based on CPLD Download PDFInfo
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- CN110362525A CN110362525A CN201910520642.7A CN201910520642A CN110362525A CN 110362525 A CN110362525 A CN 110362525A CN 201910520642 A CN201910520642 A CN 201910520642A CN 110362525 A CN110362525 A CN 110362525A
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- 238000010586 diagram Methods 0.000 description 3
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
This application discloses it is a kind of based on CPLD realize Multi-serial port switching method, system and board, this method comprises: obtain control enable signal and in control terminal BMC UART module multiple groups UART signal；According to control enable signal, UART signal to be output is determined from multiple groups UART signal using CPLD；UART signal to be output is exported using an external connector.System in the application includes: signal acquisition module, signal determining module to be output and an external connector.Board in the application includes: BMC and realizes the system that Multi-serial port switches based on CPLD.By the application, the flexible switching of serial ports can be realized, be conducive to the accuracy and switching efficiency that improve serial ports switching, additionally it is possible to effectively save plate face space and Material Cost.
Description
Technical field
This application involves server board design fields, are based on CPLD (Complex more particularly to one kind
Programmable Logic Device, Complex Programmable Logic Devices) realize method, system and board that Multi-serial port switches.
Background technique
Serial ports is the important component in server board, in general, the serial ports in server board is mainly used for transmitting control
Hold BMC (Baseboard Management Controller, baseboard management controller) chip in UART module it is direct-connected come out
Signal, and pass through the external header of the signal.With the continuous enhancing of server and the function and performance of other electronic products, clothes
Usually there are multiple serial ports in business device board, and is frequently necessary to the progress serial ports in multiple serial ports of the same server board and cuts
It changes.
The method of serial ports switching is carried out at present referring to Fig. 1, current serial ports switching method is usually as shown in Figure 1, for
Multiple serial ports, the multiple external header (connector) of corresponding configuration, are respectively used to the switching of different serial ports in server board
And debugging, it is corresponded between serial ports and the end debug (debugging), when carrying out serial ports switching and debugging, commissioning staff is needed to carry
Debug plate serial ports, is debugged respectively by the way of manually tearing machine open.
However, being carried out in the method for serial ports switching at present, since serial ports and the end debug are one-to-one, different strings
Mouth corresponds to the different ends debug, and the switching between Multi-serial port is inflexible, and the switching efficiency of manual switching is low.Moreover, because string
Mouth is corresponded with the end debug, and multiple external header are arranged in server board for multiple serial ports needs, occupied
Board space is larger, is unfavorable for reducing PCB (Printed Circuit Board), printed circuit board) plate face density.
Summary of the invention
This application provides a kind of method, system and boards that Multi-serial port switching is realized based on CPLD, to solve existing skill
Mouth in art switches the problem that inflexible, switching efficiency is low and serial ports switching occupancy board space is larger.
In order to solve the above-mentioned technical problem, the embodiment of the present application discloses following technical solution:
A method of Multi-serial port switching is realized based on CPLD, which comprises
Obtain control enable signal and in control terminal BMC UART module multiple groups UART (Universal
Asynchronous Receiver/Transmitter, universal asynchronous receiving-transmitting transmitter) signal, the UART module includes SYS
UART module and BMC UART module, and the SYS UART module issues SYS UART signal, the BMC UART module hair
BMC UART signal out；
According to the control enable signal, UART signal to be output is determined from multiple groups UART signal using CPLD；
Using an external connector, the UART signal to be output is exported.
Optionally, described according to the control enable signal, using CPLD, determination is to be output from multiple groups UART signal
UART signal, comprising:
Obtain BMC GPIO (General-purpose input/output, universal input/defeated from control terminal BMC
Outlet) signal, a BMC GPIO signal includes two kinds of level states of high level and low level；
According to the level state of the BMC GPIO signal, determine UART signal to be output be SYS UART signal or
BMC UART signal, wherein two kinds of level states are matched with SYS UART signal and BMC UART signal one by one respectively.
Optionally, described according to the control enable signal, using CPLD, determination is to be output from multiple groups UART signal
UART signal, comprising:
The external connector and CPLD are connected with signal wire, and at least provided with power supply pin in the external connector
With ground connection pin；
CPLD determines that UART signal to be output is according to the connection status of the power supply pin and ground connection pin of external connector
SYS UART signal or BMC UART signal, wherein power supply pin is connected with ground connection pin and power supply pin and ground connection pin does not connect
Two states are connect, are matched one by one with SYS UART signal and BMC UART signal respectively.
Optionally, described according to the control enable signal, using CPLD, determination is to be output from multiple groups UART signal
UART signal, comprising:
One logic sum gate circuit, the input terminal of the logic sum gate circuit are set between the external connector and CPLD
It is connect with external connector, the output end of the logic sum gate circuit is connect with CPLD, and the input of the logic sum gate circuit
End includes at least first input end and the second input terminal, wherein and the first input is connect with the power supply pin of external connector, and second
The ground connection pin connection of input terminal and external connector；
CPLD determines UART letter to be output according to the level state of logic sum gate circuit first input and the second input terminal
Number be SYS UART signal or BMC UART signal.
Optionally, according to the control enable signal, UART to be output is determined from multiple groups UART signal using CPLD
Before signal, the method also includes:
The control enable signal and multiple groups UART signal are filtered.
A kind of system that Multi-serial port switching is realized based on CPLD, the system comprises:
Signal acquisition module, for obtain control enable signal and in control terminal BMC UART module multiple groups
UART signal, the UART module includes SYS UART module and BMC UART module, and the SYS UART module issues SYS
UART signal, the BMC UART module issue BMC UART signal；
Signal determining module to be output is used for according to the control enable signal, using CPLD from multiple groups UART signal
Determine UART signal to be output；
One external connector, for exporting to the UART signal to be output, and the external connector is defeated
The output end for entering end and CPLD connects, and the output end of the external connector is connect with the end debug.
Optionally, the signal determining module to be output includes:
BMC GPIO signal acquiring unit, for obtaining the BMC GPIO signal from control terminal BMC, a BMC
GPIO signal includes two kinds of level states of high level and low level；
Determination unit determines that UART signal to be output is SYS for the level state according to the BMC GPIO signal
UART signal or BMC UART signal, wherein two kinds of level states respectively with SYS UART signal and BMC UART signal one by one
Matching.
Optionally, the signal determining module to be output includes: signal wire and signal behavior unit to be output；
The signal wire connects the external connector and CPLD, and at least provided with power supply in the external connector
Pin and ground connection pin；
The signal behavior unit to be output, for the connection shape according to the power supply pin of external connector and ground connection pin
State determines that UART signal to be output is SYS UART signal or BMC UART signal, and wherein power supply pin is connected with ground connection pin,
And power supply pin and ground connection pin are not connected to two states, match one by one with SYS UART signal and BMC UART signal respectively.
Optionally, in the system further include: filter module, for believing the control enable signal and multiple groups UART
It number is filtered.
A kind of board for realizing Multi-serial port switching based on CPLD, the board include: BMC and any base as above
It in the system that CPLD realizes Multi-serial port switching, and include UART module in the BMC.
The technical solution that embodiments herein provides can include the following benefits:
The application provides a kind of method for realizing Multi-serial port switching based on CPLD, and this method obtains control enable signal first
And in control terminal BMC UART module multiple groups UART signal, then according to control enable signal, using CPLD from multiple groups
UART signal to be output is determined in UART signal, is treated output signal finally by an external connector and is exported.?
When carrying out the switching of multiple serial ports, the present embodiment obtains control enable signal by CPLD, then according to the electricity of control enable signal
Level state determines UART signal to be output, since control enable signal can also pass through hardware according to BMC flexible setting
Circuit controls, and there are two types of link modes for tool, and therefore, the present embodiment can flexibly switch serial ports, and avoid manually switching,
Be conducive to improve the accuracy and switching efficiency of serial ports switching.Meanwhile the present embodiment is true from multiple groups UART signal using CPLD
After fixed UART signal to be output, as soon as UART signal to be output can be exported by external connector,
It is the end debug to be connected by an external connector, therefore can effectively save plate face space, advantageously reduces pcb board density
And Material Cost.
The application also provides a kind of system for realizing Multi-serial port switching based on CPLD, which mainly includes signal acquisition mould
Block, signal determining module to be output and an external connector, wherein signal acquisition module and signal determining module to be output can be with
It is realized by CPLD.Signal determining module to be output can according to control enable signal, from multiple groups UART signal determine to
The UART signal of output, and controlling enable signal not only can be according to BMC flexible setting, but also can be controlled by hardware circuit,
There are two types of link modes for tool, and therefore, the flexibility that the present embodiment switches serial ports is higher, and the present embodiment passes through hardware or software
Mode carries out serial ports switching, avoids manually switching, and is conducive to the accuracy and switching efficiency that improve serial ports switching.In addition,
For multiple serial ports, after signal acquisition module and signal determining module to be output, the present embodiment passes through an external connection
Device exports URAT signal to be output, it is only necessary to which an external connector can be debugged from realizing, avoiding receiving has technology
In serial ports the case where matching an end debug, can effectively save plate face space, advantageously reduce pcb board density and object
Expect cost.
The application also provides a kind of board that Multi-serial port switching is realized based on CPLD, includes BMC in the board, as described above
Based on CPLD realize Multi-serial port switching system.It namely is provided with BMC, CPLD and an external connector in the board, is led to
CPLD is crossed to UART signal to be output is determined from multiple groups UART signal, eventually by an external connector to be output
UART signal is exported, to realize the flexible switching of Multi-serial port, while can substantially reduce the plate face space of board, favorably
In saving Material Cost.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The application can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the application
Example, and together with specification it is used to explain the principle of the application.
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic illustration of serial ports switching method in background technique；
Fig. 2 is a kind of process signal for the method that Multi-serial port switching is realized based on CPLD provided by the embodiment of the present application
Figure；
Fig. 3 is the schematic illustration for realizing Multi-serial port switching in the embodiment of the present application based on CPLD；
Fig. 4 is the GPIO interface connected mode schematic diagram of toggle switch and CPLD；
Fig. 5 is a kind of structural representation for the system that Multi-serial port switching is realized based on CPLD provided by the embodiment of the present application
Figure.
Specific embodiment
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described implementation
Example is merely a part but not all of the embodiments of the present application.Based on the embodiment in the application, this field is common
The application protection all should belong in technical staff's every other embodiment obtained without making creative work
Range.
The application in order to better understand explains in detail presently filed embodiment with reference to the accompanying drawing.
Embodiment one
Referring to fig. 2, Fig. 2 is a kind of stream for the method that Multi-serial port switching is realized based on CPLD provided by the embodiment of the present application
Journey schematic diagram.As shown in Figure 2, the method for realizing Multi-serial port switching based on CPLD in the present embodiment, mainly comprises the following processes:
S1: obtain control enable signal and in control terminal BMC UART module multiple groups UART signal.
Wherein, the UART module in BMC chip includes SYS UART module and BMC UART module, and SYS UART module
SYS UART signal is issued, BMC UART module issues BMC UART signal.SYS UART module is system debug mode, BMC
UART module is BMC debud mode.
Realize that the schematic illustration of Multi-serial port switching may refer to Fig. 3 based on CPLD in the present embodiment, MB is service in Fig. 3
Device mainboard, BMC UART PART are UART module in BMC, and TX is to send signal, and RX is to receive signal, and P3V3 is power supply pin,
GND is ground connection pin, and 4pin header is the connector of 4pin.From the figure 3, it may be seen that controlling enable signal OE in the present embodiment has two
Road, respectively control enable signal OE1 and control enable signal OE2.Wherein OE1 is controlled by BMC, comes from BMC；OE2 is by hardware
Route is controlled by logic level, comes from peripheral interface.The present embodiment obtains control enable signal and multiple groups by CPLD
UART signal.
With continued reference to Fig. 2 it is found that after getting control enable signal and multiple groups UART signal by CPLD, step is executed
S3: according to control enable signal, UART signal to be output is determined from multiple groups UART signal using CPLD.
According to the different acquisition modes of control enable signal, UART signal to be output is determined using CPLD in the present embodiment
There are two ways to: first method is the link mode of the OE1 in Fig. 3, and second method is the OE2 link mode in Fig. 3.
Specifically, the first determination method includes the following steps:
S031: the BMC GPIO signal from control terminal BMC is obtained.
Wherein, a BMC GPIO signal includes two kinds of level states of high level and low level.It, can if there is multichannel UART
To control different pin by the BMC GPIO signal for increasing BMC.
S032: according to the level state of BMC GPIO signal, determine UART signal to be output be SYS UART signal or
BMC UART signal.
Wherein, two kinds of level states are matched with SYS UART signal and BMC UART signal one by one respectively.BMC can be set
When GPIO signal is high level, UART signal to be output is SYS UART signal, when BMC GPIO signal is low level, to defeated
UART signal out is BMC UART signal.Or on the contrary, UART to be output believes when setting BMC GPIO signal as high level
Number be BMC UART signal, BMC GPIO signal be low level when, UART signal to be output be SYS UART signal.
By above step S031 and S032 it is found that the link mode of OE1 is to carry out serial ports switching using software approach.In reality
In border, the high level and low level state of BMC GPIO signal can be set in Xshell software, to realize automatic switchover
Serial ports.
Second of determining method is hardware exchange method, and this method includes two kinds of implementations again.Wherein, the first hardware
Implementation includes the following steps:
S131: external connector and CPLD are connected with signal wire, and at least provided with power supply pin and is connect in external connector
Ground pin.
S132:CPLD determines UART to be output according to the connection status of the power supply pin and ground connection pin of external connector
Signal is SYS UART signal or BMC UART signal.Wherein power supply pin is connected and power supply pin and ground connection with ground connection pin
Pin is not connected to two states, matches one by one with SYS UART signal and BMC UART signal respectively.
When there is two groups of UART signals, can directly according to power supply pin in step S132 and ground connection pin connection status,
Determine output SYS UART signal or BMC UART signal.Such as: when power supply pin is connected with ground connection pin, export SYS UART
Signal exports BMC UART signal when power supply pin and ground connection pin is not connected to；Alternatively, when power supply pin is connected with ground connection pin
When, BMC UART signal is exported, when power supply pin and ground connection pin is not connected to, exports SYS UART signal.
When there is three groups or three groups or more UART signals, can the GPIO interface using a toggle switch and CPLD come
Determine that UART signal to be output is SYS UART signal or BMC UART signal.Wherein, the GPIO of toggle switch and CPLD connect
The connection type of mouth may refer to Fig. 4, and first UART signal is directed in Fig. 4, and the port 1 of toggle switch is grounded, and port 2 connects
Power supply, and port 2 connects the GPIO interface of CPLD；And so on, for second UART signal, the port 3 of toggle switch is connect
Ground, port 4 connects power supply, and port 4 connects the GPIO interface of CPLD.
The present embodiment can be in using connection jump cap expression between jump cap connection power supply pin and ground connection pin, two pin
Connection status, unpluging jump cap indicates in being not connected to state.
Second of hardware implementation mode includes the following steps:
S231: being arranged a logic sum gate circuit between external connector and CPLD, the input terminal of logic sum gate circuit with
External connector connection, the output end of logic sum gate circuit is connect with CPLD, and the input terminal of logic sum gate circuit includes at least
First input end and the second input terminal, wherein first input connect with the power supply pin of external connector, the second input terminal with outside
The ground connection pin connection of connecting connector.
The present embodiment obtains the connection status of the power supply pin and ground connection pin of external connector using logic sum gate circuit.
S232: it according to logic sum gate circuit first input end or the level state of the second input terminal, determines to be output
UART signal is SYS UART signal or BMC UART signal.
Specifically, according to the corresponding relationship of the different strobe states of logic sum gate circuit input end and signal to be output, step
There are two ways to determining UART signal to be output in rapid S232:
Method A:
Assuming that first input end is P3V3, the second input terminal is GND, when first input end is high level and the second input terminal
For low level, first input end is low level and the second input terminal is high level, alternatively, first input end and the second input terminal are equal
When for high level, determine that UART signal to be output is SYS UART signal；
When first input end and the second input terminal are low level, such as: it is emitted using jumping by first input end and second
After input terminal is shorted, determine that UART signal to be output is BMC UART signal.
Method B: when at least one high level in first input end and the second input terminal, UART letter to be output is determined
Number be BMC UART signal；
When first input end and the second input terminal are ground low level, such as: it is emitted using jumping by first input end and the
After two input terminals are shorted, determine that UART signal to be output is SYS UART signal.
By above step S131 and S132 and step S231 and S232 it is found that the link mode of OE2 is using hardware lines
The method on road carries out serial ports switching.Logic sum gate circuit can be used in hardware circuit, according to power supply pin in logic sum gate circuit and connects
The level of ground pin carries out the gating of UART signal, to realize that serial ports switches.
By above step S1 and S3 it is found that in the present embodiment control enable signal and multiple groups can be obtained by a CPLD
UART signal, and finally determine that UART to be output believes from multiple groups UART signal according to acquired control enable signal
Number, this method that Multi-serial port is automatically switched, compared with the prior art in manual switching, switching can be greatly improved
The flexibility of efficiency and switching.
With continued reference to Fig. 2 it is found that after determining UART signal to be output using CPLD, step S4 is executed: outside one
Connecting connector exports UART signal to be output.
By in this present embodiment in multiple serial ports, the UART signal to be output of CPLD output eventually by outside one in succession
Connect device and be connected to the end debug, can save more plate face spaces, reduce pcb board density, also help save material at
This.
Further, in this embodiment further including step S2 before step S3: to control enable signal and multiple groups
UART signal is filtered.By carrying out signal filtering, the extraordinary wave of control enable signal and UART signal can be effectively prevent
It is dynamic, to improve the accuracy of serial ports switching.
The method being filtered in the present embodiment to control enable signal acquired in CPLD and multiple groups UART signal, can
To use software filtering, this filtering method is conducive to save plate face space, and is easy to implement, to improve serial ports switching effect
Rate.Software filtering uses filtering method in the prior art, herein no longer superfluous detailed description.
Embodiment two
Referring to Fig. 5 on the basis of Fig. 2, Fig. 3 and embodiment illustrated in fig. 4, Fig. 5 is one provided by the embodiment of the present application
Kind realizes the structural schematic diagram of the system of Multi-serial port switching based on CPLD.As shown in Figure 5, it is realized in the present embodiment based on CPLD more
It include: signal acquisition module, signal determining module to be output and an external connector in the system of serial ports switching.Signal acquisition mould
Block and signal determining module to be output can realize that the input terminal of external connector and the output end of CPLD connect by a CPLD
It connects, the output end of external connector is connect with the end debug.
Wherein, signal acquisition module, for obtain control enable signal and in control terminal BMC UART module it is more
Group UART signal.UART module includes SYS UART module and BMC UART module, and SYS UART module issues SYS UART
Signal, BMC UART module issue BMC UART signal.
Signal determining module to be output, for being determined from multiple groups UART signal using CPLD according to control enable signal
UART signal to be output.
Further, according to the different acquisition modes of control enable signal, there are two types of structures for signal determining module to be output.
The first signal determining module to be output includes: BMC GPIO signal acquiring unit and determination unit.Wherein, BMC GPIO signal
For acquiring unit for obtaining the BMC GPIO signal from control terminal BMC, a BMC GPIO signal includes high level and low electricity
Put down two kinds of level states；Determination unit is used for the level state according to BMC GPIO signal, determines that UART signal to be output is
SYS UART signal or BMC UART signal, wherein two kinds of level states respectively with SYS UART signal and BMC UART signal
It matches one by one.
Second of signal determining module to be output includes: signal wire and signal behavior unit to be output.Wherein, signal wire is used
In connection external connector and CPLD, and at least provided with power supply pin and ground connection pin in external connector.Signal choosing to be output
Unit is selected, for the connection status according to the power supply pin of external connector and ground connection pin, determines that UART signal to be output is
SYS UART signal or BMC UART signal, wherein power supply pin is connected with ground connection pin and power supply pin and ground connection pin does not connect
Two states are connect, are matched one by one with SYS UART signal and BMC UART signal respectively.
Second of signal determining module to be output can also use a logic sum gate circuit and output signal determination unit.Its
In, the input terminal of logic sum gate circuit is connect with external connector, and the output end of logic sum gate circuit is connect with CPLD, and logic
OR circuit includes at least first input end and the second input terminal, wherein the first input and the power supply pin of external connector connect
It connects, the ground connection pin connection of the second input terminal and external connector.Output signal determination unit is used for according to logic sum gate circuit the
The level state of one input terminal and the second input terminal determines that UART signal to be output is that SYS UART signal or BMC UART believe
Number.
As shown in Figure 5, the system in the present embodiment further includes an external connector, for UART signal to be output
It is exported.
Further, in this embodiment further including filter module in the system based on CPLD realization Multi-serial port switching, it is used for
Control enable signal and multiple groups UART signal are filtered, to remove interference signal, avoid control enable signal and
The unusual fluctuations of multiple groups UART signal are conducive to the accuracy for further increasing serial ports switching.
The working principle and working method for realizing the system of Multi-serial port switching in the present embodiment based on CPLD, in Fig. 2-Fig. 4
Shown in embodiment one kind elaborated, between two embodiments can mutual reference, details are not described herein.
The application also provides a kind of board that Multi-serial port switching is realized based on CPLD, includes BMC and as above in the board
The system for realizing Multi-serial port switching based on CPLD.Wherein, include UART module in BMC, Multi-serial port is realized based on CPLD
Include one CPLD and external connector in the system of switching, again includes that signal acquisition module and signal to be output are true in CPLD
Cover half block.The board can obtain the control enable signal from BMC or hardware circuit, and obtain BMC by one CPLD of setting
The multiple groups UART signal of middle UART module, and according to acquired control enable signal, it is finally determined from multiple groups UART signal
UART signal to be output exports UART signal to be output finally by an external connector, to realize more
Automatic serial ports switching in the case of serial ports, and the flexible switching of serial ports, serial ports switching can be realized by software or hardware mode
Efficiency and switching flexibility it is high.Since the output end of CPLD in the board only connects an external connector, be conducive to save
The plate face space of board reduces board density.
The above is only the specific embodiment of the application, is made skilled artisans appreciate that or realizing this Shen
Please.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of method for realizing Multi-serial port switching based on CPLD, which is characterized in that the described method includes:
Obtain control enable signal and in control terminal BMC UART module multiple groups UART signal, the UART module packet
SYS UART module and BMC UART module are included, and the SYS UART module issues SYS UART signal, the BMC UART
Module issues BMC UART signal；
According to the control enable signal, UART signal to be output is determined from multiple groups UART signal using CPLD；
Using an external connector, the UART signal to be output is exported.
2. a kind of method for realizing Multi-serial port switching based on CPLD according to claim 1, which is characterized in that the basis
The control enable signal determines UART signal to be output using CPLD from multiple groups UART signal, comprising:
The BMC GPIO signal from control terminal BMC is obtained, a BMC GPIO signal includes high level and low level two
Kind level state；
According to the level state of the BMC GPIO signal, determine that UART signal to be output is SYS UART signal or BMC
UART signal, wherein two kinds of level states are matched with SYS UART signal and BMC UART signal one by one respectively.
3. a kind of method for realizing Multi-serial port switching based on CPLD according to claim 1, which is characterized in that the basis
The control enable signal determines UART signal to be output using CPLD from multiple groups UART signal, comprising:
The external connector and CPLD are connected with signal wire, and at least provided with power supply pin and is connect in the external connector
Ground pin；
CPLD determines that UART signal to be output is SYS according to the connection status of the power supply pin and ground connection pin of external connector
UART signal or BMC UART signal, wherein power supply pin is connected with ground connection pin and power supply pin and ground connection pin is not connected to two
Kind state, matches with SYS UART signal and BMC UART signal one by one respectively.
4. a kind of method for realizing Multi-serial port switching based on CPLD according to claim 1, which is characterized in that the basis
The control enable signal determines UART signal to be output using CPLD from multiple groups UART signal, comprising:
One logic sum gate circuit is set between the external connector and CPLD, the input terminal of the logic sum gate circuit and outer
Connecting connector connection, the output end of the logic sum gate circuit is connect with CPLD, and the input terminal of the logic sum gate circuit is extremely
It less include first input end and the second input terminal, wherein the first input is connect with the power supply pin of external connector, the second input
End is connect with the ground connection pin of external connector；
CPLD determines UART signal to be output according to the level state of logic sum gate circuit first input end and the second input terminal
For SYS UART signal or BMC UART signal.
5. a kind of method for realizing Multi-serial port switching based on CPLD according to any one of claims 1-4, which is characterized in that
According to the control enable signal, using CPLD before determining UART signal to be output in multiple groups UART signal, the side
Method further include:
The control enable signal and multiple groups UART signal are filtered.
6. a kind of system for realizing Multi-serial port switching based on CPLD, which is characterized in that the system comprises:
Signal acquisition module, for obtain control enable signal and in control terminal BMC UART module multiple groups UART letter
Number, the UART module includes SYS UART module and BMC UART module, and the SYS UART module issues SYS UART
Signal, the BMC UART module issue BMC UART signal；
Signal determining module to be output, for being determined from multiple groups UART signal using CPLD according to the control enable signal
UART signal to be output；
One external connector, for being exported to the UART signal to be output, and the input terminal of the external connector
It is connect with the output end of CPLD, the output end of the external connector is connect with the end debug.
7. according to a kind of system for realizing Multi-serial port switching based on CPLD as claimed in claim 6, which is characterized in that described to be output
Signal determining module includes:
BMC GPIO signal acquiring unit, for obtaining the BMC GPIO signal from control terminal BMC, a BMC GPIO
Signal includes two kinds of level states of high level and low level；
Determination unit determines that UART signal to be output is SYS for the level state according to the BMC GPIO signal
UART signal or BMC UART signal, wherein two kinds of level states respectively with SYS UART signal and BMC UART signal one by one
Matching.
8. according to a kind of system for realizing Multi-serial port switching based on CPLD as claimed in claim 6, which is characterized in that described to be output
Signal determining module includes: signal wire and signal behavior unit to be output；
The signal wire connects the external connector and CPLD, and in the external connector at least provided with power supply pin and
It is grounded pin；
The signal behavior unit to be output, for the connection status according to the power supply pin of external connector and ground connection pin, really
Fixed UART signal to be output is SYS UART signal or BMC UART signal, and wherein power supply pin is connected with ground connection pin, and
Power supply pin and ground connection pin are not connected to two states, match one by one with SYS UART signal and BMC UART signal respectively.
9. according to a kind of system for realizing Multi-serial port switching based on CPLD as claimed in claim 6, which is characterized in that in the system
Further include: filter module, for being filtered to the control enable signal and multiple groups UART signal.
10. a kind of board for realizing Multi-serial port switching based on CPLD, which is characterized in that the board includes: that BMC and right are wanted
Any system that Multi-serial port switching is realized based on CPLD in 6-9 is sought, and includes UART module in the BMC.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078603A (en) * | 2019-10-30 | 2020-04-28 | 苏州浪潮智能科技有限公司 | Method and system for controlling access of internal serial port of multi-node equipment |
| CN113094316A (en) * | 2021-04-01 | 2021-07-09 | 浪潮电子信息产业股份有限公司 | Online switching device and method of NCSI (non-volatile memory) signals |
| CN114866424A (en) * | 2022-07-08 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Server management method, device, system, electronic equipment and readable storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281254A (en) * | 2010-06-10 | 2011-12-14 | 鸿富锦精密工业（深圳）有限公司 | Design system and method of server serial port |
| CN104102614A (en) * | 2014-08-04 | 2014-10-15 | 浪潮(北京)电子信息产业有限公司 | Server serial port output method and server serial port output device |
| CN106339344A (en) * | 2016-08-18 | 2017-01-18 | 浪潮(北京)电子信息产业有限公司 | Multi-serial port switching system and method used for debugging server system |
| CN107678988A (en) * | 2017-09-08 | 2018-02-09 | 郑州云海信息技术有限公司 | A kind of multifunctional serial port device and implementation method |
| CN109684216A (en) * | 2018-12-25 | 2019-04-26 | 郑州云海信息技术有限公司 | A kind of commissioning device and electronic equipment |
-
2019
- 2019-06-17 CN CN201910520642.7A patent/CN110362525B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281254A (en) * | 2010-06-10 | 2011-12-14 | 鸿富锦精密工业（深圳）有限公司 | Design system and method of server serial port |
| CN104102614A (en) * | 2014-08-04 | 2014-10-15 | 浪潮(北京)电子信息产业有限公司 | Server serial port output method and server serial port output device |
| CN106339344A (en) * | 2016-08-18 | 2017-01-18 | 浪潮(北京)电子信息产业有限公司 | Multi-serial port switching system and method used for debugging server system |
| CN107678988A (en) * | 2017-09-08 | 2018-02-09 | 郑州云海信息技术有限公司 | A kind of multifunctional serial port device and implementation method |
| CN109684216A (en) * | 2018-12-25 | 2019-04-26 | 郑州云海信息技术有限公司 | A kind of commissioning device and electronic equipment |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111078603A (en) * | 2019-10-30 | 2020-04-28 | 苏州浪潮智能科技有限公司 | Method and system for controlling access of internal serial port of multi-node equipment |
| CN111078603B (en) * | 2019-10-30 | 2021-08-20 | 苏州浪潮智能科技有限公司 | Method and system for controlling access of internal serial port of multi-node equipment |
| CN113094316A (en) * | 2021-04-01 | 2021-07-09 | 浪潮电子信息产业股份有限公司 | Online switching device and method of NCSI (non-volatile memory) signals |
| CN114866424A (en) * | 2022-07-08 | 2022-08-05 | 苏州浪潮智能科技有限公司 | Server management method, device, system, electronic equipment and readable storage medium |
| CN114866424B (en) * | 2022-07-08 | 2022-11-18 | 苏州浪潮智能科技有限公司 | Server management method, device, system, electronic equipment and readable storage medium |
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