CN206162523U - Production domesticization signal processing platform - Google Patents

Abstract

The utility model discloses a production domesticization signal processing platform, insert processing card, homemade CPU mainboard and storage card including L wave band frequency conversion module, intermediate frequency signal, intermediate frequency signal inserts processing card and includes AD module, DA module and signal processing module, L wave band frequency conversion module electricity simultaneously is connected with the AD module with the DA module, signal processing module simultaneously with the AD module with DA module electricity is connected, signal processing module with homemade CPU mainboard electricity is connected, homemade CPU mainboard electricity is connected with the storage card. The utility model belongs to completely independent development has good compatibility between the device, the problem that the device was restricted the purchase can not appear, and the wholeness can be good, can realize functions such as the receipt of radio signal (satellite, microwave, radar etc. ), collection, processing, storage, with good extensibility.

Description

Production domesticization signal processing platform

Technical field

The utility model belongs to signal processing technology field, and in particular to one kind production domesticization signal processing platform.

Background technology

The core device that the signal processing platform equipment in the fields such as national defence, military project, national information safety is used is applied at present Part is essentially all external product, and with certain risk, one is the possibility that external device leaves back door, and two is non- Often period, some Primary Components can be by restriction buying.Because multiple functional modules of signal processing platform need collaboration to process letter The device of number, domestic device and foreign countries is implicitly present in gap in performance, if simply replacing part of devices, meeting There is unmatched problem between device.

Utility model content

The purpose of this utility model is that and provide a kind of production domesticization signal processing platform in order to solve the above problems.

The utility model is achieved through the following technical solutions above-mentioned purpose：

One kind production domesticization signal processing platform, including L-band frequency-variable module, intermediate-freuqncy signal access process card, domestic CPU master Plate and storage card, the intermediate-freuqncy signal accesses to process to block includes A/D module, D/A module and signal processing module, and the L-band becomes Frequency module is electrically connected with the A/D module and the D/A module simultaneously, the signal processing module simultaneously with the A/D module and institute D/A module electrical connection is stated, the signal processing module is electrically connected with the domestic cpu motherboard, the domestic cpu motherboard electrical connection There is the storage card.

Specifically, the signal processing module includes two panels storage chip, three FMC connectors, flash card, PCI PHY Chip, CPCI connectors, two panels FPGA signal processing chip and FPGA management control chip, FPGA signal transactings core described in two panels The model of piece and FPGA management control chips is SMQ4VSX55, wherein a piece of FPGA signal processing chips are simultaneously Electrically connect with the wherein a piece of storage chip, FMC connectors described in FMC connectors and second described in first, in addition a piece of institute State FPGA signal processing chips to connect with the other a piece of storage chip, FMC connectors and FMC described in the 3rd described in second simultaneously Plug-in unit is electrically connected, FPGA management control chip simultaneously with FMC connectors, the flash card and the PCI described in second PHY chip is electrically connected, and the PCI PHY chips are electrically connected with the CPCI connectors, and the CPCI connectors are domestic with described Cpu motherboard is electrically connected, and the A/D module and the D/A module correspond to access on one of them described FMC connector respectively, two panels Data interconnection passage between piece is provided between the FPGA signal processing chips, FPGA signal processing chips described in two panels with it is described Data interconnection passage between piece is provided between FPGA management control chips, the FPGA is managed described in control chip and two panels Configuration file passage is provided between FPGA signal processing chips.

In order to signal transacting expanded function, FPGA signal processing chips have been electrically connected a piece of described in two panels Serial conversion chip, per serial conversion chip described in piece ZD high speed connectors are electrically connected with.

Preferably, the storage card is disk array.

The beneficial effects of the utility model are：

The utility model belongs to entirely autonomous research and development, has good compatibility between device, is not in that device is limited The problem of system buying, overall performance is good, be capable of achieving the reception to wireless signal (satellite, microwave, radar etc.), collection, process, The functions such as storage, are with good expansibility.

Description of the drawings

Fig. 1 is the structured flowchart of production domesticization signal processing platform described in the utility model；

Fig. 2 is the structured flowchart of signal processing module described in the utility model.

Specific embodiment

Below in conjunction with the accompanying drawings the utility model is described in further detail：

As depicted in figs. 1 and 2, the utility model includes that L-band frequency-variable module, intermediate-freuqncy signal access process card, domestic CPU Mainboard and storage card, intermediate-freuqncy signal accesses to process to block includes A/D module, D/A module and signal processing module, L-band frequency-variable module Simultaneously A/D module and D/A module are electrically connected with, signal processing module is electrically connected with A/D module and D/A module simultaneously, signal transacting mould Block is electrically connected with domestic cpu motherboard, and domestic cpu motherboard is electrically connected with storage card, and here storage card is disk array, with enough Big memory capacity.

Signal processing module includes that two panels storage chip, three FMC connectors, flash card, PCI PHY chips, CPCI connect Connect device, two panels FPGA signal processing chip and FPGA management control chip, two panels FPGA signal processing chip and FPGA management controls The model of coremaking piece is SMQ4VSX55, wherein a piece of FPGA signal processing chips simultaneously with wherein a piece of storage chip, first FMC connectors and the 2nd FMC connectors are electrically connected, in addition a piece of FPGA signal processing chips simultaneously with other a piece of storage core The electrical connection of piece, the 2nd FMC connectors and the 3rd FMC connectors, FPGA management control chip simultaneously with the 2nd FMC connectors, dodge Card and the electrical connection of PCI PHY chips are deposited, PCI PHY chips electrically connect with CPCI connectors, CPCI connectors and domestic cpu motherboard Electrical connection, A/D module and D/A module correspond to access on one of FMC connectors, between two panels FPGA signal processing chip respectively Data interconnection passage between piece is provided with, is provided between piece between two panels FPGA signal processing chip and FPGA management control chips Data interconnection passage, between FPGA management control chips and two panels FPGA signal processing chip configuration file passage is provided with.

Two panels FPGA signal processing chip has been electrically connected a piece of serial conversion chip, and every serial conversion chip is electric ZD high speed connectors are connected with, such that it is able to realize being interconnected between signal-processing board, the extension of signal processing function is carried out.

Components and parts are domestics in presents, and the model specification of each components and parts is as follows：

Production domesticization signal processing platform described in the utility model adopts cpci bus, from the CPCI cabinets of the grooves of 2U 4, base Plinth platform accesses process card (being responsible for signal main process task) comprising 1 production domesticization intermediate-freuqncy signal and 1 domestic cpu motherboard (is responsible for flat Platform is controlled), while A/D module and D/A module that production domesticization is also carried on the intermediate-freuqncy signal access process card that domesticizes (are responsible for signal to connect Enter collection).Further, since platform also tests the demodulation decoding application for carrying out satellite communication signals, will also production domesticization be carried L-band frequency-variable module, with signal frequency down-conversion function.

Production domesticization signal processing platform can complete collection and the preprocessing function of signal, replaceable A/D module and DA moulds Block, realizes single channel or multi pass acquisition, can cover below 200MSps sample rates；Veneer provides 2 domestic FPGA signal transactings cores Piece, resource equivalent to Xilinx companies XC4VSX55, and can by way of many plates are cascaded extension process resource；FPGA resource It is reconfigurable, it is capable of achieving application reconstruct；Domestic cpu motherboard is provided, can be controlled, be shown and the application such as simple algorithm.

The main composition of domestic L frequency ranges frequency-variable module is to rise the L frequency range frequency conversion chips of electronics cooperation research and development with Chengdu state.Make The L frequency range down conversion modules developed with the chip, volume, power consumption advantages are projected very much, by ambient noise, the spuious and bit error rate The Comprehensive Correlation test of the indexs such as performance, under identical operating frequency and gain condition, the frequency conversion mould designed using the chip Block is suitable with existing equipment frequency-variable module performance, has been provided with application possibility.

At present most significant end A/D chip in the country's is mainly in 100MSps～200MSps, 12-bit～16-bit sampling precisions, 1.5GSps and with up-sample A/D chip also have.Research institute and manufacturer mainly have middle electric 24 institute, middle electric 58 Institute, Microelectronics Institute of the Chinese Academy of Sciences, Beijing Xin Fengkuantai companies etc., it is on probation for project team's assessment that above unit is each provided with AD prints. But on the whole the index such as the SFDR of domestic A/D chip, SNR, power consumption and highest sample rate compares same kind of products at abroad and also has one Determine gap.

The ADC1002 chips that collection subcard is developed using Beijing Xin Fengkuantai companies, the nominal index of its official is as follows：

A) port number：1；

A) highest sample rate：200MSps；

B) sampling precision：12bit；

C) power consumption：790mW；

d)SNR：63.6dB (representative value)；

e)SFDR：83.5dB (representative value).

Production domesticization intermediate-freuqncy signal is accessed and processes the signal transacting that card completes intermediate-freuqncy signal access output and correlation, its signal The concrete structure of processing module has been described above in the above, and the card veneer employs 3 fpga chips as master chip, type selecting For the micro- SMQ4VSX55 of state, relative to the SMQV6000 that previous generation is used, logical resource (SLICE, DFF, LUT) SMQV6000's 1.5 times, DSP core is 2 times of SMQV6000.

3 FPGA wherein two panels on plate is connected with FMC subcards, is also that user is carried out as the master chip of signal transacting The master chip of secondary development.3rd FPGA as management control chip, complete to the management of two panels signal processing chip control, Status monitoring, configuration distributing and the data transmit-receive with two panels signal processing chip.The program independent development of the 3rd FPGA is simultaneously Solidification, provides a user with interface definition and sequential, and the communication protocol of data interaction.

Signal is accessed and processes the DDR2SDRAM storages that card provides 4Gb*4=16Gb, and data storage bandwidth is up to 20Gbps. Veneer externally provides CPCI standard interfaces, while providing 8 pairs of 2.0Gbps high speeds Serdes interfaces and other interfaces；Veneer provides 3 Individual FMC slots, each slot provides sufficient LVDS interface, and FMC slots may be inserted into double channel A/D subcard, single channel AD/DA The optical module subcard of two-way single channel subcard, two-way 2.5G*4=10G

Based on hardware above framework, intermediate-freuqncy signal accesses process card can possess various operational modules, realize different work( Can, mainly have following several：

Collection memory module (snap shot)：FPGA is left intact to the data that AD is input into, and selects arbitrary port number According to, mainboard is sent to by pci interface, hard disk array is stored in, because homemade chip does not also possess high speed Serdes interface, place The bus (RAPIDIO, PCIE) of high bandwidth cannot be set up between reason plate and mainboard, process pci bus between card and mainboard into For the bandwidth bottleneck of data transfer, 33M*32=1Gbit/s is can only achieve, it is impossible to realize that real-time continuous are stored, therefore current Store function is gathered under version can only realize that data storage is first entered DDR2 chips by snapshot mode, i.e. FPGA, after DD2 storages are full again Hard disk is stored at relatively lower speeds, storage can be carried out several times, the data volume that can store about 16Gb is performed every time.For The data of storage, user can carry out application and development on single board computer directly on mainboard, it is also possible to by mainboard LAN interface reads remote data exploitation.

Data processing mode：If the insertion of FMC slots for double channel A/D card, FPGA digital intermediate frequency signal is carried out DDC, Demodulation, decoding, final output baseband signal sends mainboard to and is stored by pci interface；If the insertion of FMC slots is Single channel bidirectional AD/DA subcards, FPGA is in addition to completing DDC and demodulation coding, in addition it is also necessary to complete reverse digital mixing and Modulation, coding.

In function distribution, two panels FPGA can be selected at symmetric pattern, the i.e. base band of complete independently correspondence FMC subcards Reason, two panels FPGA is configured to the same program；Cascade mode can also be selected, i.e., DDC is completed by first piece FPGA (left side), by Two complete demodulation decoding, and baseband signal are sent to into pci bus on management control chip.

Process mode of extension：If the disposal ability of two panels FPGA is not enough in this plate, may be inserted into polylith and process card, by it The FPGA of his board carries out association's process, is interconnected by backboard, processes the bandwidth for possessing two-way 8G between board.If user is not required to This pattern is provided, the transceiver chips processed on card are not welded, reduce system cost.

Pattern is swept soon：FPGA carries out FFT calculating to the data for accessing, and the spectrum results for obtaining are sent to mainboard by pci bus, User can remotely develop software on mainboard or by LAN interface, and graphic interface shows the spectral characteristic for accessing signal.

Mould adopts pattern：According to resulting access signal spectrum information is swept soon, DDC, demodulation, decoding are carried out to characteristic spectra Obtain baseband signal.

Intermediate-freuqncy signal accesses and processes card and be between chip and chip, between chip and FMC subcards, and board and board it Between reserved the interconnecting interface of abundance, above all of operational module can be on the premise of hardware platform be motionless by configuring The program of two panels signal processing main chip FPGA is achieved, and the secondary development for user provides flexibly easily platform.

Domestic cpu motherboard adopts the Godson 3A processors of section in Godson.Carry the main control card of Godson 3A processors relatively For maturation, the exploitation debugging of early stage and operating system work on probation are completed on the board.Using being equipped with Godson 3A process The Ace of device Godson 6U CPCI mainboard ALX-13A.

The hardware block diagram of the upper figure mainboard of correspondence, storage card can adopt both of which, and the first is directly and South Bridge chip Output is connected on the docking of the SATAx3 on J3, and three pieces of hard disks are hung on a memory card；Second pattern is to be connected with north bridge chips Pciex8 is docked, and on a memory card using RAID array chip, pcie interface conversions is constituted into disk battle array into multiplex SATA interface Row.The bandwidth for being limited to process pci bus between card and mainboard is limited, and two kinds of storage cards can meet requirement.

Preferred embodiment of the present utility model is these are only, it is all in this practicality not to limit the utility model Any modification, equivalent and improvement made within new spirit and principle etc., should be included in guarantor of the present utility model In the range of shield.

Claims (4)

1. a kind of production domesticization signal processing platform, it is characterised in that：Block including L-band frequency-variable module, intermediate-freuqncy signal access process, Domestic cpu motherboard and storage card, the intermediate-freuqncy signal accesses to process to block includes A/D module, D/A module and signal processing module, institute L-band frequency-variable module is stated while being electrically connected with the A/D module and the D/A module, the signal processing module simultaneously with it is described A/D module and the D/A module are electrically connected, and the signal processing module is electrically connected with the domestic cpu motherboard, the domestic CPU Mainboard is electrically connected with the storage card.

2. production domesticization signal processing platform according to claim 1, it is characterised in that：The signal processing module includes two Piece storage chip, three FMC connectors, flash card, PCI PHY chips, CPCI connectors, two panels FPGA signal processing chip and FPGA manages the model of control chip, FPGA signal processing chips described in two panels and FPGA management control chips and is SMQ4VSX55, wherein a piece of FPGA signal processing chips simultaneously with the wherein a piece of storage chip, FMC described in first FMC connectors electrical connection described in connector and second, in addition a piece of FPGA signal processing chips simultaneously with other a piece of institute State storage chip, FMC connectors described in second and FMC connectors described in the 3rd are electrically connected, the FPGA management control chip is same When electrically connect with FMC connectors, the flash card and the PCI PHY chips described in second, the PCI PHY chips with it is described CPCI connectors are electrically connected, and the CPCI connectors electrically connect with the domestic cpu motherboard, the A/D module and the D/A module Correspond to respectively and access on one of them described FMC connector, be provided with number between piece described in two panels between FPGA signal processing chips According to interconnecting channels, between FPGA signal processing chips described in two panels and the FPGA management control chips data between piece are provided with Interconnecting channels, the FPGA manages control chip and is provided with configuration file described in two panels between FPGA signal processing chips and leads to Road.

3. production domesticization signal processing platform according to claim 2, it is characterised in that：FPGA signal transactings core described in two panels Piece has been electrically connected a piece of serial conversion chip, and per serial conversion chip described in piece ZD high speed connectors are electrically connected with.

4. production domesticization signal processing platform according to claim 1, it is characterised in that：The storage card is disk array.