CN203434991U - GSMR-R network interference signal acquisition and processing device - Google Patents

Abstract

The utility model relates to the wireless communication field, in particular to a multi-processor-based embedded GSMR-R network interference signal acquisition and processing device. The multi-processor-based embedded GSMR-R network interference signal acquisition and processing device includes a processor, a power supply module, an AD data acquisition module, a data and program storage module, a remote data transmission module, a data backup module, a reset module, an auxiliary and expanded interface module, and an interrupt management module; the AD data acquisition module converts intermediate-frequency analog signals of a GSM-R uplink frequency band and a GSM-R downlink frequency band into digital signals and transmits the digital signals to a DSP core of the processor, wherein the analog signals of the GSM-R uplink frequency band and the GSM-R downlink frequency band are acquired in a real-time manner; after calculating and processing the digital signals, the DSP core stores the processed digital signals in a DDR2 chip of the data and program storage module through a data line, and at the same time, stores the processed digital signals in a large-capacity hard disk through a SATA connector; when the acquired data are abnormal, the AD data acquisition module starts intermediate-frequency analog signals of an abnormal frequency band of the acquired data, and communicates with a host computer through an Ethernet transceiver.

Description

GSM-R network interferences signals collecting and processing unit

Technical field

The utility model relates to field of wireless communication, relates in particular to a kind of based on the Embedded GSM-R network interferences of multiprocessor signal acquiring and processing system.

Background technology

Along with the develop rapidly of mobile communication technology, GSM-R dedicated mobile communications subsystem is being played the part of more and more important role in Leap-forward Development of Railway, yet along with electromagnetic environment becomes increasingly complex, interference problem is more and more subject to people's attention.Different from public mobile communication system GSM is, and it requires system to have the safe operation that higher reliability and QoS ensure train, so GSM-R network interferences signals collecting and processing have occupied considerable position.Yet for the GSM-R network interferences signal acquiring and processing system that adopts uniprocessor to realize, its hardware resource is limited, can not be real-time to a large amount of interfering datas of GSM-R network gather, process, the operation such as storage, can not respond in time the request of the remote data transmission of Ethernet, cause promptly and accurately to interference source, positioning, make network have potential safety hazard, so the mode of uniprocessor is difficult to meet the real-time of GSM-R network interferences signal acquiring and processing system and the requirement of accuracy.

Utility model content

In order to solve the problems of the technologies described above, it is a kind of based on the embedded GSM-R network interferences of multiprocessor signal acquiring and processing system that the utility model object is to provide, can be real-time to a large amount of interfering datas of GSM-R network gather, process, store, the operation such as transmission, for interference source is positioned promptly and accurately, guarantee that GSM-R network security reliably provides hardware platform.

The technical scheme that the utility model adopts is: a kind ofly based on the embedded GSM-R network interferences of multiprocessor signal acquiring and processing system, comprise processor, power module, AD data acquisition module, data and program storage block, remote data transmission module, data backup module, reseting module, auxiliary and expansion connection module and interrupt management module, described AD data acquisition module has three circuit-switched data acquisition channels, be respectively used to gather GSM-R uplink band, band downlink, and abnormal signal frequency range, every circuit-switched data passage is by AD sampling input front end modulate circuit, AD sample conversion circuit and processor connect to form, described data and program storage block are by flash chip, DDR2 chip and processor connect and compose, flash chip is used for storing bsp driver, boot and kernel program, DDR2 chip is for the spatial cache of the digital signal as the output of AD data acquisition module, and move interim memory space is provided for program, described remote data transmission module is connected to form by ethernet transceiver and processor, described data backup module is connected to form by SATA connector, clock generator and processor, for recording the Monitoring Data of having analyzed with storage of processor, waits for that control centre transfers at any time, power module is processor, AD data acquisition module, data and program storage block, remote data transmission module, data backup module, reseting module, assist and expansion connection module, and interrupt management module provides work required voltage, AD data acquisition module converts the analog intermediate frequency signal of the GSM-R uplink band of Real-time Collection and band downlink to digital signal and is sent to the DSP kernel in processor, after DSP kernel calculation process, by data wire, deposit in the DDR2 chip in data and program storage block, by SATA connector, deposit big capacity hard disk in simultaneously, when image data is abnormal, AD data acquisition module starts the analog intermediate frequency signal of the abnormal frequency range of collection signal, and by ethernet transceiver and upper machine communication.

Described power module comprises digital power and analog power two parts: digital power is by input filter network, panel switches, power management chip and output filtering network form, plate external power provides operating voltage through panel switches for power management chip after input filter network filtering, the output voltage of power management chip partly provides voltage through output filtering network for digital circuit, analog power is by input filter network, Voltage stabilizing module, output filtering network forms, the input of plate external power is as the input of input filter network, the output of input filter network is as the input of Voltage stabilizing module, the output of Voltage stabilizing module is connected to the input of output filtering network, the output voltage of last output filtering network is supplied with for artificial circuit part provides voltage.

Described AD sampling input front end modulate circuit adopts operational amplifier, and analog intermediate frequency signal enters operational amplifier adjustment, described AD sample conversion circuit is connected to form by AD conversion chip and CPLD chip and processor, the output of No. three amplifiers is connected with AD conversion chip San road Gather and input passage, the string of AD conversion chip pattern are controlled pin PAR/SER and HW/SW pin is set to low level, realize the signals collecting under parallel schema, the data/address bus of AD conversion chip is connected to the EMIFA data terminal EMA_D[0:15 of processor], realize the output of digital conversion results, the CPLD chip being connected with EMIFA data terminal is mainly used in carrying out address decoding simultaneously, operation peripheral hardware, interrupt source is distributed, the logic controls such as multiplexer gating, the CONVST_A of CPLD chip and AD conversion chip, CONVST_B, CONVST_C is connected, control the channel selecting of AD conversion chip, the chip selection signal CS/FS that AD transforms chip is also connected with CPLD chip, control the gating of AD conversion chip, AD transforms chip BUSY/INT interrupt signal and through CPLD, outputs to the GP2[0 of processor] mouthful, when image data is abnormal, trigger interrupt signal BUSY/INT, the control of realization to intermediate frequency collection of simulant signal,

The data wire of described data and the flash chip in program storage block and DDR2 chip is connected with address wire with the data wire of processor respectively with address wire, flash chip and DDR2 chip enable and control signal is connected with processor; The read signal pin of flash chip and the enable pin of reading of processor are connected; The read-write enable pin of DDR2 chip is directly connected with the read-write enable pin of processor; The chip selection signal of flash chip and DDR2 chip is connected with DDR_CS with the CS3 of processor respectively.

Described remote data transmission module is connected by the input of ethernet transceiver and the RMII interface of processor, and ethernet transceiver output is connected with Ethernet socket RJ45, and finally the host computer by optical cable and control centre carries out data, command transfer.

The annexation of described data backup module is, the SATA transfer of data pin SATA_TXP of processor, SATA_TXN, SATA_RXN, SATA_RXP are connected with transfer of data pin SATA_TXP, SATA_TXN, SATA_RXN, the SATA_RXP of SATA interface respectively, realize the access of data; Output pin OUTN, the OUTP of clock generator is connected with SATA reference clock pin SATA_REF_CLKN, the SATA_REF_CLKP of processor respectively, for the SATA interface data transmission of processor provides reference difference clock.

Described reseting module is by the reset chip with house dog and low-voltage detection function, and three inputs form with door; The dog pulse of feeding of reset chip is produced by CPLD chip internal CPLD clock division, be used for activating watchdog function, the external reference voltage of PFI pin of reset chip, this reference voltage is realized low-voltage detection function as the reference voltage of reset chip inside low pressure comparator, and the low pressure of reset chip detects output pin PFO and is connected with the NMI pin of processor; Three inputs with door input respectively with the reset output terminal DSP_RSTOUT of processor, the reset output terminal RESET of reset chip, and external resetting voltage is connected, three inputs are connected with the output of door and the reseting pin of peripheral hardware, realize processor reset, low pressure detects and resets and manual reset.

Described auxiliary and expansion connection module comprises: (1) MMC/SD card interface, and the output pin of the MMCSD0 controller by processor inside is connected with MMC/SD card connector, assists SATA interface hard disk to back up part Monitoring Data; (2) 4 road RS232 interfaces, wherein three tunnels are connected with the input of the serial port extended chip of 1 expansion 3 by the output pin of the UART1 controller of processor inside, and provide control signal by processor, the output of the serial port extended chip of 1 expansion 3 is connected with the input of RS232 transceiver, and the output of RS232 transceiver is connected with three RS232 connectors; The output pin of UART2 controller of processor inside of leading up to is in addition connected with RS232 transceiver input, RS232 transceiver output is connected with RS232 connector, ARM9 kernel in auxiliary processor is debugged, or external demodulated equipment obtains base station cell parameter and carries out interference source location; (3) USB-A and USB-mini interface, be connected with USB-mini connector with USB-A by the USB1.1OHCI of processor inside and the output pin of USB2.0OTG controller respectively, realizes the demodulated equipment of circumscribed USB interface shape; (4) 2 JATG interfaces, the JATG interface pin by processor and CPLD chip is directly connected with JATG connector respectively, realizes the on-line debugging of processor and CPLD and program are downloaded; (5) 100 pin extensive interfaces, the expansion pin by processor and CPLD chip can directly be connected by expansion connector with 100 pin, expands this apparatus function and realizes upgrading.

Described interrupt management module is connected and composed by CPLD chip XC9572XL and processor, annexation be external interrupt signal INT0, INT1, INT2, INT3, CNTL0, CNTL1 by CPLD chip XC9572XL respectively with the GP8[12 of processor], GP8[15], GP8[13], GP8[14], GP6[2], GP6[4] be connected, realize the management of interrupt source.

The low power processor OMAP-L138 of processor adopting TI company based on Leonardo da Vinci's framework, the asymmetric coenocytism that uses DSP to be combined with ARM, it comprises the ARM9 kernel of a dominant frequency 300M and the C6748DSP kernel of a 300M, between DSP and ARM, by DSPLINK, carries out exchanges data.

Described AD conversion chip adopts ADS8556, and CPLD chip adopts XC95144XL.

Operation principle of the present utility model: this system needs the Real-time Collection monitoring up 885～889MHz frequency range of GSM-R and the descending 930～934MHz frequency range of GSM-R; acquisition scans 137～960MHz frequency range when discovery signals is abnormal; search abnormal base station signal; provide and disturb source base station information, report control centre.Three groups of acquisition channels of AD data acquisition module are connected with the radio-frequency front-end that receives above three frequency band signals respectively, by the data conversion storage collecting in data storage module, then in the DSP in processor, check the GSM-R up-downgoing intermediate-freuqncy signal frequency spectrum of collection and the GSM-R template signal spectral contrast in database, when discovery signals is abnormal, prove that signal is interfered, acquisition scans 137～960MHz frequency range immediately, by processor analysis, search abnormal base station signal, to producing the GSM-R of interference signal, GSM, CDMA, UMTS(Guangdong and Shenzhen area) etc. system base-station message decode, obtain base station IDs, operator's coding, carrier wave configuration and bcch carrier intensity, identify Frequency Hopping Signal, obtain frequency set and the frequency hopping rate information of Frequency Hopping Signal, judgement interference type (the same frequency of GSM-R or adjacent frequency interference, GSM intermodulation, the outer interference of CDMA band, frequency hopping interference, bursty interference, noise jamming, not clear interference etc.), by Ethernet, report in time control centre's host computer, the real-time interference monitoring result of host computer integrated treatment, and according to interference type and intensity, location interference source on electronic chart, can link with existing monitoring and positioning system, eliminate and disturb.Or by manual coordination, guarantee the safe operation of GRM-R network.

Beneficial effect:

(1) this system adopts the low power processor OMAP-L138 with the asymmetric coenocytism that DSP is combined with ARM, it comprises the ARM9 kernel of a dominant frequency 300M and the C6748DSP kernel of a 300M, DSP kernel is mainly responsible for data acquisition, GSM-R network interferences detection algorithm etc., ARM9 kernel is mainly responsible for data backup, network data transmission, the functions such as system reset, internuclearly in DSP kernel and ARM9 by DSPLINK, carry out exchanges data, the utility model can well meet the real-time of GSM-R network interferences signal acquiring and processing system and the requirement of accuracy by the collaborative work of DSP kernel and ARM9 kernel, saved development cost, accelerated the construction cycle.(2) adopt 16,6 tunnel SAR AD conversion chip, there is real bipolar input .Mei road and comprised sample-and-hold circuit, allow to carry out high-speed, multi-path signals collecting, support the data acquisition rate of parallel interface pattern up to 630kSPS, guaranteed precision and the efficiency of Interference Detection; Therefore the intermediate-freuqncy signal that no matter above three frequency ranges are exported is the I of zero intermediate frequency, Q orthogonal signalling, or non-zero if signal can gather by this AD conversion chip.(3) adopt special power management chip and filter network.This with the power supply of 1117A, the common power conversion chip designs such as 7805, compare, power work efficiency is higher, and has less output voltage ripple, makes the more stable of system operation.(4) in the design, add CPLD chip to be mainly used in carrying out address decoding, operation peripheral hardware, interrupt source is distributed, the logic controls such as multiplexer gating; The part of control AD data acquisition module etc. is controlled and enable signal; Carry out the processing of interrupting between processor and peripheral hardware.Greatly alleviate the operating pressure of processor, improved operating efficiency and the flexibility of this system.(5) adopt the serial port extended chip of 1 expansion 3 standard serial port of a full duplex can be extended to 3 standard serial ports, solved the few shortcoming of processor serial port resource, can connect the cell parameter that more demodulated equipment obtains interference source, thereby more accurately to interference source target localization.(6) adopt the reset chip with house dog and low-voltage detection function, this compares with the reset chip only with watchdog function, voltage condition that can measurement processor, in good time reset operation, the stability of assurance system of carrying out.(7) circuit board of the present utility model adopts six laminate designs, and laminated construction is top layer, stratum, interior signals layer 1, interior signals layer 2, bus plane, bottom; It is reference planes that all signals layers of this laminated construction can find stratum and bus plane, and very applicable high-speed PCB design makes this system have good stability; Board area size is 100x100 millimeter, and key network and signal in circuit board are equipped with test point, makes system have the advantages such as little, the easy installation of volume, easy debugging.

Accompanying drawing explanation

Fig. 1 is the general frame of the related GSM-R network interferences signal acquiring and processing system of the utility model.

Fig. 2 is the design principle block diagram of the related power module of the utility model.

Fig. 3 is the design principle block diagram of the related AD data acquisition module of the utility model.

Fig. 4 is the design principle block diagram of the related data of the utility model and program storage block

Fig. 5 is the design principle block diagram of the related remote data transmission module of the utility model

Fig. 6 is the design principle block diagram of the related data backup module of the utility model

Fig. 7 is the design principle block diagram of the related reseting module of the utility model

Fig. 8 is the design principle block diagram of the related auxiliary and expansion connection module of the utility model

Fig. 9 is the design principle block diagram of the related interrupt management module of the utility model

Figure 10 is the related interference identification process figure of the utility model

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail:

Of the present utility model based on the Embedded GSM-R network interferences of multiprocessor signal acquiring and processing system, the general frame of its system as shown in Figure 1.The low-power consumption OMAP-L138 processor of the asymmetric coenocytism that system employing DSP is combined with ARM is main process chip, take CPLD chip XC95144XL as auxiliary control, process chip, control AD conversion chip ADS8556 the intermediate-freuqncy signal of three monitoring frequency ranges is carried out to Real-time Collection conversion, after the DSP kernel processes in OMAP-L138 processor is analyzed, by Ethernet and control centre's communication, realize the real time high-speed transmission of interference signal data and system task order.OMAP-L138 processor extends out the flash chip K9XXG08UXM of a slice 128MB and the DDR2 chip MT47H64M16HR of a slice 128MB is respectively used to the storage to program and data.System can be divided into power module, AD data acquisition module, data and program storage block, remote data transmission module, data backup module, reseting module, auxiliary and expansion connection module, interrupt management module eight parts according to Module Division, described in being implemented as follows of each module.

The power module of system comprises analog-and digital-two large divisions; Can provide+5.0V, the power supply of+3.3V ,+1.8V ,+1.2V digital voltage and+15V ,-15V analog voltage power supply.As shown in Figure 2, digital power system part is mainly by power management chip TPS650250RHBR with two modules of panel switches TPS2068DGNR are equipped with input filter network and output filtering network forms for power module design frame chart.Power management chip TPS650250RHBR ShiTI company aims at Embedded System Design, it provides three efficient step-down controllers for the voltage signal that kernel, peripheral hardware, I/O and internal memory etc. based on processor system are provided, also integrated two general 200mA LDO voltage regulators, by power management chip TPS650250RHBR for provide+3.3V of other module ,+1.8V in this system ,+1.2V voltage signal and+1.8V ,+1.2V two-way LDO voltage signal.Panel switches TPS2068DGNR ShiTI company aims at power system design, and it can limit the level of output current to safety, enters constant-current mode, realizes overcurrent protection function, the damage to circuit while preventing overload and short circuit.Simulation power pack is mainly equipped with respectively input filter network by LM7815 Voltage stabilizing module and LM7915 Voltage stabilizing module and output filtering network forms, be mainly provide+15V of other module and-15V voltage signal.Input filter network and output filtering network are comprised of magnetic bead MMZ2012S121A and AVR series capacitance network.

System will be to the up 885～889MHz of GSM-R as required, descending 930～the 934MHz of GSM-R, the intermediate-freuqncy signal acquisition process of these three frequency ranges of abnormal signal frequency range 137～960MHz, the intermediate-freuqncy signal of these three frequency ranges may be I, the non-zero if signal of Q zero intermediate frequency orthogonal signalling or other form, in order to improve the applicability of system, the AD conversion chip ADS8556 that this system adopts TI company to produce, it is a 16 the successive approximation register types in 6 tunnel (SAR) ADC, there is real bipolar input, every road has comprised sampling hold circuit, allow multichannel analog signals to be carried out to high speed acquisition simultaneously, the data acquisition rate of its parallel interface pattern is up to 630kSPS, 8～16 of highway widths are optional.This system has also adopted the CPLD chip XC95144XL of Xilinx company production and 4 road operational amplifier chip OPA4277 and the 2 road operational amplifier chip OPA2277 that Burr-Brown company produces, AD data acquisition module block diagram as shown in Figure 3, this module is by AD sampling input front end modulate circuit, AD sample conversion circuit and processor connect to form, wherein AD sample conversion circuit is connected to form by AD conversion chip ADS8556 and CPLD chip XC95144XL and OMAP-L138 processor, the input channel of AD conversion chip ADS8556 is divided into 3 groups, be A0, A1, B0, B1, C0, C1, be used for gathering three road analog intermediate frequency signals, A0 wherein, A1, B0, B1 is connected with 4 road operational amplifier OPA4277 outputs of AD sampling input front end modulate circuit, C0, C1 is connected with the output of 2 road operational amplifier OPA2277, pin PAR/SER and the HW/SW of AD conversion chip ADS8556 are set to low level, can realize the signals collecting under parallel schema, 16 bit data bus that are AD conversion chip ADS8556 transmit data to the EMIFA data terminal of OMAP-L138 processor simultaneously, the data/address bus DB ［ 0: 15 ］ of AD conversion chip ADS8556 is connected to the EMIFA data terminal EMA_D[0:15 of OMAP-L138 processor], realize the output of digital conversion results, the CPLD chip XC95144XL being connected with EMIFA data terminal is mainly used in carrying out address decoding simultaneously, operation peripheral hardware, interrupt source is distributed, the logic controls such as multiplexer gating, the CONVST_A of CPLD chip and AD conversion chip, CONVST_B, CONVST_C is connected, control the channel selecting of AD conversion chip, the chip selection signal CS/FS that AD transforms chip is also connected with CPLD chip, control the gating of AD conversion chip, the BUSY/INT of AD conversion chip ADS8556 outputs to the GPIO mouth of OMAP-L138 processor through CPLD chip XC95144XL as AD interrupt request singal, when image data is abnormal, trigger interrupt signal BUSY/INT, the control of realization to intermediate frequency collection of simulant signal, the cardinal principle workflow of AD data acquisition module is, the analog intermediate frequency signal of the up 885～889MHz of GSM-R and the descending 930～934MHz of GSM-R is gathered by A group and the B group passage of AD conversion chip ADS8556 after 4 road operational amplifier OPA4277 conditionings, AD conversion chip ADS8556 converts analog signal to digital signal, through CPLD chip XC95144XL, trigger OMAP-L138 processor respective interrupt signals, and by advance AD conversion chip ADS8556 being arranged to parallel transmission pattern, by the data/address bus DB ［ 0: 15 ］ of AD conversion chip ADS8556, export the EMIFA data terminal EMA_D[0:15 of OMAP-L138 processor to], interference analysis computing through OMAP-L138 processor, when discovery signals is abnormal, the analog intermediate frequency signal of abnormal signal frequency range 137～960MHz is gathered by the C group passage of AD conversion chip ADS8556 after 2 road operational amplifier chip OPA2277 conditionings, acquisition channel wherein switches to be realized by logic control by CPLD chip XC95144XL, by AD conversion chip, ADS8556 converts analog signal to digital signal, through CPLD chip XC95144XL, trigger OMAP-L138 processor respective interrupt signals, then by the data/address bus DB ［ 0: 15 ］ of AD conversion chip ADS8556, export the EMIFA data terminal EMA_D[0:15 of OMAP-L138 processor to], after the interference Scan orientation computing of OMAP-L138 processor, finally obtain interference source information.

Data and program storage block are comprised of data storage cell and program storage unit (PSU), and data storage cell is used to OMAP-L138 processor that enough data and the spatial cache of program operation are provided.In design, adopt the DDR2 chip MT47H64M16HR of memory space 128MB, this space is to determine according to the data volume after interference signal sampling.Program storage unit (PSU) is mainly used in program code stored, adopts the flash chip K9XXG08UXM of memory space 128MB in design, and this space mainly determines according to loading Linux operating system file size.Data/address bus and the address bus of K9XXG08UXM are multiplexing, have address latch.The EMA_D[0:7 of the data wire of flash chip K9XXG08UXM, address wire and OMAP-L138 processor] be connected, the data wire DQ[0:15 of DDR2 chip MT47H64M16HR], address wire A[0:15] respectively with the data/address bus DDR_D[0:15 of OMAP-L138 processor], address bus DDR_A[0:15] be connected.Flash chip K9XXG08UXM and DDR2 chip MT47H64M16HR enable and control signal is connected with OMAP-L138 processor; Wherein the read signal pin RE of flash chip K9XXG08UXM and OMAP-L138 processor read enable EMA_OE and be connected; The read-write enable pin WE of DDR2 chip MT47H64M16HR is directly connected with the read-write enable pin DDR_WE of OMAP-L138 processor; The chip selection signal CE of flash chip K9XXG08UXM and DDR2 chip MT47H64M16HR is connected with DDR_CS with the CS3 of OMAP-L138 processor respectively with CS.The design principle block diagram of this module as shown in Figure 4.

Remote data transmission module is comprised of ethernet transceiver LAN8710A, OMAP-L138 processor and Ethernet socket RJ45, be mainly used in setting up communication channel with control centre, realize the operations such as uploading data and transmitting order to lower levels, in OMAP-L138 processor integrated Ethernet MAC controller (EMAC).In this modular design, adopt the active crystal oscillator of external 25M to provide clock input for ethernet transceiver LAN8710A; when being configured to the message transmission rate of 100Mbit/s, ethernet transceiver LAN8710A offers tranmitting data register TXCLK and the receive clock RXCLK of EMAC25MHz; When being configured to the message transmission rate of 10Mbit/s, 25MHz clock input obtains the sending and receiving data clock of 2.5MHz and gives EMAC after 10 times of inner PLL frequency divisions of ethernet transceiver LAN8710A.The transmission data/address bus TXD[3:0 of ethernet transceiver LAN8710A] and receive data/address bus RXD[3:0] respectively the rising edge at tranmitting data register TXCLK and receive clock RXCLK be triggered.During half-duplex mode of operation, if the network conflict of ethernet transceiver LAN8710A monitoring pin COL detects network, there is data transmission collision, can automatic set report to the police.When the carrier wave induction pin CRS of ethernet transceiver LAN8710A detects network in busy state, the automatic set of meeting is also informed EMAC, if find mistake in the Frame receiving, the reception error in data marking signal RXERR meeting set of ethernet transceiver LAN8710A, and continue one or several RXCLK clock cycle.The design principle block diagram of this module as shown in Figure 5.

Data backup module is comprised of OMAP-L138 processor, SATA connector, the active crystal oscillator of 25M and clock generator CDCM61001RHBT, Main Function is that the Monitoring Data (comprising spectrogram, signal identification and decoded result, warning information) that OMAP-L138 processor has been analyzed records and stores, and waits for that control centre transfers at any time.Integrated SATA controller in OMAP-L138 processor, directly the respective pin of OMAP-L138 processor is connected with SATA connector, the SATA transfer of data pin (SATA_TXP, SATA_TXN, SATA_RXN, SATA_RXP) that concrete annexation is processor is connected with the transfer of data pin (SATA_TXP, SATA_TXN, SATA_RXN, SATA_RXP) of SATA interface respectively; During by SATA interface transmission data, need to provide reference clock for the SATA controller in OMAP-L138 processor, reference clock is produced by clock generator CDCM61001RHBT, and pin OUTN, OUTP that concrete annexation is clock generator are connected with SATA_REF_CLKN, the SATA_REF_CLKP of processor respectively; The active crystal oscillator of 25M provides input clock signal for clock generator CDCM61001RHBT.The design principle block diagram of this module as shown in Figure 6.

Reseting module mainly consists of with door SN74LVC1G11DBVR reset chip TPS3075 and three inputs with house dog and low-voltage detection function; Feed dog pulse and by CPLD chip XC95144XL inside, the clock division of CPLD is produced, activate watchdog function; Realize low-voltage detection function and need to provide reference voltage for the inner low pressure comparator of reset chip TPS3075, this voltage is provided by corresponding drive circuit, the low pressure of reset chip TPS3075 detects output pin PFO and is connected with the NMI pin of OMAP-L138 processor, realizes the detection to OMAP-L138 processor voltage state; Three inputs are connected with the reset output terminal DSP_RSTOUT of OMAP-L138 processor and the reset output terminal RESET of reset chip TPS3075 respectively with the input of door SN74LVC1G11DBVR; The reseting pin of three inputs and door SN74LVC1G11DBVR output and other modules is connected to it provides reset signal, and this module can realize artificial button and reset, and low pressure detects and resets and processor forced resetting.The design principle block diagram of this module as shown in Figure 7.

MMC/SD, USB-A and USB-mini interface in auxiliary and expansion connection module, the realization that is connected with USB-mini connector with MMC/SD, USB-A of the output pin by OMAP-L138 processor inner integrated MMCSD0, USB1.1OHCI and USB2.0OTG controller; 100 pin extensive interfaces, the expansion pin by processor and CPLD chip can directly be connected by expansion connector with 100 pin; 2 JATG interfaces, the JATG interface pin by processor and CPLD chip is directly connected with JATG connector respectively; 4 road RS232 interfaces, wherein three tunnels are connected with the input of the serial port extended chip GM8123 of 1 expansion 3 by the output pin of the UART1 controller of OMAP-L138 processor inside, the serial port extended chip GM8123 of 1 expansion 3 can be extended to the standard serial port of a full duplex 3 standard serial ports, and can control serial ports expansion pattern by external pin: single channel mode of operation and multichannel mode of operation, can specify 1 sub-serial ports and female serial ports with the single work of identical baud rate, also can allow all substring mouths frequency division on female serial ports baud rate basis work simultaneously.1 output that expands 3 serial port extended chip GM8123 is connected with the input of RS232 transceiver SN65C3238E, the realization that is directly connected with 3 RS232 connectors of the output of RS232 transceiver SN65C3238E; The output pin of UART2 controller of OMAP-L138 processor inside of leading up to is in addition connected with RS232 transceiver TRS3221ECPWR input, the realization that is connected with RS232 connector of the output of RS232 transceiver TRS3221ECPWR.The design principle block diagram of this module as shown in Figure 8.

Interrupt management module is connected and composed by CPLD chip XC9572XL and processor, annexation be external interrupt signal INT0, INT1, INT2, INT3, CNTL0, CNTL1 by CPLD chip XC9572XL respectively with the GP8[12 of processor], GP8[15], GP8[13], GP8[14], GP6[2], GP6[4] be connected, realize the management of interrupt source.This module is for expanded function, and the design principle block diagram of this module as shown in Figure 9.

Interference identification process based on the Embedded GSM-R network interferences of multiprocessor signal acquiring and processing system as shown in Figure 10.Before carrying out interference monitoring work, need some initializations: by this system scan 850-960MHz frequency range; By program control identification GSM and cdma base station signal; In the host computer of control centre, set up GSM and cdma base station Signals Data Base; Calculate possible GSM base station signal third-order intermodulation product, contrast while disturbing for generation.

After initial work completes, interference source work is searched in execution: by the up 885～889MHz frequency range of this system Real-Time Monitoring GSM-R and the descending 930～934MHz frequency range of GSM-R; by with database in GSM-R template data compare; judge that whether signal is abnormal, when generation is abnormal, analyzing is to make an uproar extremely in abnormal signal or the end.

If abnormal signal, analyzing is that co-channel interference is also non-co-channel interference, if then co-channel interference by the separated co-channel interference of algorithm identification, finally reports control centre; If be non-co-channel interference, further analyzing is that disturb GSM base station or other disturb, if disturb GSM base station, by decoding, obtain base station information, contrast GSM intermodulation database, scanning GSM working frequency range, search target BS signal, then provide and disturb source GSM base station information; If other disturb, by demodulation, decoding, obtain interference source information, then report control centre.

If make an uproar extremely in the end, then analyzing is that white Gaussian noise disturbs or CDMA band is outer to be disturbed, if white Gaussian noise disturbs, directly reports control centre; If CDMA band is outer, disturb, then scan CDMA working frequency range, search abnormal base station signal, thereby provide, disturb source cdma base station information, finally report control centre.

Complete above flow process interference source information and be aggregated into control centre, control centre is according to interference type and intensity, location interference source on electronic chart; Finally can link with existing monitoring and positioning system, eliminate and disturb, or by manual coordination, guarantee the safe operation of GRM-R network.

Claims (3)

1.GSM-R network interferences signals collecting and processing unit, it is characterized in that: comprise processor, power module, AD data acquisition module, data and program storage block, remote data transmission module, data backup module, reseting module, auxiliary and expansion connection module and interrupt management module; Described AD data acquisition module has three circuit-switched data acquisition channels, be respectively used to gather GSM-R uplink band, band downlink and abnormal signal frequency range, every circuit-switched data passage is connected to form by AD sampling input front end modulate circuit, AD sample conversion circuit and processor, described data and program storage block are connected and composed by flash chip, DDR2 chip and processor, and DDR2 chip is for the spatial cache of the digital signal as the output of AD data acquisition module; Described remote data transmission module is connected to form by ethernet transceiver and processor; Described data backup module is connected to form by SATA connector, clock generator and processor; AD data acquisition module converts the analog intermediate frequency signal of the GSM-R uplink band of Real-time Collection and band downlink to digital signal and is sent to the DSP kernel in processor, after DSP kernel calculation process, by data wire, deposit in the DDR2 chip in data and program storage block, by SATA connector, deposit big capacity hard disk in simultaneously, when image data is abnormal, AD data acquisition module starts the analog intermediate frequency signal of the abnormal frequency range of collection signal, and by ethernet transceiver and upper machine communication;

Described power module comprises digital power and analog power two parts: digital power is by input filter network, panel switches, power management chip and output filtering network form, plate external power provides operating voltage through panel switches for power management chip after input filter network filtering, the output voltage of power management chip partly provides voltage through output filtering network for digital circuit, analog power is by input filter network, Voltage stabilizing module, output filtering network forms, the input of plate external power is as the input of input filter network, the output of input filter network is as the input of Voltage stabilizing module, the output of Voltage stabilizing module is connected to the input of output filtering network, the output voltage of last output filtering network is supplied with for artificial circuit part provides voltage,

Described AD sampling input front end modulate circuit adopts operational amplifier, and analog intermediate frequency signal enters operational amplifier adjustment, described AD sample conversion circuit is connected to form by AD conversion chip and CPLD chip and processor, the output of No. three amplifiers is connected with AD conversion chip San road Gather and input passage respectively, the string of AD conversion chip pattern are controlled pin (PAR/SER and HW/SW) and are set to low level, realize the signals collecting under parallel schema, the data/address bus of AD conversion chip is connected to the data terminal EMA_D[0:15 of the external memory interface (EMIFA) of processor], realize the output of digital conversion results, the CPLD chip being connected with processor external memory interface (EMIFA) data terminal for carrying out address decoding simultaneously, operation peripheral hardware, interrupt source is distributed, the logic control of multiplexer gating, channel selecting pin (the CONVST_A of CPLD chip and AD conversion chip, CONVST_B, CONVST_C) be connected, control the channel selecting of AD conversion chip, the chip selection signal CS/FS of AD conversion chip is also connected with CPLD chip, control the gating of AD conversion chip, AD conversion chip BUSY/INT interrupt signal outputs to the interrupting input pin GP2[0 of processor through CPLD] mouthful, when image data is abnormal, trigger interrupt signal BUSY/INT, the control of realization to intermediate frequency collection of simulant signal,

The data wire of described data and the flash chip in program storage block and DDR2 chip is connected with address wire with the data wire of processor respectively with address wire, flash chip and DDR2 chip enable and control signal is connected with processor; The read signal pin of flash chip and the enable pin of reading of processor are connected; The read-write enable pin of DDR2 chip is directly connected with the read-write enable pin of processor; The chip selection signal of flash chip and DDR2 chip selects pin CS3 to be connected with DDR_CS with the sheet of processor respectively;

Described remote data transmission module is connected by the input of ethernet transceiver and the RMII interface of processor, and ethernet transceiver output is connected with Ethernet socket RJ45, and finally the host computer by optical cable and control centre carries out data, command transfer;

The annexation of described data backup module is, the SATA transfer of data pin (SATA_TXP, SATA_TXN, SATA_RXN, SATA_RXP) of processor is connected with the transfer of data pin (SATA_TXP, SATA_TXN, SATA_RXN, SATA_RXP) of SATA interface respectively, realizes the access of data; The output pin of clock generator (OUTN, OUTP) is connected with the SATA reference clock pin (SATA_REF_CLKN, SATA_REF_CLKP) of processor respectively, for the SATA interface data transmission of processor provides reference difference clock;

Described reseting module is by the reset chip with house dog and low-voltage detection function, and three inputs form with door; The dog pulse of feeding of reset chip is produced by CPLD chip internal CPLD clock division, be used for activating watchdog function, the external reference voltage of PFI pin of reset chip, this reference voltage is realized low-voltage detection function as the reference voltage of reset chip inside low pressure comparator, and the low pressure of reset chip detects output pin PFO and is connected with the NMI pin of processor; Three inputs with door input respectively with the reset output terminal DSP_RSTOUT of processor, the reset output terminal RESET of reset chip, and external resetting voltage is connected, three inputs are connected with the output of door and the reseting pin of peripheral hardware, realize processor reset, low pressure detects and resets and manual reset;

Described auxiliary and expansion connection module comprises: (1) MMC/SD card interface, and the output pin of the MMCSD0 controller by processor inside is connected with MMC/SD card connector, assists SATA interface hard disk to back up part Monitoring Data; (2) 4 road RS232 interfaces, wherein three tunnels are connected with the input of the serial port extended chip of 1 expansion 3 by the output pin of the UART1 controller of processor inside, and provide control signal by processor, the output of the serial port extended chip of 1 expansion 3 is connected with the input of RS232 transceiver, and the output of RS232 transceiver is connected with three RS232 connectors; The output pin of UART2 controller of processor inside of leading up to is in addition connected with RS232 transceiver input, RS232 transceiver output is connected with RS232 connector, ARM9 kernel in auxiliary processor is debugged, or external demodulated equipment obtains base station cell parameter and carries out interference source location; (3) USB-A and USB-mini interface, be connected with USB-mini connector with USB-A by the USB1.1OHCI of processor inside and the output pin of USB2.0OTG controller respectively, realizes the demodulated equipment of circumscribed USB interface shape; (4) 2 JATG interfaces, the JATG interface pin by processor and CPLD chip is directly connected with JATG connector respectively; (5) 100 pin extensive interfaces, the expansion pin by processor and CPLD chip can directly be connected by expansion connector with 100 pin, expands this apparatus function and realizes upgrading;

Described interrupt management module is connected and composed by CPLD chip and processor, annexation be external interrupt signal INT0, INT1, INT2, INT3, CNTL0, CNTL1 by CPLD chip respectively with the interrupting input pin of processor (GP8[12], GP8[15], GP8[13], GP8[14], GP6[2], GP6[4]) be connected, realize the management of interrupt source.

2. GSM-R network interferences signals collecting according to claim 1 and processing unit, it is characterized in that: the low power processor OMAP-L138 of processor adopting TI company based on Leonardo da Vinci's framework, the asymmetric coenocytism that uses DSP to be combined with ARM, it comprises the ARM9 kernel of a dominant frequency 300M and the C6748DSP kernel of a 300M, between DSP and ARM, by DSPLINK, carries out exchanges data.

3. GSM-R network interferences signals collecting according to claim 1 and processing unit, is characterized in that: described AD conversion chip adopts ADS8556, and CPLD chip adopts XC95144XL.

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