CN202533935U - Peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device - Google Patents
Peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device Download PDFInfo
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- CN202533935U CN202533935U CN2012201093419U CN201220109341U CN202533935U CN 202533935 U CN202533935 U CN 202533935U CN 2012201093419 U CN2012201093419 U CN 2012201093419U CN 201220109341 U CN201220109341 U CN 201220109341U CN 202533935 U CN202533935 U CN 202533935U
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Abstract
The utility model provides a peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device, wherein the inner portion of the integrated device is provided with a field programmable gata array (FPGA) chip, and the FPGA chip is respectively connected with a PCIe interface, a network interface, and an input-output interface. A PCIe end-point device is arranged in the FPGA chip, and the PCIe end-point device is provided with at least two logical function devices. The peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device can achieve multiple functions at the same time through a PCIe insert card, and basically does not occupy central processing unit (CPU) resources.
Description
Technical field
The utility model belongs to networking technology area, specifically is a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting.
Background technology
Present PCIe equipment generally is simple function PCIe plug-in card, and for completion is applied in the PCIe peripheral that needs multiple function in the system, the PCIe plug-in card of a plurality of difference in functionalitys need take a plurality of PC slots, and slot is limited in the system board.A plurality of PCIe apparatus card need the PC driver to participate in through PCIe bus switch information, take the system CPU resource.
The utility model content
In order to solve the problems of the technologies described above, the utility model provides a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting.
A kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting; It is characterized in that its set inside has fpga chip; Said fpga chip is connected with PCIe interface, network interface and IO interface respectively; Be provided with the PCIe endpoint device in the said fpga chip, at least 2 logic function equipment of PCIe endpoint device setting.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting is characterized in that said PCIe endpoint device is provided with 8 logic function equipment at most.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting is characterized in that said logic function equipment comprises cellular logic equipment, algorithm acceleration logic equipment and input and output logical device.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting; It is characterized in that said cellular logic equipment is connected to network Mac module through system interconnect bus in the sheet; Network Mac module connects the networked physics layer chip, and the networked physics layer chip connects network interface.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting; It is characterized in that said input and output logical device is connected to input/output control module through system interconnect bus in the sheet, input/output control module is connected with IO interface with pio chip through the input chip.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting is characterized in that interconnecting through equipment room hardware algorithm or interconnect module between the said logic function equipment.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting is characterized in that connecting through system interconnect bus in the sheet between the said logic function equipment.
Described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting is characterized in that described interior system interconnect bus is connected with system bus hardware algorithm module.
A kind of PCIe multifunctional equipment of the utility model and hardware-accelerated set of algorithms apparatus for converting can be realized multiple function simultaneously through a PCIe plug-in card, do not take cpu resource basically.
Description of drawings
Fig. 1 is a kind of PCIe multifunctional equipment of the utility model and the construction module synoptic diagram of hardware-accelerated set of algorithms apparatus for converting;
Among the figure, 1-PCIe interface; 2-fpga chip (field programmable gate array chip); 3-PCIe endpoint device; 4-cellular logic equipment; 5-algorithm acceleration logic equipment; 6-input and output logical device; 7-equipment room hardware algorithm or interconnect module; System interconnect bus in 8-sheet; 9-network Mac module; 10-system bus hardware algorithm module; 11-input/output control module; 12-networked physics layer chip (network phy); 13-network interface; 14-input chip; 15-pio chip; 16-IO interface.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated.
As shown in Figure 1; The utility model provides a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting; Its set inside has fpga chip; Fpga chip is connected with PCIe interface, network interface and IO interface respectively, is provided with the PCIe endpoint device in the fpga chip, and the PCIe endpoint device is provided with maximum 8 logic function equipment.Logic function equipment comprises cellular logic equipment, algorithm acceleration logic equipment and input and output logical device.Cellular logic equipment wherein is connected to network Mac module through system interconnect bus in the sheet, and network Mac module connects the networked physics layer chip, and the networked physics layer chip connects network interface.Input and output logical device wherein is connected to input/output control module through system interconnect bus in the sheet, and input/output control module is connected with IO interface with pio chip through the input chip.Interconnect through equipment room hardware algorithm or interconnect module between the logic function equipment, realize in this module that algorithms of different is handled or the data channel of stream interface; Connect through system interconnect bus in the sheet between the logic function equipment, in the sheet typically there be system bus: AXI bus, Avalon bus; The system interconnect bus is connected with system bus hardware algorithm module in the sheet, supplies distinct device through system interconnect bus access in the sheet and use.Adopt said structure; Broken through the restriction that under PC application program and driver control, to pass through PCIe system bus transmission information between the conventional P CIe equipment; Between the equipment directly or interconnected effective raising system performance of bus on chip mode, the simplified system complexity.
The PC main frame is connected to the PCIe interface of the utility model structure through PCIe interface (slot or expansion cable); Be connected to fpga chip and the inner PCIe of realization endpoint device then; Realize the Different Logic function device in the PCIe endpoint device, the PC main frame is equivalent to has connected a plurality of different physical equipment plug-in cards.Fpga chip is a programmable chip, in FPGA PCIe end points, can realize at most being equivalent to 8 PCIe plug-in cards by 8 logic function equipment.Hardware algorithm equipment uses the DSP piece in the FPGA to realize the acceleration of related algorithm, and like the FIR filtering algorithm, the FPGA hardware of fft algorithm and other algorithms is realized.Input/output module is relevant information and the input/output control circuit of realizing with fpga logic, gathers AD and data output DA like control data, and perhaps other control the IO input and output, like the supervisory system cradle head control etc.PC application program and driver can not participated in data transmission procedure, only keep watch on the control hardware processing procedure, effectively reduce system CPU occupancy rate.
The utility model is in the network monitoring field, 4 cards of former needs: network card, and Audio and Video Processing Card, storage card and cradle head control card, the device through this structure is implemented is reduced to 1 PCIe plug-in card.In data acquisition and compression applications, the data acquisition of former 250MByte/s and storage have taken the whole bandwidth of the Raid0 that 2 hard disks form and 50% cpu resource.The equipment that adopts this structure to implement; A logical device is accomplished the AD function, and another logical device is accomplished lossless compression algorithm, and last logical device is born memory function; Adopt data stream interface between the equipment; Not through the PCIe bus transfer data, the system that makes reduces hard disk of use, does not take cpu resource basically.
The above is merely the preferred embodiment of the utility model, not in order to restriction the utility model, any modification of being done within all spirit at the utility model and the principle, is equal to and replaces and improvement etc., all is included within the protection domain of the utility model.
Claims (8)
1. a PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting; It is characterized in that its set inside has fpga chip; Said fpga chip is connected with PCIe interface, network interface and IO interface respectively; Be provided with the PCIe endpoint device in the said fpga chip, at least 2 logic function equipment of PCIe endpoint device setting.
2. a kind of PCIe multifunctional equipment as claimed in claim 1 and hardware-accelerated set of algorithms apparatus for converting is characterized in that said PCIe endpoint device is provided with 8 logic function equipment at most.
3. a kind of PCIe multifunctional equipment as claimed in claim 1 and hardware-accelerated set of algorithms apparatus for converting is characterized in that said logic function equipment comprises cellular logic equipment, algorithm acceleration logic equipment and input and output logical device.
4. a kind of PCIe multifunctional equipment as claimed in claim 3 and hardware-accelerated set of algorithms apparatus for converting; It is characterized in that said cellular logic equipment is connected to network Mac module through system interconnect bus in the sheet; Network Mac module connects the networked physics layer chip, and the networked physics layer chip connects network interface.
5. a kind of PCIe multifunctional equipment as claimed in claim 3 and hardware-accelerated set of algorithms apparatus for converting; It is characterized in that said input and output logical device is connected to input/output control module through system interconnect bus in the sheet, input/output control module is connected with IO interface with pio chip through the input chip.
6. a kind of PCIe multifunctional equipment as claimed in claim 1 and hardware-accelerated set of algorithms apparatus for converting is characterized in that interconnecting through equipment room hardware algorithm or interconnect module between the said logic function equipment.
7. a kind of PCIe multifunctional equipment as claimed in claim 1 and hardware-accelerated set of algorithms apparatus for converting is characterized in that connecting through system interconnect bus in the sheet between the said logic function equipment.
8. like claim 4 or 5 or 7 described a kind of PCIe multifunctional equipment and hardware-accelerated set of algorithms apparatus for converting, it is characterized in that described interior system interconnect bus is connected with system bus hardware algorithm module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201093419U CN202533935U (en) | 2012-03-22 | 2012-03-22 | Peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201093419U CN202533935U (en) | 2012-03-22 | 2012-03-22 | Peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device |
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| CN202533935U true CN202533935U (en) | 2012-11-14 |
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| CN2012201093419U Expired - Fee Related CN202533935U (en) | 2012-03-22 | 2012-03-22 | Peripheral component interface express (PCIe) multifunctional device and hardware acceleration algorithm integrated device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050133A (en) * | 2014-06-16 | 2014-09-17 | 哈尔滨工业大学 | Communication device and method for realizing communication between DSP and PC by means of PCIE on basis of FPGA |
| CN107426347A (en) * | 2017-07-25 | 2017-12-01 | 深圳市中航比特通讯技术有限公司 | A kind of three-layer network interface arrangement and mapping method |
-
2012
- 2012-03-22 CN CN2012201093419U patent/CN202533935U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050133A (en) * | 2014-06-16 | 2014-09-17 | 哈尔滨工业大学 | Communication device and method for realizing communication between DSP and PC by means of PCIE on basis of FPGA |
| CN104050133B (en) * | 2014-06-16 | 2017-04-26 | 哈尔滨工业大学 | Communication device and method for realizing communication between DSP and PC by means of PCIE on basis of FPGA |
| CN107426347A (en) * | 2017-07-25 | 2017-12-01 | 深圳市中航比特通讯技术有限公司 | A kind of three-layer network interface arrangement and mapping method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121114 Termination date: 20210322 |