CN206042010U - Mesh multi-wing chaotic circuit - Google Patents

Mesh multi-wing chaotic circuit Download PDF

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CN206042010U
CN206042010U CN201621088517.1U CN201621088517U CN206042010U CN 206042010 U CN206042010 U CN 206042010U CN 201621088517 U CN201621088517 U CN 201621088517U CN 206042010 U CN206042010 U CN 206042010U
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operational amplifier
resistance
output end
negative input
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张朝霞
唐朝晖
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Central South University
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Abstract

The utility model discloses a chaos circuit of net multiple wing, constitute including basic chaotic signal generator circuit N1, the sequencer N2 who is used for producing switching control function, the sequencer N3 who is used for producing switching control function, basic chaotic signal generator circuit N1's output is connected with sequencer N2, sequencer N3's input respectively, and sequencer N2, sequencer N3's output and basic chaotic signal generator circuit N1 input are connected. A sequencer makes chaos circuit of net multiple wing hardware change the realization for producing switching control function, the utility model discloses can produce the chaos system of net multiple wing for chaotic encryption nature is stronger.

Description

网格多翼混沌电路Mesh multi-wing chaotic circuit

技术领域technical field

本发明涉及混沌保密通信中所需的混沌电路，具体涉及基于切换控制函数的网格多翼混沌电路。The invention relates to a chaotic circuit required in chaotic secure communication, in particular to a grid multi-wing chaotic circuit based on a switching control function.

背景技术Background technique

如何产生用于混沌保密通信中所需的各种混沌电路是近年来非线性电路与系统学科研究的一个新领域，目前已取得了一些相关的研究成果，如中国专利授权公告号CN1199968A的专利文献公开了一种变型蔡氏电路、中国专利授权公告号ZL201210129556.1的专利文献公开了一种复合混沌信号电路，但没涉及网格多翼混沌系统，因此，用于混沌保密通讯还存在局限。How to generate various chaotic circuits required in chaotic secure communication is a new field of nonlinear circuit and system research in recent years, and some related research results have been obtained, such as the patent document of Chinese patent authorization announcement number CN1199968A A modified Cai's circuit is disclosed, and the patent document of Chinese patent authorization announcement number ZL201210129556.1 discloses a composite chaotic signal circuit, but it does not involve a grid multi-wing chaotic system, so there are still limitations in using it for chaotic secure communication.

发明内容Contents of the invention

为了克服现有技术的不足，本发明的目的是提供网格多翼混沌电路，使混沌电路硬件更易实现，加密性更强。In order to overcome the deficiencies of the prior art, the object of the present invention is to provide a grid multi-wing chaotic circuit, which makes the hardware of the chaotic circuit easier to realize and stronger in encryption.

为了实现上述目的，本发明采取以下方案：In order to achieve the above object, the present invention takes the following schemes:

网格多翼混沌电路，包括基本混沌信号产生电路N1、用于产生切换控制函数S(y)的序列发生器N2、用于产生切换控制函数T(z)的序列发生器N3；所述基本混沌信号产生电路N1的输出端分别与序列发生器N2、序列发生器N3的输入端连接，序列发生器N2、序列发生器N3的输出端与基本混沌信号产生电路N1的输入端连接；The grid multi-wing chaotic circuit includes a basic chaotic signal generation circuit N1, a sequence generator N2 for generating a switching control function S (y), a sequence generator N3 for generating a switching control function T (z); the basic The output end of the chaotic signal generating circuit N1 is respectively connected to the input ends of the sequence generator N2 and the sequence generator N3, and the output ends of the sequence generator N2 and the sequence generator N3 are connected to the input end of the basic chaotic signal generating circuit N1;

其中所述基本混沌信号产生电路N1包括运算放大器OP1、运算放大器OP2、运算放大器OP3、运算放大器OP4、运算放大器OP5、乘法器MUL1、乘法器MUL2和乘法器MUL3；Wherein said basic chaotic signal generating circuit N1 includes operational amplifier OP 1 , operational amplifier OP 2 , operational amplifier OP 3 , operational amplifier OP 4 , operational amplifier OP 5 , multiplier MUL 1 , multiplier MUL 2 and multiplier MUL 3 ;

其中运算放大器OP1的输出端通过电容C1与运算放大器OP1的负输入端连接，运算放大器OP1的负输入端分别通过电阻R1、电阻R2、电阻R3与乘法器MUL1的输出端、运算放大器OP1的输出端、运算放大器OP4的输出端连接；The output terminal of the operational amplifier OP 1 is connected to the negative input terminal of the operational amplifier OP 1 through the capacitor C 1 , and the negative input terminal of the operational amplifier OP 1 is respectively connected to the multiplier MUL 1 through the resistor R 1 , the resistor R 2 , the resistor R 3 The output terminal, the output terminal of the operational amplifier OP 1 , and the output terminal of the operational amplifier OP 4 are connected;

所述运算放大器OP2的输出端通过电容C2与运算放大器OP2的负输入端连接，运算放大器OP2的负输入端通过电阻R4与运算放大器OP5的输出端连接；运算放大器OP2的输出端与序列发生器N2的输入端连接；The output terminal of the operational amplifier OP 2 is connected with the negative input terminal of the operational amplifier OP 2 through a capacitor C 2 , and the negative input terminal of the operational amplifier OP 2 is connected with the output terminal of the operational amplifier OP 5 through a resistor R 4 ; the operational amplifier OP 2 The output end of is connected with the input end of sequence generator N2;

所述运算放大器OP3的输出端通过电容C3与运算放大器OP3的负输入端连接，运算放大器OP3的负输入端分别通过电阻R5、电阻R6、电阻R7与序列发生器N3的输入端、乘法器MUL2的输出端、乘法器MUL2的输入端二连接；所述运算放大器OP3的输出端与序列发生器N3的输入端连接；The output terminal of the operational amplifier OP 3 is connected to the negative input terminal of the operational amplifier OP 3 through a capacitor C 3 , and the negative input terminal of the operational amplifier OP 3 is respectively connected to the sequence generator N3 through a resistor R 5 , a resistor R 6 , and a resistor R 7 The input end of the multiplier MUL 2 , the output end of the multiplier MUL 2 , and the input end of the multiplier MUL 2 are connected; the output end of the operational amplifier OP 3 is connected with the input end of the sequencer N3;

所述运算放大器OP4的输出端通过电阻R9与运算放大器OP4的负输入端连接，运算放大器OP4的负输入端通过电阻R8与序列发生器N2的输入端连接； The output terminal of the operational amplifier OP4 is connected with the negative input terminal of the operational amplifier OP4 through the resistance R9 , and the negative input terminal of the operational amplifier OP4 is connected with the input terminal of the sequence generator N2 through the resistance R8 ;

所述运算放大器OP5的输出端通过电阻R11与运算放大器OP5的负输入端连接，运算放大器OP5的负输入端通过电阻R10与运算放大器OP1的输出端连接；The output end of described operational amplifier OP 5 is connected with the negative input end of operational amplifier OP 5 by resistance R 11 , and the negative input end of operational amplifier OP 5 is connected with the output end of operational amplifier OP 1 by resistance R 10 ;

所述乘法器MUL2的输入端一、输入端二分别与序列发生器N2的输出端、序列发生器N3的输出端连接；The input terminal 1 and the input terminal 2 of the multiplier MUL 2 are respectively connected to the output terminal of the sequence generator N2 and the output terminal of the sequence generator N3;

所述乘法器MUL1的输入端二与乘法器MUL2的输入端二连接；The input terminal 2 of the multiplier MUL 1 is connected to the input terminal 2 of the multiplier MUL 2 ;

所述乘法器MUL3的输出端与乘法器MUL1的输入端一连接，乘法器MUL3的输入端一、输入端二分别与序列发生器N2的输入端、序列发生器N3的输入端连接；The output end of the multiplier MUL 3 is connected with the input end one of the multiplier MUL 1 , and the input end one and the input end two of the multiplier MUL 3 are respectively connected with the input end of the sequence generator N2 and the input end of the sequence generator N3 ;

所述运算放大器OP1、运算放大器OP2、运算放大器OP3、运算放大器OP4、运算放大器OP5的正输入端接地。The positive input ends of the operational amplifiers OP 1 , OP 2 , OP 3 , OP 4 and OP 5 are grounded.

优选地，序列发生器N2包括运算放大器OP6、运算放大器OP7、包括运算放大器OP8、包括运算放大器OP9、运算放大器OP10、运算放大器OP11、运算放大器OP12、运算放大器OP13、运算放大器OP14、运算放大器OP15、运算放大器OP16、运算放大器OP17、运算放大器OP18、运算放大器OP19、运算放大器OP20、运算放大器OP21、运算放大器OP22、运算放大器OP23、运算放大器OP24、运算放大器OP25、运算放大器OP26、运算放大器OP27和乘法器MUL4；Preferably, the sequencer N2 includes operational amplifiers OP 6 , operational amplifiers OP 7 , operational amplifiers OP 8 , operational amplifiers OP 9 , operational amplifiers OP 10 , operational amplifiers OP 11 , operational amplifiers OP 12 , operational amplifiers OP 13 , Operational amplifier OP 14 , Operational amplifier OP 15 , Operational amplifier OP 16 , Operational amplifier OP 17 , Operational amplifier OP 18 , Operational amplifier OP 19 , Operational amplifier OP 20 , Operational amplifier OP 21 , Operational amplifier OP 22 , Operational amplifier OP 23 , Operational amplifier OP 24 , operational amplifier OP 25 , operational amplifier OP 26 , operational amplifier OP 27 and multiplier MUL 4 ;

所述运算放大器OP6的正输入端与运算放大器OP2的输出端连接，运算放大器OP6的负输入端与运算放大器OP6的输出端连接；运算放大器OP6的输出端与乘法器MUL4的输入端一、输入端二连接，乘法器MUL3的输出端通过电阻R12与运算放大器OP12的负输入端连接；The positive input terminal of the operational amplifier OP 6 is connected with the output terminal of the operational amplifier OP 2 , and the negative input terminal of the operational amplifier OP 6 is connected with the output terminal of the operational amplifier OP 6 ; the output terminal of the operational amplifier OP 6 is connected with the multiplier MUL 4 The input terminal one and the input terminal two are connected, and the output terminal of the multiplier MUL 3 is connected with the negative input terminal of the operational amplifier OP 12 through the resistor R12 ;

所述运算放大器OP9的负输入端与运算放大器OP2的输出端连接，运算放大器OP9的输出端通过电阻R18与运算放大器OP8的负输入端连接，运算放大器OP8的负输入端通过电阻R17与运算放大器OP8的输出端连接，运算放大器OP8的输出端通过电阻R16与运算放大器OP7的负输入端连接，运算放大器OP7的负输入端通过电阻R14与运算放大器OP7的输出端连接，运算放大器OP7的输出端依次通过电阻R13、开关K1与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 9 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 9 is connected with the negative input terminal of the operational amplifier OP 8 through a resistor R 18 , and the negative input terminal of the operational amplifier OP 8 The output terminal of the operational amplifier OP 8 is connected through the resistor R 17 , the output terminal of the operational amplifier OP 8 is connected with the negative input terminal of the operational amplifier OP 7 through the resistor R 16 , and the negative input terminal of the operational amplifier OP 7 is connected with the operational amplifier through the resistor R 14 The output terminal of the amplifier OP 7 is connected, and the output terminal of the operational amplifier OP 7 is connected with the negative input terminal of the operational amplifier OP 12 through the resistor R 13 and the switch K 1 in turn;

所述运算放大器OP11的负输入端与运算放大器OP2的输出端连接，运算放大器OP11的输出端通过电阻R22与运算放大器OP10的负输入端连接，运算放大器OP10的负输入端通过电阻R21与运算放大器OP10的输出端连接；运算放大器OP10的输出端通过电阻R20与运算放大器OP7的正输入端连接；The negative input terminal of the operational amplifier OP 11 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 11 is connected with the negative input terminal of the operational amplifier OP 10 through a resistor R 22 , and the negative input terminal of the operational amplifier OP 10 Connect with the output end of operational amplifier OP 10 through resistance R 21 ; The output end of operational amplifier OP 10 is connected with the positive input end of operational amplifier OP 7 through resistance R 20 ;

所述运算放大器OP15的负输入端与运算放大器OP2的输出端连接，运算放大器OP15的输出端通过电阻R29与运算放大器OP14的负输入端连接，运算放大器OP14的负输入端通过电阻R28与运算放大器OP14的输出端连接，运算放大器OP14的输出端通过电阻R27与运算放大器OP13的负输入端连接，运算放大器OP13的负输入端通过电阻R25与运算放大器OP13的输出端连接，运算放大器OP13的输出端依次通过电阻R24、开关K2与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 15 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 15 is connected with the negative input terminal of the operational amplifier OP 14 through a resistor R 29 , and the negative input terminal of the operational amplifier OP 14 The output terminal of the operational amplifier OP 14 is connected through the resistor R 28 , the output terminal of the operational amplifier OP 14 is connected with the negative input terminal of the operational amplifier OP 13 through the resistor R 27 , and the negative input terminal of the operational amplifier OP 13 is connected with the operational amplifier through the resistor R 25 The output terminal of the amplifier OP 13 is connected, and the output terminal of the operational amplifier OP 13 is connected with the negative input terminal of the operational amplifier OP 12 through a resistor R 24 and a switch K 2 in turn;

所述运算放大器OP17的负输入端与运算放大器OP2的输出端连接，运算放大器OP17的输出端通过电阻R33与运算放大器OP16的负输入端连接，运算放大器OP16的负输入端通过电阻R32与运算放大器OP16的输出端连接；运算放大器OP16的输出端通过电阻R31与运算放大器OP13的正输入端连接；The negative input terminal of the operational amplifier OP 17 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 17 is connected with the negative input terminal of the operational amplifier OP 16 through a resistor R 33 , and the negative input terminal of the operational amplifier OP 16 Connect with the output end of operational amplifier OP 16 through resistance R 32 ; The output end of operational amplifier OP 16 is connected with the positive input end of operational amplifier OP 13 through resistance R 31 ;

所述运算放大器OP20的负输入端与运算放大器OP2的输出端连接，运算放大器OP20的输出端通过电阻R39与运算放大器OP19的负输入端连接，运算放大器OP19的负输入端通过电阻R38与运算放大器OP19的输出端连接，运算放大器OP19的输出端通过电阻R37与运算放大器OP18的负输入端连接，运算放大器OP18的负输入端通过电阻R35与运算放大器OP18的输出端连接，运算放大器OP18的输出端依次通过电阻R34、开关K3与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 20 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 20 is connected with the negative input terminal of the operational amplifier OP 19 through a resistor R 39 , and the negative input terminal of the operational amplifier OP 19 The output terminal of the operational amplifier OP 19 is connected through the resistor R 38 , the output terminal of the operational amplifier OP 19 is connected with the negative input terminal of the operational amplifier OP 18 through the resistor R 37 , and the negative input terminal of the operational amplifier OP 18 is connected with the operational amplifier through the resistor R 35 The output terminal of the amplifier OP 18 is connected, and the output terminal of the operational amplifier OP 18 is connected with the negative input terminal of the operational amplifier OP 12 through a resistor R 34 and a switch K 3 in turn;

所述运算放大器OP22的负输入端与运算放大器OP2的输出端连接，运算放大器OP22的输出端通过电阻R43与运算放大器OP21的负输入端连接，运算放大器OP21的负输入端通过电阻R42与运算放大器OP21的输出端连接；运算放大器OP21的输出端通过电阻R41与运算放大器OP18的正输入端连接；The negative input terminal of the operational amplifier OP 22 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 22 is connected with the negative input terminal of the operational amplifier OP 21 through a resistor R 43 , and the negative input terminal of the operational amplifier OP 21 Connect with the output end of operational amplifier OP 21 through resistance R 42 ; The output end of operational amplifier OP 21 is connected with the positive input end of operational amplifier OP 18 through resistance R 41 ;

所述运算放大器OP25的负输入端与运算放大器OP2的输出端连接，运算放大器OP25的输出端通过电阻R49与运算放大器OP24的负输入端连接，运算放大器OP24的负输入端通过电阻R48与运算放大器OP24的输出端连接，运算放大器OP24的输出端通过电阻R47与运算放大器OP23的负输入端连接，运算放大器OP23的负输入端通过电阻R45与运算放大器OP23的输出端连接，运算放大器OP23的输出端依次通过电阻R44、开关K4与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 25 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 25 is connected with the negative input terminal of the operational amplifier OP 24 through a resistor R 49 , and the negative input terminal of the operational amplifier OP 24 The output terminal of the operational amplifier OP 24 is connected through the resistor R 48 , the output terminal of the operational amplifier OP 24 is connected with the negative input terminal of the operational amplifier OP 23 through the resistor R 47 , and the negative input terminal of the operational amplifier OP 23 is connected with the operational amplifier through the resistor R 45 The output terminal of the amplifier OP 23 is connected, and the output terminal of the operational amplifier OP 23 is connected with the negative input terminal of the operational amplifier OP 12 through a resistor R 44 and a switch K 4 in turn;

所述运算放大器OP27的负输入端与运算放大器OP2的输出端连接，运算放大器OP27的输出端通过电阻R53与运算放大器OP26的负输入端连接，运算放大器OP26的负输入端通过电阻R52与运算放大器OP26的输出端连接；运算放大器OP26的输出端通过电阻R51与运算放大器OP23的正输入端连接；The negative input terminal of the operational amplifier OP 27 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 27 is connected with the negative input terminal of the operational amplifier OP 26 through a resistor R 53 , and the negative input terminal of the operational amplifier OP 26 Connect with the output end of operational amplifier OP 26 through resistance R 52 ; The output end of operational amplifier OP 26 is connected with the positive input end of operational amplifier OP 23 through resistance R 51 ;

所述运算放大器OP12的负输入端通过电阻R23与运算放大器OP12的输出端连接，运算放大器OP12的输出端与乘法器MUL2的输入端一连接；The negative input terminal of the operational amplifier OP 12 is connected with the output terminal of the operational amplifier OP 12 through a resistor R 23 , and the output terminal of the operational amplifier OP 12 is connected with the input terminal of the multiplier MUL 2 ;

所述运算放大器OP9、运算放大器OP11、运算放大器OP15、运算放大器OP17、运算放大器OP20、运算放大器OP22、运算放大器OP25、运算放大器OP27的正输入端分别接入电压E1、电压E2、电压E3、电压E4、电压E5、电压E6、电压E7、电压E8；The positive input terminals of the operational amplifier OP 9 , operational amplifier OP 11 , operational amplifier OP 15 , operational amplifier OP 17 , operational amplifier OP 20 , operational amplifier OP 22 , operational amplifier OP 25 , and operational amplifier OP 27 are respectively connected to the voltage E 1. Voltage E 2 , voltage E 3 , voltage E 4 , voltage E 5 , voltage E 6 , voltage E 7 , voltage E 8 ;

所述运算放大器OP8、运算放大器OP10、运算放大器OP14、运算放大器OP16、运算放大器OP19、运算放大器OP21、运算放大器OP24、运算放大器OP26、运算放大器OP12的正输入端接地；The positive input terminals of the operational amplifier OP 8 , operational amplifier OP 10 , operational amplifier OP 14 , operational amplifier OP 16 , operational amplifier OP 19 , operational amplifier OP 21 , operational amplifier OP 24 , operational amplifier OP 26 , and operational amplifier OP 12 grounding;

所述运算放大器OP7、运算放大器OP13、运算放大器OP18、运算放大器OP23的正输入端分别通过电阻R19、电阻R30、电阻R40、电阻R50接地，运算放大器OP7、运算放大器OP13、运算放大器OP18、运算放大器OP23的负输入端分别通过电阻R15、电阻R26、电阻R36、电阻R46接入电压E9、电压E10、电压E11、电压E12。The positive input terminals of the operational amplifier OP 7 , operational amplifier OP 13 , operational amplifier OP 18 , and operational amplifier OP 23 are respectively grounded through resistors R 19 , resistor R 30 , resistor R 40 , and resistor R 50 , and the operational amplifier OP 7 , operational The negative input terminals of amplifier OP 13 , operational amplifier OP 18 , and operational amplifier OP 23 are connected to voltage E 9 , voltage E 10 , voltage E 11 , and voltage E through resistor R 15 , resistor R 26 , resistor R 36 , and resistor R 46 respectively. 12 .

优选地，所述序列发生器N3包括运算放大器OP28和运算放大器OP29，其中运算放大器OP28的负输入端与运算放大器OP3的输出端连接，运算放大器OP28的输出端通过电阻R54与运算放大器OP29的负输入端连接，运算放大器OP29的负输入端通过电阻R55与运算放大器OP29的输出端连接，运算放大器OP29的输出端与乘法器MUL2的输入端二连接；运算放大器OP29和运算放大器OP29的正输入端接地。Preferably, the sequence generator N3 includes an operational amplifier OP 28 and an operational amplifier OP 29 , wherein the negative input terminal of the operational amplifier OP 28 is connected to the output terminal of the operational amplifier OP 3 , and the output terminal of the operational amplifier OP 28 is connected through a resistor R 54 Connect with the negative input terminal of the operational amplifier OP 29 , the negative input terminal of the operational amplifier OP 29 is connected with the output terminal of the operational amplifier OP 29 through the resistor R 55 , and the output terminal of the operational amplifier OP 29 is connected with the input terminal 2 of the multiplier MUL 2 ; The operational amplifier OP 29 and the positive input of the operational amplifier OP 29 are grounded.

优选地，所述运算放大器OP1～运算放大器OP29选用TL082运算放大器。Preferably, the operational amplifiers OP 1 -OP 29 are TL082 operational amplifiers.

优选地，所述乘法器MUL1～乘法器MUL4选用AD633乘法器。Preferably, the multipliers MUL 1 - MUL 4 are AD633 multipliers.

优选地，所述电阻R1～电阻R55选用精密可调电阻或精密可调电位器。Preferably, the resistors R 1 -R 55 are precision adjustable resistors or precision adjustable potentiometers.

序列发生器N2、序列发生器N3作为切换控制器来产生网格多翅膀超混沌信号，其硬件电路更易实现。Sequencer N2 and sequencer N3 are used as switching controllers to generate grid multi-wing hyperchaotic signals, and their hardware circuits are easier to implement.

本发明与已有技术相比的有益效果为：1)由于用偶对称多分段平方函数序列作为切换控制器来产生网格多翼混沌信号，其硬件电路的实现更加容易；2)采用本发明的超混沌电路，能产生网格多翼混沌信号，用于通讯中的加密，其性能更佳。Compared with the prior art, the present invention has the beneficial effects as follows: 1) due to using the even symmetric multi-section square function sequence as the switching controller to generate the grid multi-wing chaotic signal, the realization of its hardware circuit is easier; 2) adopting the present invention The super chaotic circuit invented can generate grid multi-wing chaotic signal, which is used for encryption in communication, and its performance is better.

附图说明Description of drawings

图1为本发明总体结构示意图；Fig. 1 is a schematic diagram of the overall structure of the present invention;

图2为产生切换控制函数S(y)序列发生器N2的电路示意图；Fig. 2 is the circuit schematic diagram that produces switching control function S (y) sequence generator N2;

图3为产生切换控制函数T(z)序列发生器N3的电路示意图；Fig. 3 is the circuit schematic diagram that produces switching control function T (z) sequence generator N3;

具体实施方式detailed description

图中各个器件：Each device in the figure:

OP1～OP5：基本混沌信号产生电路N1的运算放大器；OP 1 ~ OP 5 : the operational amplifier of the basic chaotic signal generating circuit N1;

MUL1～MUL3：基本混沌信号产生电路N1的乘法器；MUL 1 ~ MUL 3 : the multiplier of the basic chaotic signal generating circuit N1;

OP6～OP27：产生切换控制函数S(y)序列发生器N2的运算放大器；OP 6 -OP 27 : generate the operational amplifier of the switching control function S(y) sequence generator N2;

OP28～OP29：产生切换控制函数T(z)序列发生器N3的运算放大器；OP 28 -OP 29 : generate the operational amplifier of the switching control function T(z) sequence generator N3;

E1～E12：序列发生器N2的延时电压；E 1 ~ E 12 : Delayed voltage of sequencer N2;

以下实施用于说明本发明，但不用来限制本发明的范围。The following implementations are used to illustrate the present invention, but not to limit the scope of the present invention.

所述基本混沌信号产生电路N1的输出端分别与序列发生器N2、序列发生器N3的输入端连接，序列发生器N2、序列发生器N3的输出端与基本混沌信号产生电路N1输入端连接。The output terminals of the basic chaotic signal generating circuit N1 are respectively connected to the input terminals of the sequence generator N2 and the sequence generator N3, and the output terminals of the sequence generator N2 and the sequence generator N3 are connected to the input terminal of the basic chaotic signal generating circuit N1.

如图1所示，网格多翼混沌电路，包括基本混沌信号产生电路N1、用于产生切换控制函数S(y)的序列发生器N2、用于产生切换控制函数T(z)的序列发生器N3；所述基本混沌信号产生电路N1的输出端分别与序列发生器N2、序列发生器N3的输入端连接，序列发生器N2、序列发生器N3的输出端与基本混沌信号产生电路N1的输入端连接；As shown in Figure 1, the grid multi-wing chaotic circuit includes a basic chaotic signal generation circuit N1, a sequence generator N2 for generating the switching control function S(y), and a sequence generator for generating the switching control function T(z) device N3; the output end of the basic chaotic signal generating circuit N1 is respectively connected with the input ends of the sequence generator N2 and the sequence generator N3, and the output ends of the sequence generator N2 and the sequence generator N3 are connected with the basic chaotic signal generating circuit N1 input connection;

其中所述基本混沌信号产生电路N1包括运算放大器OP1、运算放大器OP2、运算放大器OP3、运算放大器OP4、运算放大器OP5、乘法器MUL1、乘法器MUL2和乘法器MUL3；Wherein said basic chaotic signal generating circuit N1 includes operational amplifier OP 1 , operational amplifier OP 2 , operational amplifier OP 3 , operational amplifier OP 4 , operational amplifier OP 5 , multiplier MUL 1 , multiplier MUL 2 and multiplier MUL 3 ;

其中运算放大器OP1的输出端通过电容C1与运算放大器OP1的负输入端连接，运算放大器OP1的负输入端分别通过电阻R1、电阻R2、电阻R3与乘法器MUL1的输出端、运算放大器OP1的输出端、运算放大器OP4的输出端连接；The output terminal of the operational amplifier OP 1 is connected to the negative input terminal of the operational amplifier OP 1 through the capacitor C 1 , and the negative input terminal of the operational amplifier OP 1 is respectively connected to the multiplier MUL 1 through the resistor R 1 , the resistor R 2 , the resistor R 3 The output terminal, the output terminal of the operational amplifier OP 1 , and the output terminal of the operational amplifier OP 4 are connected;

所述运算放大器OP2的输出端通过电容C2与运算放大器OP2的负输入端连接，运算放大器OP2的负输入端通过电阻R4与运算放大器OP5的输出端连接；运算放大器OP2的输出端与序列发生器N2的输入端连接；The output terminal of the operational amplifier OP 2 is connected with the negative input terminal of the operational amplifier OP 2 through a capacitor C 2 , and the negative input terminal of the operational amplifier OP 2 is connected with the output terminal of the operational amplifier OP 5 through a resistor R 4 ; the operational amplifier OP 2 The output end of is connected with the input end of sequence generator N2;

所述运算放大器OP3的输出端通过电容C3与运算放大器OP3的负输入端连接，运算放大器OP3的负输入端分别通过电阻R5、电阻R6、电阻R7与序列发生器N3的输入端、乘法器MUL2的输出端、乘法器MUL2的输入端二连接；所述运算放大器OP3的输出端与序列发生器N3的输入端连接；The output terminal of the operational amplifier OP 3 is connected to the negative input terminal of the operational amplifier OP 3 through a capacitor C 3 , and the negative input terminal of the operational amplifier OP 3 is respectively connected to the sequence generator N3 through a resistor R 5 , a resistor R 6 , and a resistor R 7 The input end of the multiplier MUL 2 , the output end of the multiplier MUL 2 , and the input end of the multiplier MUL 2 are connected; the output end of the operational amplifier OP 3 is connected with the input end of the sequencer N3;

所述运算放大器OP4的输出端通过电阻R9与运算放大器OP4的负输入端连接，运算放大器OP4的负输入端通过电阻R8与序列发生器N2的输入端连接； The output terminal of the operational amplifier OP4 is connected with the negative input terminal of the operational amplifier OP4 through the resistance R9 , and the negative input terminal of the operational amplifier OP4 is connected with the input terminal of the sequence generator N2 through the resistance R8 ;

所述运算放大器OP5的输出端通过电阻R11与运算放大器OP5的负输入端连接，运算放大器OP5的负输入端通过电阻R10与运算放大器OP1的输出端连接；The output end of described operational amplifier OP 5 is connected with the negative input end of operational amplifier OP 5 by resistance R 11 , and the negative input end of operational amplifier OP 5 is connected with the output end of operational amplifier OP 1 by resistance R 10 ;

所述乘法器MUL2的输入端一、输入端二分别与序列发生器N2的输出端、序列发生器N3的输出端连接；The input terminal 1 and the input terminal 2 of the multiplier MUL 2 are respectively connected to the output terminal of the sequence generator N2 and the output terminal of the sequence generator N3;

所述乘法器MUL1的输入端二与乘法器MUL2的输入端二连接；The input terminal 2 of the multiplier MUL 1 is connected to the input terminal 2 of the multiplier MUL 2 ;

所述乘法器MUL3的输出端与乘法器MUL1的输入端一连接，乘法器MUL3的输入端一、输入端二分别与序列发生器N2的输入端、序列发生器N3的输入端连接；The output end of the multiplier MUL 3 is connected with the input end one of the multiplier MUL 1 , and the input end one and the input end two of the multiplier MUL 3 are respectively connected with the input end of the sequence generator N2 and the input end of the sequence generator N3 ;

所述运算放大器OP1、运算放大器OP2、运算放大器OP3、运算放大器OP4、运算放大器OP5的正输入端接地。The positive input ends of the operational amplifiers OP 1 , OP 2 , OP 3 , OP 4 and OP 5 are grounded.

在具体的实施过程中，如图2所示，序列发生器N2包括运算放大器OP6、运算放大器OP7、包括运算放大器OP8、包括运算放大器OP9、运算放大器OP10、运算放大器OP11、运算放大器OP12、运算放大器OP13、运算放大器OP14、运算放大器OP15、运算放大器OP16、运算放大器OP17、运算放大器OP18、运算放大器OP19、运算放大器OP20、运算放大器OP21、运算放大器OP22、运算放大器OP23、运算放大器OP24、运算放大器OP25、运算放大器OP26、运算放大器OP27和乘法器MUL4；In the specific implementation process, as shown in Figure 2, the sequence generator N2 includes operational amplifiers OP 6 , operational amplifiers OP 7 , operational amplifiers OP 8 , operational amplifiers OP 9 , operational amplifiers OP 10 , operational amplifiers OP 11 , Operational amplifier OP 12 , Operational amplifier OP 13 , Operational amplifier OP 14 , Operational amplifier OP 15 , Operational amplifier OP 16 , Operational amplifier OP 17 , Operational amplifier OP 18 , Operational amplifier OP 19 , Operational amplifier OP 20 , Operational amplifier OP 21 , Operational amplifier OP 22 , operational amplifier OP 23 , operational amplifier OP 24 , operational amplifier OP 25 , operational amplifier OP 26 , operational amplifier OP 27 and multiplier MUL 4 ;

所述运算放大器OP6的正输入端与运算放大器OP2的输出端连接，运算放大器OP6的负输入端与运算放大器OP6的输出端连接；运算放大器OP6的输出端与乘法器MUL4的输入端一、输入端二连接，乘法器MUL3的输出端通过电阻R12与运算放大器OP12的负输入端连接；The positive input terminal of the operational amplifier OP 6 is connected with the output terminal of the operational amplifier OP 2 , and the negative input terminal of the operational amplifier OP 6 is connected with the output terminal of the operational amplifier OP 6 ; the output terminal of the operational amplifier OP 6 is connected with the multiplier MUL 4 The input terminal one and the input terminal two are connected, and the output terminal of the multiplier MUL 3 is connected with the negative input terminal of the operational amplifier OP 12 through the resistor R12 ;

所述运算放大器OP9的负输入端与运算放大器OP2的输出端连接，运算放大器OP9的输出端通过电阻R18与运算放大器OP8的负输入端连接，运算放大器OP8的负输入端通过电阻R17与运算放大器OP8的输出端连接，运算放大器OP8的输出端通过电阻R16与运算放大器OP7的负输入端连接，运算放大器OP7的负输入端通过电阻R14与运算放大器OP7的输出端连接，运算放大器OP7的输出端依次通过电阻R13、开关K1与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 9 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 9 is connected with the negative input terminal of the operational amplifier OP 8 through a resistor R 18 , and the negative input terminal of the operational amplifier OP 8 The output terminal of the operational amplifier OP 8 is connected through the resistor R 17 , the output terminal of the operational amplifier OP 8 is connected with the negative input terminal of the operational amplifier OP 7 through the resistor R 16 , and the negative input terminal of the operational amplifier OP 7 is connected with the operational amplifier through the resistor R 14 The output terminal of the amplifier OP 7 is connected, and the output terminal of the operational amplifier OP 7 is connected with the negative input terminal of the operational amplifier OP 12 through the resistor R 13 and the switch K 1 in turn;

所述运算放大器OP11的负输入端与运算放大器OP2的输出端连接，运算放大器OP11的输出端通过电阻R22与运算放大器OP10的负输入端连接，运算放大器OP10的负输入端通过电阻R21与运算放大器OP10的输出端连接；运算放大器OP10的输出端通过电阻R20与运算放大器OP7的正输入端连接；The negative input terminal of the operational amplifier OP 11 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 11 is connected with the negative input terminal of the operational amplifier OP 10 through a resistor R 22 , and the negative input terminal of the operational amplifier OP 10 Connect with the output end of operational amplifier OP 10 through resistance R 21 ; The output end of operational amplifier OP 10 is connected with the positive input end of operational amplifier OP 7 through resistance R 20 ;

所述运算放大器OP15的负输入端与运算放大器OP2的输出端连接，运算放大器OP15的输出端通过电阻R29与运算放大器OP14的负输入端连接，运算放大器OP14的负输入端通过电阻R28与运算放大器OP14的输出端连接，运算放大器OP14的输出端通过电阻R27与运算放大器OP13的负输入端连接，运算放大器OP13的负输入端通过电阻R25与运算放大器OP13的输出端连接，运算放大器OP13的输出端依次通过电阻R24、开关K2与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 15 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 15 is connected with the negative input terminal of the operational amplifier OP 14 through a resistor R 29 , and the negative input terminal of the operational amplifier OP 14 The output terminal of the operational amplifier OP 14 is connected through the resistor R 28 , the output terminal of the operational amplifier OP 14 is connected with the negative input terminal of the operational amplifier OP 13 through the resistor R 27 , and the negative input terminal of the operational amplifier OP 13 is connected with the operational amplifier through the resistor R 25 The output terminal of the amplifier OP 13 is connected, and the output terminal of the operational amplifier OP 13 is connected with the negative input terminal of the operational amplifier OP 12 through a resistor R 24 and a switch K 2 in turn;

所述运算放大器OP17的负输入端与运算放大器OP2的输出端连接，运算放大器OP17的输出端通过电阻R33与运算放大器OP16的负输入端连接，运算放大器OP16的负输入端通过电阻R32与运算放大器OP16的输出端连接；运算放大器OP16的输出端通过电阻R31与运算放大器OP13的正输入端连接；The negative input terminal of the operational amplifier OP 17 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 17 is connected with the negative input terminal of the operational amplifier OP 16 through a resistor R 33 , and the negative input terminal of the operational amplifier OP 16 Connect with the output end of operational amplifier OP 16 through resistance R 32 ; The output end of operational amplifier OP 16 is connected with the positive input end of operational amplifier OP 13 through resistance R 31 ;

所述运算放大器OP20的负输入端与运算放大器OP2的输出端连接，运算放大器OP20的输出端通过电阻R39与运算放大器OP19的负输入端连接，运算放大器OP19的负输入端通过电阻R38与运算放大器OP19的输出端连接，运算放大器OP19的输出端通过电阻R37与运算放大器OP18的负输入端连接，运算放大器OP18的负输入端通过电阻R35与运算放大器OP18的输出端连接，运算放大器OP18的输出端依次通过电阻R34、开关K3与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 20 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 20 is connected with the negative input terminal of the operational amplifier OP 19 through a resistor R 39 , and the negative input terminal of the operational amplifier OP 19 The output terminal of the operational amplifier OP 19 is connected through the resistor R 38 , the output terminal of the operational amplifier OP 19 is connected with the negative input terminal of the operational amplifier OP 18 through the resistor R 37 , and the negative input terminal of the operational amplifier OP 18 is connected with the operational amplifier through the resistor R 35 The output terminal of the amplifier OP 18 is connected, and the output terminal of the operational amplifier OP 18 is connected with the negative input terminal of the operational amplifier OP 12 through a resistor R 34 and a switch K 3 in turn;

所述运算放大器OP22的负输入端与运算放大器OP2的输出端连接，运算放大器OP22的输出端通过电阻R43与运算放大器OP21的负输入端连接，运算放大器OP21的负输入端通过电阻R42与运算放大器OP21的输出端连接；运算放大器OP21的输出端通过电阻R41与运算放大器OP18的正输入端连接；The negative input terminal of the operational amplifier OP 22 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 22 is connected with the negative input terminal of the operational amplifier OP 21 through a resistor R 43 , and the negative input terminal of the operational amplifier OP 21 Connect with the output end of operational amplifier OP 21 through resistance R 42 ; The output end of operational amplifier OP 21 is connected with the positive input end of operational amplifier OP 18 through resistance R 41 ;

所述运算放大器OP25的负输入端与运算放大器OP2的输出端连接，运算放大器OP25的输出端通过电阻R49与运算放大器OP24的负输入端连接，运算放大器OP24的负输入端通过电阻R48与运算放大器OP24的输出端连接，运算放大器OP24的输出端通过电阻R47与运算放大器OP23的负输入端连接，运算放大器OP23的负输入端通过电阻R45与运算放大器OP23的输出端连接，运算放大器OP23的输出端依次通过电阻R44、开关K4与运算放大器OP12的负输入端连接；The negative input terminal of the operational amplifier OP 25 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 25 is connected with the negative input terminal of the operational amplifier OP 24 through a resistor R 49 , and the negative input terminal of the operational amplifier OP 24 The output terminal of the operational amplifier OP 24 is connected through the resistor R 48 , the output terminal of the operational amplifier OP 24 is connected with the negative input terminal of the operational amplifier OP 23 through the resistor R 47 , and the negative input terminal of the operational amplifier OP 23 is connected with the operational amplifier through the resistor R 45 The output terminal of the amplifier OP 23 is connected, and the output terminal of the operational amplifier OP 23 is connected with the negative input terminal of the operational amplifier OP 12 through a resistor R 44 and a switch K 4 in turn;

所述运算放大器OP27的负输入端与运算放大器OP2的输出端连接，运算放大器OP27的输出端通过电阻R53与运算放大器OP26的负输入端连接，运算放大器OP26的负输入端通过电阻R52与运算放大器OP26的输出端连接；运算放大器OP26的输出端通过电阻R51与运算放大器OP23的正输入端连接；The negative input terminal of the operational amplifier OP 27 is connected with the output terminal of the operational amplifier OP 2 , the output terminal of the operational amplifier OP 27 is connected with the negative input terminal of the operational amplifier OP 26 through a resistor R 53 , and the negative input terminal of the operational amplifier OP 26 Connect with the output end of operational amplifier OP 26 through resistance R 52 ; The output end of operational amplifier OP 26 is connected with the positive input end of operational amplifier OP 23 through resistance R 51 ;

所述运算放大器OP12的负输入端通过电阻R23与运算放大器OP12的输出端连接，运算放大器OP12的输出端与乘法器MUL2的输入端一连接；The negative input terminal of the operational amplifier OP 12 is connected with the output terminal of the operational amplifier OP 12 through a resistor R 23 , and the output terminal of the operational amplifier OP 12 is connected with the input terminal of the multiplier MUL 2 ;

所述运算放大器OP9、运算放大器OP11、运算放大器OP15、运算放大器OP17、运算放大器OP20、运算放大器OP22、运算放大器OP25、运算放大器OP27的正输入端分别接入电压E1、电压E2、电压E3、电压E4、电压E5、电压E6、电压E7、电压E8；The positive input terminals of the operational amplifier OP 9 , operational amplifier OP 11 , operational amplifier OP 15 , operational amplifier OP 17 , operational amplifier OP 20 , operational amplifier OP 22 , operational amplifier OP 25 , and operational amplifier OP 27 are respectively connected to the voltage E 1. Voltage E 2 , voltage E 3 , voltage E 4 , voltage E 5 , voltage E 6 , voltage E 7 , voltage E 8 ;

所述运算放大器OP8、运算放大器OP10、运算放大器OP14、运算放大器OP16、运算放大器OP19、运算放大器OP21、运算放大器OP24、运算放大器OP26、运算放大器OP12的正输入端接地；The positive input terminals of the operational amplifier OP 8 , operational amplifier OP 10 , operational amplifier OP 14 , operational amplifier OP 16 , operational amplifier OP 19 , operational amplifier OP 21 , operational amplifier OP 24 , operational amplifier OP 26 , and operational amplifier OP 12 grounding;

所述运算放大器OP7、运算放大器OP13、运算放大器OP18、运算放大器OP23的正输入端分别通过电阻R19、电阻R30、电阻R40、电阻R50接地，运算放大器OP7、运算放大器OP13、运算放大器OP18、运算放大器OP23的负输入端分别通过电阻R15、电阻R26、电阻R36、电阻R46接入电压E9、电压E10、电压E11、电压E12。The positive input terminals of the operational amplifier OP 7 , operational amplifier OP 13 , operational amplifier OP 18 , and operational amplifier OP 23 are respectively grounded through resistors R 19 , resistor R 30 , resistor R 40 , and resistor R 50 , and the operational amplifier OP 7 , operational The negative input terminals of amplifier OP 13 , operational amplifier OP 18 , and operational amplifier OP 23 are connected to voltage E 9 , voltage E 10 , voltage E 11 , and voltage E through resistor R 15 , resistor R 26 , resistor R 36 , and resistor R 46 respectively. 12 .

在具体的实施过程中，如图3所示，所述序列发生器N3包括运算放大器OP28和运算放大器OP29，其中运算放大器OP28的负输入端与运算放大器OP3的输出端连接，运算放大器OP28的输出端通过电阻R54与运算放大器OP29的负输入端连接，运算放大器OP29的负输入端通过电阻R55与运算放大器OP29的输出端连接，运算放大器OP29的输出端与乘法器MUL2的输入端二连接；运算放大器OP29和运算放大器OP29的正输入端接地。In a specific implementation process, as shown in Figure 3, the sequence generator N3 includes an operational amplifier OP 28 and an operational amplifier OP 29 , wherein the negative input terminal of the operational amplifier OP 28 is connected to the output terminal of the operational amplifier OP 3 , and the operational The output terminal of the amplifier OP 28 is connected with the negative input terminal of the operational amplifier OP 29 through the resistor R 54 , the negative input terminal of the operational amplifier OP 29 is connected with the output terminal of the operational amplifier OP 29 through the resistor R 55 , and the output terminal of the operational amplifier OP 29 It is connected with the input terminal 2 of the multiplier MUL 2 ; the operational amplifier OP 29 and the positive input terminal of the operational amplifier OP 29 are grounded.

按照图1-图3连接电路，根据表1、表2、表3给出的数据，可确定各图中各个元器件的参数。电路产生基于切换控制的网格多翼混沌信号，序列发生器N2的开关状态与翅膀数量的对应关系如表4所示。Connect the circuit according to Figure 1-Figure 3, and according to the data given in Table 1, Table 2, and Table 3, the parameters of each component in each figure can be determined. The circuit generates a grid multi-wing chaotic signal based on switching control, and the corresponding relationship between the switching state of the sequence generator N2 and the number of wings is shown in Table 4.

根据图2，得序列发生器N2的切换控制函数S(y)的数学表达式为According to Figure 2, the mathematical expression of the switching control function S(y) of the sequence generator N2 is

上式中，N＝4，H0＝2,H1＝2.825,H2＝4.645,H3＝5.854,H4＝6.432,E1＝1.755,E2＝2.675,E3＝3.525,E4＝4.295.In the above formula, N=4, H 0 =2, H 1 =2.825, H 2 =4.645, H 3 =5.854, H 4 =6.432, E 1 =1.755, E 2 =2.675, E 3 =3.525, E 4 =4.295.

根据图3，得序列发生器N3的切换控制函数T(z)的数学表达式为According to Fig. 3, the mathematical expression of the switching control function T(z) of the sequence generator N3 is

T(z)＝sgn(z) (2)T(z)=sgn(z) (2)

根据图1，可得产生网格多翼混沌信号的状态方程为下According to Fig. 1, the state equation of grid multi-wing chaotic signal can be obtained as follows

其中，当z0＝0.35、z0＝0.35、z0＝0.3、z0＝0.23、z0＝0.2时，分别产生2×2、4×2、6×2、8×2、10×2翅膀混沌信号。Among them, when z 0 =0.35, z 0 =0.35, z 0 =0.3, z 0 =0.23, z 0 =0.2, respectively produce 2×2, 4×2, 6×2, 8×2, 10×2 Wings Chaos Signal.

本发明电路元件和电源电压的选择：图1～图3中所有的运算放大器，型号为TL082，电源电压为±E＝±15V，实验测得此时各运算放大器输出电压的饱和值为Vsat＝±13.5V。图1～图2中所有的乘法器，型号为AD633，电源电压为±E＝±15V。为了便于电路实验，为了保证电阻值的准确性，图1～图3中所有电阻均采用精密可调电阻或精密可调电位器。The selection of circuit element of the present invention and power supply voltage: all operational amplifiers among Fig. 1～Fig. =±13.5V. All the multipliers in Fig. 1 to Fig. 2, the model is AD633, and the power supply voltage is ±E=±15V. In order to facilitate the circuit experiment, in order to ensure the accuracy of the resistance value, all the resistors in Figures 1 to 3 are precision adjustable resistors or precision adjustable potentiometers.

本发明元器件参数表如下：The component parameter table of the present invention is as follows:

表1(单位：kΩ)Table 1 (unit: kΩ)

R1 R 1 55 R2 R 2 500500 R4 R 4 10001000 R5 R 5 1010 R6 R 6 10001000 R8 R 8 1010 R9 R 9 1010 R10 R 10 1010 R11 R 11 1010

表2(单位：V)Table 2 (unit: V)

E1 E 1 1.7551.755 E2 E 2 -1.755-1.755 E3 E 3 2.6752.675 E4 E 4 -2.675-2.675 E5 E 5 3.5253.525 E6 E 6 -3.525-3.525 E7 E 7 4.2954.295 E8 E 8 -4.295-4.295 E9 E 9 22 E10 E10 22 E11 E 11 22 E12 E 12 22

表3(单位：kΩ)Table 3 (unit: kΩ)

R12 R 12 5050 R13 R 13 350.88350.88 R14 R 14 1010 R15 R 15 1010 R16 R 16 1010 R17 R 17 11 R18 R 18 13.513.5 R19 R 19 55 R20 R 20 1010 R21 R 21 11 R22 R 22 13.513.5 R23 R 23 100100 R24 R 24 215.28215.28 R25 R 25 1010 R26 R 26 1010 R27 R 27 1010 R28 R 28 11 R29 R 29 13.513.5 R30 R 30 55 R31 R 31 1010 R32 R 32 11 R33 R 33 13.513.5 R34 R 34 170.82170.82 R35 R 35 1010 R36 R 36 1010 R37 R 37 1010 R38 R 38 11 R39 R 39 13.513.5 R40 R 40 55 R41 R 41 1010 R42 R 42 11 R43 R 43 13.513.5 R44 R 44 155.47155.47 R45 R 45 1010 R46 R 46 1010 R47 R 47 1010 R48 R 48 11 R49 R 49 13.513.5 R50 R 50 55 R51 R 51 1010 R52 R 52 11 R53 R 53 13.513.5 R54 R 54 13.513.5 R55 R 55 11

表4图2中电阻R3、R7、开关状态与翅膀数量的对应关系Table 4 Corresponding relationship between resistors R 3 , R 7 , switch states and the number of wings in Figure 2

R3 R 3 R7 R 7 K1 K 1 K2 K 2 K3 K 3 K4 K 4 翅膀数量number of wings 166.67166.67 28572857 断开disconnect 断开disconnect 断开disconnect 断开disconnect 2×22×2 166.67166.67 28572857 接通connected 断开disconnect 断开disconnect 断开disconnect 4×24×2 163.93163.93 33333333 接通connected 接通connected 断开disconnect 断开disconnect 6×26×2 160.26160.26 4347.84347.8 接通connected 接通connected 接通connected 断开disconnect 8×28×2 158.73158.73 50005000 接通connected 接通connected 接通connected 接通connected 10×210×2

Claims (6)

1. grid multiple wing chaos circuit, it is characterised in that including basic Generation of Chaotic Signals N1, for producing switching control The sequencer N2 of function S (y), the sequencer N3 for producing switching control function T (z)；The basic chaos letter Number produce circuit N1 output end be connected with the input of sequencer N2, sequencer N3 respectively, sequencer N2, The output end of sequencer N3 is connected with the input of basic Generation of Chaotic Signals N1；
Wherein described basic Generation of Chaotic Signals N1 includes operational amplifier OP1, operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, operational amplifier OP5, multiplier MUL1, multiplier MUL2With multiplier MUL3；
Wherein operational amplifier OP1Output end pass through electric capacity C1With operational amplifier OP1Negative input end connection, operation amplifier Device OP1Negative input end respectively pass through resistance R1, resistance R2, resistance R3With multiplier MUL1Output end, operational amplifier OP1's Output end, operational amplifier OP4Output end connection；
The operational amplifier OP2Output end pass through electric capacity C2With operational amplifier OP2Negative input end connection, operation amplifier Device OP2Negative input end pass through resistance R4With operational amplifier OP5Output end connection；Operational amplifier OP2Output end and sequence The input connection of row generator N2；
The operational amplifier OP3Output end pass through electric capacity C3With operational amplifier OP3Negative input end connection, operation amplifier Device OP3Negative input end respectively pass through resistance R5, resistance R6, resistance R7Input, multiplier MUL with sequencer N32's Output end, multiplier MUL2Input two connect；The operational amplifier OP3Output end and sequencer N3 input End connection；
The operational amplifier OP4Output end pass through resistance R9With operational amplifier OP4Negative input end connection, operation amplifier Device OP4Negative input end pass through resistance R8It is connected with the input of sequencer N2；
The operational amplifier OP5Output end pass through resistance R11With operational amplifier OP5Negative input end connection, operation amplifier Device OP5Negative input end pass through resistance R10With operational amplifier OP1Output end connection；
The multiplier MUL2Input one, input two output end respectively with sequencer N2, sequencer N3 Output end connects；
The multiplier MUL1Input two and multiplier MUL2Input two connect；
The multiplier MUL3Output end and multiplier MUL1Input one connect, multiplier MUL3Input one, input Two input respectively with sequencer N2 of end, the input of sequencer N3 are connected；
The operational amplifier OP1, operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, operational amplifier OP5's Positive input terminal is grounded.
2. grid multiple wing chaos circuit according to claim 1, it is characterised in that sequencer N2 includes operation amplifier Device OP6, operational amplifier OP7, including operational amplifier OP8, including operational amplifier OP9, operational amplifier OP10, operation amplifier Device OP11, operational amplifier OP12, operational amplifier OP13, operational amplifier OP14, operational amplifier OP15, operational amplifier OP16, operational amplifier OP17, operational amplifier OP18, operational amplifier OP19, operational amplifier OP20, operational amplifier OP21、 Operational amplifier OP22, operational amplifier OP23, operational amplifier OP24, operational amplifier OP25, operational amplifier OP26, computing Amplifier OP27With multiplier MUL4；
The operational amplifier OP6Positive input terminal and operational amplifier OP2Output end connection, operational amplifier OP6It is negative defeated Enter end and operational amplifier OP6Output end connection；Operational amplifier OP6Output end and multiplier MUL4Input one, defeated Enter two connections of end, multiplier MUL3Output end pass through resistance R12With operational amplifier OP12Negative input end connection；
The operational amplifier OP9Negative input end and operational amplifier OP2Output end connection, operational amplifier OP9Output End is by resistance R18With operational amplifier OP8Negative input end connection, operational amplifier OP8Negative input end pass through resistance R17With Operational amplifier OP8Output end connection, operational amplifier OP8Output end pass through resistance R16With operational amplifier OP7It is negative defeated Enter end connection, operational amplifier OP7Negative input end pass through resistance R14With operational amplifier OP7Output end connection, computing puts Big device OP7Output end pass sequentially through resistance R13, switch K1With operational amplifier OP12Negative input end connection；
The operational amplifier OP11Negative input end and operational amplifier OP2Output end connection, operational amplifier OP11It is defeated Go out end by resistance R22With operational amplifier OP10Negative input end connection, operational amplifier OP10Negative input end pass through resistance R21With operational amplifier OP10Output end connection；Operational amplifier OP10Output end pass through resistance R20With operational amplifier OP7 Positive input terminal connection；
The operational amplifier OP15Negative input end and operational amplifier OP2Output end connection, operational amplifier OP15It is defeated Go out end by resistance R29With operational amplifier OP14Negative input end connection, operational amplifier OP14Negative input end pass through resistance R28With operational amplifier OP14Output end connection, operational amplifier OP14Output end pass through resistance R27With operational amplifier OP13Negative input end connection, operational amplifier OP13Negative input end pass through resistance R25With operational amplifier OP13Output end connect Connect, operational amplifier OP13Output end pass sequentially through resistance R24, switch K2With operational amplifier OP12Negative input end connection；
The operational amplifier OP17Negative input end and operational amplifier OP2Output end connection, operational amplifier OP17It is defeated Go out end by resistance R33With operational amplifier OP16Negative input end connection, operational amplifier OP16Negative input end pass through resistance R32With operational amplifier OP16Output end connection；Operational amplifier OP16Output end pass through resistance R31With operational amplifier OP13Positive input terminal connection；
The operational amplifier OP20Negative input end and operational amplifier OP2Output end connection, operational amplifier OP20It is defeated Go out end by resistance R39With operational amplifier OP19Negative input end connection, operational amplifier OP19Negative input end pass through resistance R38With operational amplifier OP19Output end connection, operational amplifier OP19Output end pass through resistance R37With operational amplifier OP18Negative input end connection, operational amplifier OP18Negative input end pass through resistance R35With operational amplifier OP18Output end connect Connect, operational amplifier OP18Output end pass sequentially through resistance R34, switch K3With operational amplifier OP12Negative input end connection；
The operational amplifier OP22Negative input end and operational amplifier OP2Output end connection, operational amplifier OP22It is defeated Go out end by resistance R43With operational amplifier OP21Negative input end connection, operational amplifier OP21Negative input end pass through resistance R42With operational amplifier OP21Output end connection；Operational amplifier OP21Output end pass through resistance R41With operational amplifier OP18Positive input terminal connection；
The operational amplifier OP25Negative input end and operational amplifier OP2Output end connection, operational amplifier OP25It is defeated Go out end by resistance R49With operational amplifier OP24Negative input end connection, operational amplifier OP24Negative input end pass through resistance R48With operational amplifier OP24Output end connection, operational amplifier OP24Output end pass through resistance R47With operational amplifier OP23Negative input end connection, operational amplifier OP23Negative input end pass through resistance R45With operational amplifier OP23Output end connect Connect, operational amplifier OP23Output end pass sequentially through resistance R44, switch K4With operational amplifier OP12Negative input end connection；
The operational amplifier OP27Negative input end and operational amplifier OP2Output end connection, operational amplifier OP27It is defeated Go out end by resistance R53With operational amplifier OP26Negative input end connection, operational amplifier OP26Negative input end pass through resistance R52With operational amplifier OP26Output end connection；Operational amplifier OP26Output end pass through resistance R51With operational amplifier OP23Positive input terminal connection；
The operational amplifier OP12Negative input end pass through resistance R23With operational amplifier OP12Output end connection, computing puts Big device OP12Output end and multiplier MUL2Input one connect；
The operational amplifier OP9, operational amplifier OP11, operational amplifier OP15, operational amplifier OP17, operational amplifier OP20, operational amplifier OP22, operational amplifier OP25, operational amplifier OP27Positive input terminal be respectively connected to voltage E1, voltage E2, voltage E3, voltage E4, voltage E5, voltage E6, voltage E7, voltage E8；
The operational amplifier OP8, operational amplifier OP10, operational amplifier OP14, operational amplifier OP16, operational amplifier OP19, operational amplifier OP21, operational amplifier OP24, operational amplifier OP26, operational amplifier OP12Positive input terminal ground connection；
The operational amplifier OP7, operational amplifier OP13, operational amplifier OP18, operational amplifier OP23Positive input terminal difference By resistance R19, resistance R30, resistance R40, resistance R50Ground connection, operational amplifier OP7, operational amplifier OP13, operational amplifier OP18, operational amplifier OP23Negative input end respectively pass through resistance R15, resistance R26, resistance R36, resistance R46Access voltage E9, electricity Pressure E10, voltage E11, voltage E12。
3. grid multiple wing chaos circuit according to claim 2, it is characterised in that the sequencer N3 includes computing Amplifier OP28With operational amplifier OP29, wherein operational amplifier OP28Negative input end and operational amplifier OP3Output end Connection, operational amplifier OP28Output end pass through resistance R54With operational amplifier OP29Negative input end connection, operational amplifier OP29Negative input end pass through resistance R55With operational amplifier OP29Output end connection, operational amplifier OP29Output end with take advantage of Musical instruments used in a Buddhist or Taoist mass MUL2Input two connect；Operational amplifier OP29With operational amplifier OP29Positive input terminal ground connection.
4. grid multiple wing chaos circuit according to claim 3, it is characterised in that the operational amplifier OP1～computing is put Big device OP29From TL082 operational amplifiers.
5. grid multiple wing chaos circuit according to claim 3, it is characterised in that the multiplier MUL1～multiplier MUL4From AD633 multipliers.
6. grid multiple wing chaos circuit according to claim 3, it is characterised in that the resistance R1～resistance R55From essence Close adjustable resistance or accurate adjustable potentiometer.
CN201621088517.1U 2016-09-28 2016-09-28 Mesh multi-wing chaotic circuit Expired - Fee Related CN206042010U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107294699A (en) * 2017-08-08 2017-10-24 佛山科学技术学院 A kind of three-dimensional multi-scroll chaotic signals generator
CN108599921A (en) * 2018-06-27 2018-09-28 佛山科学技术学院 A kind of grid multi-scroll chaotic signals generator
CN109361503A (en) * 2018-12-25 2019-02-19 佛山科学技术学院 A multi-scroll circuit based on sawtooth wave chaotic anti-control

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107294699A (en) * 2017-08-08 2017-10-24 佛山科学技术学院 A kind of three-dimensional multi-scroll chaotic signals generator
CN107294699B (en) * 2017-08-08 2023-03-31 佛山科学技术学院 Three-dimensional multi-scroll chaotic signal generator
CN108599921A (en) * 2018-06-27 2018-09-28 佛山科学技术学院 A kind of grid multi-scroll chaotic signals generator
CN108599921B (en) * 2018-06-27 2023-11-03 佛山科学技术学院 A grid multi-scroll chaos signal generator
CN109361503A (en) * 2018-12-25 2019-02-19 佛山科学技术学院 A multi-scroll circuit based on sawtooth wave chaotic anti-control
CN109361503B (en) * 2018-12-25 2023-08-22 佛山科学技术学院 Multi-scroll circuit based on sawtooth wave chaos inverse control

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