CN205986786U - Take advantage of high linearity sine wave generator that clock multiplier followed - Google Patents
Take advantage of high linearity sine wave generator that clock multiplier followed Download PDFInfo
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- CN205986786U CN205986786U CN201620890988.8U CN201620890988U CN205986786U CN 205986786 U CN205986786 U CN 205986786U CN 201620890988 U CN201620890988 U CN 201620890988U CN 205986786 U CN205986786 U CN 205986786U
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Abstract
The utility model relates to a take advantage of high linearity sine wave generator that clock multiplier followed, divider resistance including reference voltage input, earthing terminal, full difference amplifier and a plurality of series connection, still include and remove the M phase -locked loop with outside clock signal is connected, with remove not door and counter that the M phase -locked loop is connected, with the seed logic generator that the counter is connected, with the shift register that seed logic generator is connected, shift register's clock signal input with the output of door is not connected, does shift register pass through logic switch and controls positive switch of 1+H and N+1 in proper order H burden switch is opened, and H is less than or equal to N and more than or equal to 0's integer, so that full difference amplifier output sine wave. Adopt the utility model discloses, can solve the low problem poor with the linearity of frequency stability.
Description
【Technical field】
This utility model is related to electronic circuit, more particularly, to takes advantage of the high linearity sine-wave generator that clock multiplier is followed.
【Background technology】
Sine-wave generator can be used for a lot of fields, such as sensor carrier wave demodulation, communication reference oscillator etc..Should at these
With, on field, the stability of frequency and the linearity are the most important parameters of sine-wave generator, directly determine application system
Performance.Sine-wave generator (shown in Fig. 1) generally used now, this output frequency becomes to the discordance of resistance and electric capacity and temperature
The impact changed is very big, so being unable to reach the state of frequency stable.This linearity be also affected by operational amplifier impact and no
Method improves.If necessary to Frequency output, capacitance needs very big, leads to area very big, severe one cannot basis in chip
And must be external.
【Utility model content】
For solving foregoing problems, the utility model proposes a kind of small volume and clock times of taking the opportunity of low frequency sine wave can be produced
The high linearity sine-wave generator that number is followed.
For reaching object defined above, this utility model adopts the following technical scheme that：Just take advantage of the high linearity that clock multiplier is followed
String wave producer is it is characterised in that include reference voltage input, the partial pressure of earth terminal, fully-differential amplifier and multiple series connection
Resistance, described divider resistance includes zero resistance to N+2 resistance, one end of described zero resistance and described reference voltage input
End connects, and described N+2 resistance is connected with earth terminal, is respectively equipped with first voltage output point and the between the plurality of divider resistance
N+1 voltage output point；
Described first voltage output point to N+1 voltage output point passes through a filter capacitor ground connection respectively；Described first
Voltage output o'clock is just being switched by one respectively to N+1 voltage output point and is being connected with the anode of described fully-differential amplifier, institute
State and just switch as N+1；Described first voltage output point and to N+1 voltage output point pass through respectively a negative switch with described
The negative terminal of fully-differential amplifier connects, and described negative switchs as N+1；
Also include：Be connected with external timing signal except M phaselocked loop, with the described not door being connected except M phaselocked loop and counting
Device, the seed logic generator being connected with described enumerator, the shift register being connected with described seed logic generator, described
The clock signal input terminal of shift register is connected with the outfan of described not door；
Described shift register controls 1+H just switching by logic switch successively and N+1-H bears switch and opens, and H is
Integer less than or equal to N and more than or equal to 0, so that described fully-differential amplifier sine wave output.
First preferred version of the present utility model is：Also include the wave filter being connected with described fully-differential amplifier, be used for
Remove clock bur.
Second preferred version of the present utility model is：Described enumerator is the N-bit counter with reset function.
This utility model possesses following technique effect：Frequency stability and the linearity can be solved the problems, such as.Sine wave output
Frequency following the punctual clock of input taking advantage of multiple (M/N).M multiple can be any integer such as 1,2,4,8 etc..Internal sine wavelength-division
Resolution coefficient N can also arbitrarily devised for any integer such as 8,10,12,16 etc., N multiple more high linearity is better.By interior
Put phaselocked loop and arbitrarily devised to be reached can take advantage of multiple (M/N), it is possible to achieve low frequency or very high-frequency sine wave signal.
Input clock just can reach very stable frequency with common crystal oscillator, is not also acted upon by temperature changes.This practicality is new
Type design and realization are simple, invent for integrated circuit (IC) system internal module, in any integrated circuit technology all
It is capable of, not there is a problem of that area is excessive or cannot be integrated.This utility model achieves fully differential output, can be all
Even slope remove, more improve the linearity.
These features of the present utility model and advantage will be detailed in following specific embodiment, accompanying drawing exposure.
【Brief description】
Below in conjunction with the accompanying drawings this utility model is described further：
Fig. 1 is first that takes advantage of the high linearity sine-wave generator that clock multiplier follows of this utility model embodiment 1
Divide theory diagram.
Fig. 2 is second that takes advantage of the high linearity sine-wave generator that clock multiplier follows of this utility model embodiment 1
Divide theory diagram.
Fig. 3 is the 3rd that takes advantage of the high linearity sine-wave generator that clock multiplier follows of this utility model embodiment 1
Divide theory diagram.
Fig. 4 is the use field taking advantage of the high linearity sine-wave generator that clock multiplier follows of this utility model embodiment 2
Scape schematic diagram.
【Specific embodiment】
The technical scheme of this utility model embodiment is explained with reference to the accompanying drawing of this utility model embodiment and
Illustrate, but following embodiment is only preferred embodiment of the present utility model, and not all.Based on the embodiment in embodiment,
Those skilled in the art's obtained other embodiment on the premise of not making creative work, broadly falls into of the present utility model
Protection domain.
Embodiment 1.
Referring to Fig. 1, Fig. 2 and Fig. 3, a kind of high linearity sine-wave generator taking advantage of clock multiplier to follow, including benchmark electricity
Pressure input Vref, the divider resistance of earth terminal, fully-differential amplifier and multiple series connection, divider resistance includes zero resistance R0、
First resistor R1, second resistance R2... N+2 resistance Rn+2, zero resistance R0One end be connected with reference voltage input, N
+ 2 resistance Rn+2Resistance is connected with earth terminal, is respectively equipped with first voltage output point V between multiple divider resistances1, second voltage output
Point V2 ... N+1 voltage output point VN+1.Wherein, first voltage output point is located at zero resistance R0With first resistor R1Between, with
The set location that this analogizes N+1 voltage output point is between two divider resistances.
As Fig. 2, first voltage output point V1To N+1 voltage output point VN+1Pass through a filter capacitor ground connection respectively, this
Place, filter capacitor has N+1, respectively C1、C2……CN+1；First voltage output point leads to respectively to N+1 voltage output point
Cross an anode V just switching with fully-differential amplifierinpConnect, just switching as N+1, respectively SP1、SP2……SPN+1；The
One voltage output point V1And to N+1 voltage output point VN+1Pass through the negative terminal V of a negative switch and fully-differential amplifier respectivelyinn
Connect, bear switch for N+1, respectively SN1、SN2……SNN+1；
The high linearity sine-wave generator that clock multiplier is followed is taken advantage of also to include：It is connected with external timing signal Clock
Except M phaselocked loop, the not door NOT being connected with except M phaselocked loop and the N-bit counter with reset function, it is connected with N-bit counter
Seed logic generator, the shift register being connected with seed logic generator, the clock signal input terminal of shift register with
The outfan of door does not connect；Shift register controls 1+H just switching by logic switch successively and N+1-H bears switch and beats
Open, H is the integer less than or equal to N and more than or equal to 0, so that fully-differential amplifier sine wave output.The numerical value of H is in clock times of taking the opportunity
In the work process of high linearity sine-wave generator followed of number, incremented by successively or successively decrease as the case may be.
The high linearity sine-wave generator that clock multiplier is followed is taken advantage of also to include the wave filter being connected with fully-differential amplifier,
For removing clock bur.
Based on aforementioned circuit, specific workflow is as follows：
Phaselocked loop is except M phaselocked loop, except the function of M phaselocked loop is the clock output frequency realizing taking advantage of clock multiplier (M).Gather around
The function of having the N-bit counter of reset function is the clock output frequency realized except multiple clock.
The function of seed logic generator is to generate first carry digit signal D to shift register1.Shift register
Function is only to allow one of just switch (S being connected with fully-differential amplifier anode according to the signal of displacementP1～SPN+1) open
With one of negative switch (S being connected with fully-differential amplifier negative terminalP1～SPN+1) open.The function of door NOT is not outside
The corresponding negative master clock Clock of clock signal Clock supplies the displacement of shift register.
The function of multiple logic switches is that the signal of shift register output is only realized with clock generation logic relation
One of them is allowed just to switch (SP1～SPN+1) open and one of negative switch (SP1～SPN+1) open.Just switch (SP1～SPN+1)
Function be, if this switch cuts out, the voltage output point connecting its one end is connected to the anode of fully-differential amplifier
VinpIf the anode V being switched off the voltage output point and fully-differential amplifier connecting its one end opened by this switchinpConnection.
Negative switch (SP1～SPN+1) function be if this switch close if connect its one end voltage output point be connected to entirely poor
Divide the negative terminal V of amplifierinnIf this negative switch opens the voltage output point being switched off connecting its one end and fully-differential amplifier
Negative terminal VinnConnection.
Filter capacitor (C1～CN+1)Function be provide this connection sine wave signal voltage node filtering, stablize this section
The voltage of point and provide the switch when connecting this node to close required moment electric charge, reduces switch and closes and caused by opening
Clock bur.Divider resistance (R0～RN+1) function mostly important, the design of each this resistance value is to be believed according to sine wave
That number function is calculated it is achieved that real sine wave signal voltage, determine the output electricity of each voltage output point
Pressure, greatly improves the linearity of sine-wave generator output.The function of fully-differential amplifier is the just switch (S per periodP1~
SPN+1) and negative switch (SP1～SPN+1) voltage that comes of sampling subtracts each other and then amplify.Amplify voltage just pass through wave filter because
Switch cuts out and opens the clock bur causing to removal.
External timing signal Clock connects the input except M phaselocked loop.Have reset function except the output of M phaselocked loop connects
The clock of N-bit counter input the input of Clk and not door NOT.Have the reset terminal Rst of N-bit counter of reset function even
Connect reset signal Reset.N position exports (Q1～QN) it is connected to seed logic generator.After completing N counting, seed logic generator
Will generate and export seed signal D1To shift register.The negative master that shift register is given according to not door NOT output
Clock signal Clockn come to realize shift.Not door NOT input connects external timing signal Clock.Enter the kind of shift register
Subsignal D1With the shift signal (D shifting out2～D2N)【2N is the number of 2xN】Connect respective logic switch, and with outside
Clock signal Clock generates logical relation to control the enable of the switch that respective logic switch output connects.
For example:
Seed signal D1Generate logical relation to control the 1st just switching S with external timing signal ClockP1；
Shift signal D2With shift signal D2NGenerate logical relation to control the 2nd just to switch with external timing signal Clock
SP2；
Shift signal DN-1With shift signal DN+1Generate logical relation to control N just to open with external timing signal Clock
Close SPN；
Shift signal DNGenerate logical relation to control N+1 just switching S with external timing signal ClockPN+1；
Shift signal DNGenerate logical relation to control the 1st negative switch S with external timing signal ClockN1；
Shift signal DN-1With shift signal DN+1Generate logical relation to control second negative to open with external timing signal Clock
Close SN2；
Shift signal D2With shift signal D2NGenerate logical relation to control N to bear switch with external timing signal Clock
SNN；
Seed signal D1Generate logical relation to control N+1 to bear switch S with external timing signal ClockNN+1Etc..
Embodiment 2.
Referring to Fig. 4, to the high linearity taking advantage of clock multiplier to follow just input a clock signal stablizing frequency from crystal oscillator
String wave producer.The time clock tracking that the high linearity sine-wave generator that clock multiplier is followed produces difference output is taken advantage of to stablize frequency
To the substrate of sensor, anode exports V to sine wave signaloutpConnect the upper substrate V of sensorst, negative terminal output VoutnConnect and pass
The infrabasal plate V of sensorsb【Connection can also export V for anode in turnoutpConnect the infrabasal plate V of sensorsb, negative terminal output
VoutnConnect the upper substrate V of sensorst】.The middle substrate V of sensorctrConnect the negative terminal input of front-end amplifier, connect feedback
Electric capacity CfOne end, is connected to feedback resistance RfOne end.The anode input of front-end amplifier connects simulation ground or power supply ground.Front end
The output of amplifier connects feedback capacity CfThe other end, be connected to feedback resistance RfThe other end.
The above, specific embodiment only of the present utility model, but protection domain of the present utility model does not limit to
In this, it is familiar with this those skilled in the art and should be understood that this utility model includes but is not limited to accompanying drawing and specific embodiment party above
Content described in formula.Any modification without departing from function and structure principle of the present utility model is intended to be included in claims
Scope in.
Claims (3)
1. take advantage of the high linearity sine-wave generator that clock multiplier is followed it is characterised in that including reference voltage input, ground connection
The divider resistance of end, fully-differential amplifier and multiple series connection, described divider resistance includes zero resistance to N+2 resistance, described
One end of zero resistance is connected with described reference voltage input, and described N+2 resistance is connected with earth terminal, the plurality of partial pressure
It is respectively equipped with first voltage output point and N+1 voltage output point between resistance；
Described first voltage output point to N+1 voltage output point passes through a filter capacitor ground connection respectively；Described first voltage
Output point is just being switched by one respectively to N+1 voltage output point and is being connected with the anode of described fully-differential amplifier, described just
Switch as N+1；Described first voltage output point and to pass through a negative switch respectively to N+1 voltage output point entirely poor with described
The negative terminal of point amplifier connects, and described negative switchs as N+1；
Also include：Be connected with external timing signal except M phaselocked loop, and the described not door being connected except M phaselocked loop and enumerator, with
The seed logic generator that described enumerator connects, the shift register being connected with described seed logic generator, described displacement
The clock signal input terminal of depositor is connected with the outfan of described not door；
Described shift register controls described 1+H just switching by logic switch successively and N+1-H bears switch and opens, and H is
Integer less than or equal to N and more than or equal to 0, so that described fully-differential amplifier sine wave output.
2. take advantage of the high linearity sine-wave generator that clock multiplier follows according to claim 1 it is characterised in that：Also include
The wave filter being connected with described fully-differential amplifier, for removing clock bur.
3. take advantage of the high linearity sine-wave generator that clock multiplier follows according to claim 1 it is characterised in that：Described meter
Number device is the N-bit counter with reset function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620890988.8U CN205986786U (en) | 2016-08-16 | 2016-08-16 | Take advantage of high linearity sine wave generator that clock multiplier followed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620890988.8U CN205986786U (en) | 2016-08-16 | 2016-08-16 | Take advantage of high linearity sine wave generator that clock multiplier followed |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205986786U true CN205986786U (en) | 2017-02-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620890988.8U Active CN205986786U (en) | 2016-08-16 | 2016-08-16 | Take advantage of high linearity sine wave generator that clock multiplier followed |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205986786U (en) |
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2016
- 2016-08-16 CN CN201620890988.8U patent/CN205986786U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: High-linearity sine-wave generator with multiplying clock multiple following Effective date of registration: 20190807 Granted publication date: 20170222 Pledgee: China Co truction Bank Corp Jiaxing branch Pledgor: JIAXING NAJIE MICROELECTRONIC TECHNOLOGY CO., LTD. Registration number: Y2019330000007 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20210429 Granted publication date: 20170222 Pledgee: China Co. truction Bank Corp Jiaxing branch Pledgor: JIAXING NAJIE MICROELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: Y2019330000007 |