CN109995372A - A kind of circuit turning voltage for pwm signal - Google Patents
A kind of circuit turning voltage for pwm signal Download PDFInfo
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- CN109995372A CN109995372A CN201910418013.3A CN201910418013A CN109995372A CN 109995372 A CN109995372 A CN 109995372A CN 201910418013 A CN201910418013 A CN 201910418013A CN 109995372 A CN109995372 A CN 109995372A
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- H—ELECTRICITY
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Abstract
The present invention discloses a kind of circuit for turning voltage for pwm signal, include: PWM sample circuit, its input signal is pwm signal and carries out high frequency clock sampling to input signal, obtain high level sampling number value of the input signal between high period and the low level sampling number value between low period, or, obtain high level sampling number value of the input signal between high period and the sampling number value in entire PWM cycle, alternatively, obtaining low level sampling number value of the input signal between low period and the sampling number value in entire PWM cycle；Count value turns potential circuit, it is connect with PWM sample circuit, each sampling number value of input is respectively controlled into count value and turns corresponding one or more digit-control resistance in potential circuit, each digit-control resistance is connected to form a ratio circuit, so that count value turns the output voltage of potential circuit and the duty ratio of the input signal is in a linear relationship.The present invention can have both high speed and low cost simultaneously, and have good stability.
Description
Technical field
The present invention relates to integrated circuit signal process field, in particular to a kind of circuit for turning voltage for pwm signal.
Background technique
Pwm signal is signal very common in electronic system, it had both had the advantages that digital signal every anti-interference, is also held very much
It easily is reduced into analog voltage signal, so many times electric message is transmitted by pwm signal as carrier.
It needs to restore by circuit after pwm signal transmits analog quantity, there are two types of common modes, the first is direct
Pwm signal is filtered by RC low-pass filter circuit, so that it may the high fdrequency component in pwm signal is filtered out, to obtain therein
DC component, i.e. voltage value.This method advantage is at low cost, the disadvantage is that speed is slow, vulnerable to interference.Second is to pass through monolithic
Machine carries out high frequency clock sampling to pwm signal, obtains the duty cycle information of PWM, then pass through DAC (digital analog converter) circuit conversion
At analog voltage signal.This method is that speed is fast a little, the disadvantage is that at high cost, system stability series depend on the property of single-chip microcontroller
Energy.
For these reasons, high speed and low cost can be had both simultaneously, have the dedicated of fine stability by providing one kind
The circuit that pwm signal turns voltage is actually necessary.
Summary of the invention
The purpose of the present invention is to provide a kind of circuits for turning voltage for pwm signal, first by high-frequency clock to defeated
The pwm signal that enters carries out high frequency clock sampling, obtains between high period sampling number between sampling number value DATAH, low period
Value DATAL or integer-period sampled secondary numerical value DATAC controls digit-control resistance secondly by DATAH, DATAL, DATAC, obtains
The resistance value directly proportional to sampling number value obtains after the interconnection again by the digit-control resistance directly proportional to sampling number value
The analog voltage output proportional to digit-control resistance value, the analog voltage of this final output and the duty ratio of pwm signal are linear
Relationship, the present invention can have both high speed and low cost simultaneously, and have good stability.
In order to achieve the above object, the invention is realized by the following technical scheme:
It is a kind of for pwm signal turn voltage circuit, characterized by comprising:
PWM sample circuit, input signal is pwm signal and carries out high frequency clock sampling to the input signal, obtains
High level sampling number value of the input signal between high period and the low level sampling number value between low period, or
Person obtains high level sampling number value of the input signal between high period and the sampling number value in entire PWM cycle,
Alternatively, obtaining low level sampling number value of the input signal between low period and the sampling number in entire PWM cycle
Value, is adopted alternatively, obtaining high level sampling number value, the low level between low period of the input signal between high period
Sample time numerical value and the sampling number value in entire PWM cycle；
Count value turns potential circuit, connect with the PWM sample circuit, and each sampling number value of input is respectively controlled institute
It states count value and turns corresponding one or more digit-control resistances in potential circuit, each digit-control resistance is connected to form a ratio circuit, with
Make that the count value turns the output voltage of potential circuit and the duty ratio of the input signal is in a linear relationship.
Preferably, the PWM sample circuit includes a pair of of counter and matched a pair of of data latches, difference
For each sampling number value counting, refresh storage and lasting output, and counted in an input PWM cycle, one
A input PWM cycle refresh and completes a PWM sampling by two PWM cycles.
Preferably, the PWM sample circuit includes:
First counter, one end are connect with the output end of the first NAND gate module, the other end and the first data latches
Input terminal connection, first counter exports high level sampling number buffer value to first data latches, output
The high level sampling number value；
Phase inverter, one end are connect with input signal, and the other end is connect with the input terminal of the second NAND gate module；
Second counter, one end are connect with the output end of the second NAND gate module, and the other end and the second data are locked
The input terminal of storage connects, the second counter output low level sampling number buffer value to second data latches,
Export the low level sampling number value；
The high level sampling number buffer value be at the signal-count period and the input signal be high level when, lead to
It crosses the input signal and enables the first NAND gate module and sampled clock signal and touched by the first NAND gate module
The numerical value sending out the first counter described and counting to get, at this time the input signal by the phase inverter close described second with it is non-
Door module, second counter stop counting；
The low level sampling number buffer value be at the signal-count period and the input signal be low level when, lead to
It crosses the input signal and closes the first NAND gate module so that first counter stops counting and the input is believed
Number enabling the second NAND gate module and sampled clock signal by the phase inverter passes through the second NAND gate module
Trigger the numerical value that second counter counts to get.
It preferably, is the signal-count period between the high period of the fractional frequency signal PWMX2 of the input signal, it is described
It is the low of the fractional frequency signal PWMX2 of a signal refresh cycle or the input signal between the low period of fractional frequency signal PWMX2
It is the signal-count period during level, is a signal refresh cycle between the high period of the fractional frequency signal PWMX2；Institute
When stating the signal refresh cycle, the failing edge or rising edge of the fractional frequency signal of the input signal produce after the delay of certain time
It is raw to refresh reset signal, the rising edge for refreshing reset signal or failing edge trigger the high level sampling number buffer value and
The low level sampling number buffer value is stored in first data latches and second data latches, refreshes high level
The high level sampling number value of period and the low level sampling number value between low period, and under the refreshing reset signal
Drop edge or rising edge trigger the reset of first counter and second counter.
Preferably, the count value turns potential circuit and is internally provided with by corresponding the first numerical control adjusted of each sampling number value
Resistance and the second digit-control resistance；First digit-control resistance and second digit-control resistance are connected in series；The second numerical control electricity
First end ground connection is hindered, second end is connected with the first end of first digit-control resistance, the second end of first digit-control resistance
A reference voltage is connected, and first digit-control resistance and the second digit-control resistance connected node are as output voltage；Work as institute
State that the first digit-control resistance is matched with the low level sampling number value and second digit-control resistance and the high level sample
When secondary values match, the output voltage and the high level duty ratio of the input signal are in a linear relationship；Or, working as described first
Digit-control resistance is matched with the high level sampling number value and second digit-control resistance and the low level sampling number value
When matching, the output voltage and the low level duty ratio of the input signal are in a linear relationship.
Preferably, first digit-control resistance and second digit-control resistance are resistance string, if the resistance string includes
The dry resistance being serially connected, the high level sampling number value and low level sampling number value are more than one bit number, bit
Digit is identical as the resistance number of corresponding digit-control resistance.
Preferably, each resistance is parallel with a switching circuit, the high level sampling number value or low level sampling time
Numerical value is connect with single bit of each switching circuit input terminal control signal, is opened when the control signal controls the switching circuit
The resistance value of Lu Shi, corresponding resistance are included in the resistance value of resistance string, corresponding when the control signal controls the switching circuit short circuit
The resistance value of resistance is not counted in the resistance value of resistance string；
The resistance value of each resistance successively increases one times in sequence in the resistance string, when the digit-control resistance is adopted by corresponding
When resistance total value after sample time numerical value adjusting is equal to the product of the smallest resistance value and the sampling number value in resistance string, the meter
Numerical value turns the output voltage of potential circuit and the high level of the input signal or low level duty ratio are in a linear relationship.
Preferably, the PWM sample circuit includes:
First counter, one end are connect with the output end of the first NAND gate module, the other end and the first data latches
Input terminal connection, first counter output high level sampling number buffer value or low level sampling number buffer value to institute
The first data latches are stated, the high level sampling number value or the low level sampling number value are exported；
Second counter, one end are connect with the output end of the second NAND gate module, and the other end and the second data are locked
The input terminal of storage connects, and second counter exports the sampling number buffer value of entire PWM cycle to second data
Latch exports the sampling number value of the entire PWM cycle；
The high level sampling number buffer value be at the signal-count period and the input signal be high level when, lead to
It crosses the input signal and enables the first NAND gate module and sampled clock signal and touched by the first NAND gate module
The numerical value sending out the first counter described and counting to get；When in the signal-count period and when the input signal is low level, institute
It states input signal and closes the first NAND gate module, first counter stops counting；
The sampling number buffer value of the entire PWM cycle is in the fractional frequency signal when the input signal as another defeated
When entering signal and when the fractional frequency signal of the input signal is high level or low level, described second is enabled by the fractional frequency signal
NAND gate module and sampled clock signal trigger what second counter counted to get by the second NAND gate module
Numerical value；When the fractional frequency signal of the input signal is low level or high level, which closes second NAND gate
Module, second counter stop counting.
It preferably, is the signal-count period between the high period of the fractional frequency signal PWMX2 of the input signal, it is described
It is the low of the fractional frequency signal PWMX2 of a signal refresh cycle or the input signal between the low period of fractional frequency signal PWMX2
It is the signal-count period during level, is a signal refresh cycle between the high period of the fractional frequency signal PWMX2；Institute
When stating the signal refresh cycle, the failing edge or rising edge of the fractional frequency signal of the input signal produce after the delay of certain time
It is raw to refresh reset signal, the rising edge for refreshing reset signal or failing edge triggering high level sampling number buffer value or low electricity
Flat sampling number buffer value and the sampling number buffer value of the entire PWM cycle are stored in the first data latches and respectively
Two data latches realize the high level sampling number value or the low level sampling number value and entire PWM weeks described
The refreshing of the sampling number value of phase；The failing edge for refreshing reset signal or rising edge trigger first counter and described
The reset of second counter guarantees the correct movement in next signal sampling period.
Preferably, the count value turns potential circuit and is internally provided with sampling number value tune by the entire PWM cycle
The first digit-control resistance and third digit-control resistance and by the high level sampling number value or the low level sampling number of section
It is worth the second digit-control resistance and the 4th digit-control resistance adjusted；The first end of first digit-control resistance is grounded, second end and one
The negative input end of operational amplifier is connected；The output voltage of the first termination operational amplifier of second digit-control resistance,
Its second end is connected with the negative input end of the operational amplifier；First termination reference voltage of the third digit-control resistance,
Second end is connected with the positive input terminal of the operational amplifier；The first end of 4th digit-control resistance is grounded, second end with
The positive input terminal of the operational amplifier is connected；The high level duty ratio or low level of the output voltage and the input signal
Duty ratio is in a linear relationship.
Compared with prior art, the invention has the benefit that there are two groups of timers in PWM sample circuit of the invention
+ latch structure for the accumulative of high-frequency count and refreshes storage and lasting output, and is counted in an input PWM cycle
Number, an input PWM cycle are refreshed, and are completed a PWM sampling by two PWM cycles, are sampled between acquisition high period
Sampling number value DATAL or integer-period sampled secondary numerical value DATAC between secondary numerical value DATAH, low period, and control count value
Turn the digit-control resistance in potential circuit, obtains the analog voltage output proportional to digit-control resistance value, the simulation of this final output
The duty ratio of voltage and pwm signal is in a linear relationship, and the present invention can have both high speed and low cost simultaneously, and has well
Stability.
Detailed description of the invention
Fig. 1 is that the pwm signal of the embodiment of the present invention one turns the circuit diagram of voltage；
Fig. 2 is the PWM sample circuit figure of the embodiment of the present invention one；
Fig. 3 is the working waveform figure of the PWM sample circuit of the embodiment of the present invention one；
Fig. 4 is that the count value of the embodiment of the present invention one turns potential circuit schematic diagram；
Fig. 5 is the digit-control resistance structural schematic diagram of the embodiment of the present invention one；
Fig. 6 is that the pwm signal of the embodiment of the present invention two turns the circuit diagram of voltage；
Fig. 7 is the PWM sample circuit figure of the embodiment of the present invention two；
Fig. 8 is the working waveform figure of the PWM sample circuit of the embodiment of the present invention two；
Fig. 9 is that the count value of the embodiment of the present invention two turns potential circuit figure.
Specific embodiment
By reading detailed description of non-limiting embodiments made by-Fig. 9 referring to Fig.1, feature of the invention,
Objects and advantages will become more apparent upon.Referring to Fig. 1-Fig. 9 for showing the embodiment of the present invention, this hair hereafter will be described in greater detail
It is bright.However, the present invention can be realized by many different forms, and it should not be construed as the limit by the embodiment herein proposed
System.
Embodiment one:
The pwm signal that Fig. 1 show the embodiment of the present invention one turns the circuit diagram of voltage, which includes PWM sample circuit
I101 and count value turn potential circuit I102.
As shown in Figure 1, PWM sample circuit I101 carries out high frequency clock sampling to input signal PWM_IN, sampling clock is
The sampling number value of CLK, the input signal PWM_IN between high period is denoted as DATAH, and the input signal PWM_IN exists
Sampling number value between low period is denoted as DATAL.
Count value turns potential circuit I102 and connect with PWM sample circuit I101, which turns potential circuit I102 will be defeated
Sampling number the value DATAH and DATAL entered respectively controls the count value respectively and turns a digit-control resistance in potential circuit I102,
The intraconnection of the two digit-control resistances forms ratio circuit, and count value turns potential circuit I102 output voltage VO UT and numerical control electricity
Hinder proportional, this output voltage VO UT and the duty ratio of input signal PWM_IN signal are in a linear relationship.
Fig. 2 show the PWM sample circuit figure of the embodiment of the present invention one, and the PWM that Fig. 3 show the embodiment of the present invention one is adopted
The working waveform figure of sample circuit.
As shown in Fig. 2 and Fig. 3 combination, PWM sample circuit I101 includes NAND gate I202, NAND gate I203, phase inverter
I201, the first counter I204, the second counter I205, the first data latches 206 and the second data latches I207.
The acquisition of the input signal PWM_IN is divided to two PWM_IN signal periods to complete, the two PWM_IN signal periods
Respectively signal-count period and signal refresh cycle.Both wherein, distinguished by the fractional frequency signal PWMX2 of PWM_IN, point
It is the signal-count period that frequency signal PWMX2, which is between high period, and it is the signal refresh cycle that PWMX2, which is between low period,.
At the signal-count period, and (the fractional frequency signal of PWM_IN at this time when input signal PWM_IN is high level
PWMX2 is high level and input signal PWM_IN is high level), the input signal PWM_IN enables NAND gate I202, sampling
Clock signal clk triggers the first counter I204 by NAND gate I202 and counts, and the first counter I204 exports high level sampling
Number buffer value DH；The input signal PWM_IN closes NAND gate I203 by phase inverter I201, and the second counter I205 stops
Only count.
At the signal-count period, and (the fractional frequency signal of PWM_IN at this time when input signal PWM_IN is low level
PWMX2 is high level and input signal PWM_IN is low level), the input signal PWM_IN closing NAND gate I202, first
Counter I204 stops counting；The input signal PWM_IN enables NAND gate I203, sampling clock letter by phase inverter I201
Number CLK triggers the second counter I205 by NAND gate I203 and counts, and it is slow that the second counter I205 exports low level sampling number
Punching value DL.
Signal refresh cycle (the i.e. at this time fractional frequency signal PWMX2 of PWM_IN is low level), the failing edge of PWMX2 passes through
It is generated after the delay of certain time and refreshes reset signal RST, the rising edge for refreshing reset signal RST triggers sampling number buffer value
DH and DL is stored in the first data latches I206 and the second data latches I207, realizes sampling number value DATAH's and DATAL
Refresh.The reset for refreshing failing edge triggering the first counter and the second counter of reset signal RST, guarantees that next signal is adopted
The correct movement in sample period.
In the present embodiment, signal-count period and signal refresh cycle are distinguished by the fractional frequency signal PWMX2 of PWM_IN,
But it is the signal-count period and PWMX2 be between low period is letter that be not limited only to fractional frequency signal PWMX2, which be between high period,
Number refresh cycle can also be that fractional frequency signal PWMX2 be between low period is the signal-count period and PWMX2 is high period
Between be the signal refresh cycle, as long as meet PWM sample circuit counted in an input PWM cycle, an input PWM cycle
Refresh and complete a PWM sampling by two PWM cycles, accordingly, the process in the signal refresh cycle is only
Rising edge and failing edge above are substituted for failing edge and rising edge respectively, details are not described herein for other content.
The count value that Fig. 4 show the embodiment of the present invention one turns potential circuit schematic diagram.
As shown in figure 4, count value, which turns potential circuit I102, is internally provided with digit-control resistance I401 and digit-control resistance I402, lead to
It crosses intraconnection and forms ratio circuit.Sampling number value DATAH adjusts digit-control resistance I402, and the resistance value after adjusting is RDH, sampling
Secondary numerical value DATAL adjusts digit-control resistance I401, and the resistance value after adjusting is RDL.Wherein, digit-control resistance I402 first end is grounded, the
Two ends are connected with the first end of digit-control resistance I401, and the second termination reference voltage VREF of digit-control resistance I401.
The connected node of digit-control resistance I401 and digit-control resistance I402 is as output VOUT, according to voltage divider principle, output electricity
Press VOUT=VREF*RDH/(RDH+RDL), i.e. output voltage VO UT and RDH/(RDH+RDL) proportional.
Fig. 5 show the exemplary embodiments of the digit-control resistance structure for the embodiment of the present invention one, wherein resistance I507,
I506, I505, I504, I503, I502, I501, I500 and the intermediate each resistance omitted form a resistance string (also referred to as numerical control
Resistance).
As shown in figure 5, I509, I510, I511, I512, I513, I514, I515, I516 are the identical switch of circuit structure
Circuit.Such as switching circuit I509 comprising N-type field-effect tube I517, p-type field-effect tube I518 and phase inverter I519.
Resistance I507 is in parallel with switching circuit I509, controls switching circuit I509 by switching circuit control signal D<X>
On-off: when switching circuit control signal D<X>is high, switching circuit I509 open circuit, resistance I507 resistance value is included in all-in resistance string
Resistance value, i.e., at this time switching circuit control signal D<X>be logical signal, can be denoted as being 1；When switching circuit controls signal D<X>
When being low, switching circuit I509 short circuit, resistance I507 resistance value is not counted in the resistance value of all-in resistance string, i.e. the letter of switching circuit control at this time
Number D<X>can be denoted as being 0.
Similarly, resistance I506 is in parallel with switching circuit I510, controls signal D<X-1>control switch electricity by switching circuit
The on-off of road I510: when switching circuit control signal D<x-1>is high, switching circuit I510 open circuit, resistance I506 resistance value is included in
The resistance value of all-in resistance string, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit controls
When signal D<x-1>is low, switching circuit I510 short circuit, resistance I506 resistance value is not counted in the resistance value of all-in resistance string, i.e., switchs at this time
Circuit control signal D<X>can be denoted as being 0.
Similarly, resistance I505 is in parallel with switching circuit I511, controls signal D<X-2>control switch electricity by switching circuit
The on-off of road I511, when switching circuit control signal D<X-2>is high, switching circuit I511 open circuit, resistance I505 resistance value is included in
The resistance value of all-in resistance string, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit controls
When signal D<X-2>is low, switching circuit I511 short circuit, resistance I505 resistance value is not counted in the resistance value of all-in resistance string, i.e., switchs at this time
Circuit control signal D<X>can be denoted as being 0.
Similarly, resistance I504 is in parallel with switching circuit I512, controls signal D<X-3>control switch electricity by switching circuit
The on-off of road I512, when switching circuit control signal D<X-3>is high, switching circuit I512 open circuit, resistance I504 resistance value is included in
The resistance value of all-in resistance string, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit controls
When signal D<X-3>is low, switching circuit I512 short circuit, resistance I504 resistance value is not counted in the resistance value of all-in resistance string, i.e., switchs at this time
Circuit control signal D<X>can be denoted as being 0.
Similarly, resistance I503 is in parallel with switching circuit I513, controls signal D<3>control switch circuit by switching circuit
The on-off of I513, when switching circuit control signal D<3>is high, switching circuit I513 open circuit, resistance I503 resistance value is included in total electricity
The resistance value of string is hindered, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit controls signal D
<3>when being low, switching circuit I513 short circuit, resistance I503 resistance value is not counted in the resistance value of all-in resistance string, i.e. switching circuit control at this time
Signal D<X>processed can be denoted as being 0.
Resistance I502 is in parallel with switching circuit I514, controls signal D<2>control switch circuit I 514 by switching circuit
On-off, when switching circuit control signal D<2>is high, switching circuit I514 open circuit, resistance I502 resistance value is included in all-in resistance string
Resistance value, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit control signal D<2>is
When low, switching circuit I514 short circuit, resistance I502 resistance value is not counted in the resistance value of all-in resistance string, i.e., switching circuit controls signal at this time
D<X>can be denoted as being 0.
Similarly, resistance I501 is in parallel with switching circuit I515, controls signal D<1>control switch circuit by switching circuit
The on-off of I515, when switching circuit control signal D<1>is high, switching circuit I515 open circuit, resistance I501 resistance value is included in total electricity
The resistance value of string is hindered, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit controls signal D
<1>when being low, switching circuit I515 short circuit, resistance I501 resistance value is not counted in the resistance value of all-in resistance string, i.e. switching circuit control at this time
Signal D<X>processed can be denoted as being 0.
Similarly, resistance I500 is in parallel with switching circuit I516, controls signal D<0>control switch circuit by switching circuit
The on-off of I516, when switching circuit control signal D<0>is high, switching circuit I516 open circuit, resistance I500 resistance value is included in total electricity
The resistance value of string is hindered, i.e., switching circuit control signal D<X>is logical signal at this time, can be denoted as being 1；When switching circuit controls signal D
<0>when being low, switching circuit I516 short circuit, resistance I500 resistance value is not counted in the resistance value of all-in resistance string, i.e. switching circuit control at this time
Signal D<X>processed can be denoted as being 0.
In conclusion including several resistance in resistance string, the not limited to of resistance is electric in above-described embodiment, resistance string
The quantity of resistance is denoted as being X+1.Sampling number value DATAH or sampling number value DATAL passes through above-mentioned each switching circuit control letter
Number realize the resistance value for controlling each digit-control resistance.Sampling number value DATAH and sampling number value DATAL is bit number more than one,
Bit digit is identical as the resistance number of corresponding resistance string, i.e. sampling number value DATAH is the control of digit-control resistance I402
Signal, sampling number value DATAL are the control signal of I401.In resistance string, the corresponding control bit of each resistance (D <
0>, D<1>, D<2>, D<3>... D<X-3>, D<X-2>, D<X-1>, D<X>, be single bit number), when switching circuit control believe
When number every high control bit, resistance is doubled.
As shown in figure 5, setting resistance I500 resistance value as R0, then resistance I501 resistance value is R0*2, resistance I502 resistance
Value is R0*22, resistance I503 resistance value is R0*23, resistance I504 resistance value is R0*2X-3, resistance I505 resistance value is R0*2X-2,
Resistance I506 resistance value is R0*2X-1, resistance I507 resistance value is R0*2X.The total resistance value R of the resistance string of digit-control resistanceTOTALIt is as follows:
RTOTAL
=D<0>* R0+D<1>* R0*2+D<2>* R0*22+D<3>*R0*23+……
+D<X-3>*R0*2X-3+D<X-2>*R0*2X-2+D<X-1>*R0*2X-1+D<X>*
R0*2X
=R0 (D<0>+D<1>* 2+D<2>* 22+D<3>*23+D<1>*2+
……+D<X-3>*2X-3+D<X-2>*2X-2+D<X-1>*2X-1+D<X>*2X)
=R0*D<X:0>；
In formula, D<0>, D<1>, D<2>, D<3>... D<X-3>, D<X-2>, D<X-1>, D<X>are single bit numbers, D<X:
0>be with the bit digit of sampling number value DATAH or the DATAL more bit numbers to match and D<X:0>be X+1.
As shown in figure 4, the digit-control resistance I401 (also referred to as resistance string) and digit-control resistance I402 of the present embodiment are that resistance string is total
Resistance value and all identical two digit-control resistances of control digit.Since the control that sampling number value DATAH is digit-control resistance I402 is believed
Number, sampling number value DATAL is the control signal of I401, then after said switching circuit controls Signal Regulation, so that numerical control
Resistance value R after resistance I402 adjustingDHResistance value R after=R0*DATAH and digit-control resistance I401 adjustingDL=R0*DATAL, most
Whole output voltage VO UT is as follows:
VOUT
=VREF*RDH/(RDH+RDL)
=VREF* (R0*DATAH)/(R0*DATAH+R0*DATAL)
=VREF*DATAH/ (DATAH+DATAL)；
Wherein, due to the high level count value that DATAH is pwm signal, DATAL is the low level count value of pwm signal, institute
It is exactly count value of the pwm signal high level count value divided by one complete cycle of pwm signal with DATAH/ (DATAH+DATAL),
It is exactly high level duty ratio Duty, then has following formula:
VOUT=VREF*Duty；
Wherein, VOUT is the output voltage for the circuit that pwm signal of the invention turns voltage, and VREF is reference voltage, Duty
High level for the high level duty ratio of input signal PWM_IN, i.e. this output voltage VO UT and input signal PWM_IN signal accounts for
Sky is than in a linear relationship.Therefore, this embodiment achieves pwm signals to the linear transformation of voltage signal.
In addition, the sampling number value DATAH in above-described embodiment one transforms the control signal for digit-control resistance I401 into, adopt
Sample time numerical value DATAL transforms the control signal for digit-control resistance I402 into, then the resistance value of digit-control resistance I402 is RDH=R0*DATAL,
The resistance value of digit-control resistance I401 is RDL=R0*DATAH, then output voltage VO UT is as follows:
VOUT
=VREF*RDH/(RDH+RDL)
=VREF* (R0*DATAL)/(R0*DATAH+R0*DATAH)
=VREF*DATAL/ (DATAH+DATAL)；
Wherein, due to the high level count value that DATAH is pwm signal, DATAL is the low level count value of pwm signal, institute
It is exactly count value of the pwm signal low level count value divided by one complete cycle of pwm signal with DATAL/ (DATAH+DATAL),
It is exactly low level duty ratio Duty ', then has following formula:
VOUT=VREF*Duty '；
Wherein, VOUT is the output voltage for the circuit that pwm signal of the invention turns voltage, and VREF is reference voltage, Duty '
Low level for the low level duty ratio of input signal PWM_IN, i.e. this output voltage VO UT and input signal PWM_IN signal accounts for
Sky is than in a linear relationship.Therefore, this embodiment achieves pwm signals to the linear transformation of voltage signal.
Embodiment two:
The pwm signal that Fig. 6 show the embodiment of the present invention two turns the circuit diagram of voltage, which includes PWM sample circuit
I601 and count value turn potential circuit I602.
As shown in fig. 6, PWM sample circuit I601 carries out high frequency clock sampling to input signal PWM_IN, sampling clock is
CLK, the sampling number value between the input signal PWM_IN high period are denoted as DATAH, the input signal PWM_IN mono-
The sampling number value of entire PWM cycle is denoted as DATAC.
Count value turns potential circuit I602 and connect with PWM sample circuit I601, which turns potential circuit I602 will be defeated
Sampling number value DATAH and DATAC the control count value entered turns multiple digit-control resistances in potential circuit I602, and by multiple
The intraconnection of digit-control resistance forms ratio circuit, count value turn potential circuit I602 output voltage VO UT and digit-control resistance at than
Example, the i.e. duty ratio of this output voltage VO UT and input signal PWM_IN signal are in a linear relationship.
Fig. 7 show the PWM sample circuit figure of the embodiment of the present invention two, is illustrated in figure 8 the PWM of the embodiment of the present invention two
The working waveform figure of sample circuit.
As shown in Fig. 7 and Fig. 8 combination, the PWM sample circuit I601 includes: NAND gate I701, NAND gate I702, first
Counter I703, the second counter I704, the first data latches I705 and the second data latches I706.
The acquisition of input signal PWM_IN is divided to two PWM_IN signal periods to complete, the two PWM_IN signal periods are distinguished
For signal-count period and signal refresh cycle.Both wherein, distinguished by the fractional frequency signal PWMX2 of PWM_IN, PWMX2 is
It is the signal-count period between high period, it is the signal refresh cycle that PWMX2, which is between low period,.
In the signal-count period, and (the fractional frequency signal of PWM_IN at this time when input signal PWM_IN is high level
PWMX2 is high level and input signal PWM_IN is high level), input signal PWM_IN enables NAND gate I701, sampling clock
Signal CLK triggers the first counter I703 by NAND gate I701 and counts, and the first counter I703 exports high level sampling number
Buffer value DH.
In the signal-count period, and (the fractional frequency signal of PWM_IN at this time when input signal PWM_IN is low level
PWMX2 is high level and input signal PWM_IN is low level), input signal PWM_IN closes NAND gate I701, and first counts
Device I703 stops counting.
During the signal-count period, for PWMX2 as another input signal, input signal PWMX2 is high level, frequency dividing
Signal PWMX2 enables NAND gate I702, and sampled clock signal CLK triggers the second counter I704 by NAND gate I702 and counts,
Second counter I704 exports sampling number buffer value, the as sampling number value DC of complete cycle, because when PWMX2 is high level
It comprising input signal PWM_IN is low level and input signal PWM_IN is both feelings of high level when the phase (signal-count period)
Condition, so the count value that PWM_IN is low level and high level will be obtained when counting PWMX2 as an input signal
With to obtain the sampling number value DC of complete cycle；When signal-count end cycle, PWMX2 becomes low level, fractional frequency signal
PWMX2 closes NAND gate I702, and the second counter I704 stops counting.
Under signal refresh cycle (the i.e. at this time fractional frequency signal PWMX2 of PWM_IN is low level), fractional frequency signal PWMX2
Drop refreshes the rising edge triggering sampling time of reset signal RST along refreshing reset signal RST is generated after the delay of certain time
Number buffer value DH and DC are stored in the first data latches I705 and the second data latches I706 respectively, realize sampling number value
The refreshing of DATAH and DATAC.The failing edge for refreshing reset signal RST triggers the first counter I703 and the second counter I704
Reset, guarantee the next signal sampling period correct movement.
In the present embodiment, signal-count period and signal refresh cycle are distinguished by the fractional frequency signal PWMX2 of PWM_IN,
But it is the signal-count period and PWMX2 be between low period is letter that be not limited only to fractional frequency signal PWMX2, which be between high period,
Number refresh cycle can also be that fractional frequency signal PWMX2 be between low period is the signal-count period and PWMX2 is high period
Between be the signal refresh cycle, as long as meet PWM sample circuit counted in an input PWM cycle, an input PWM cycle
Refresh and completes a PWM sampling by two PWM cycles.
The count value that Fig. 9 show the embodiment of the present invention two turns potential circuit figure.
As shown in figure 9, count value, which turns potential circuit I602, is internally provided with digit-control resistance I901, I902, I903 and I904,
Ratio circuit is formed by intraconnection.The sampling number value DATAC of complete cycle adjusts digit-control resistance I901 and digit-control resistance
I903, the resistance value after adjusting are RDC；High level sampling number value DATAH adjusts digit-control resistance I902 and I904, after adjusting
Resistance value is RDH。
Digit-control resistance I901 first end ground connection, second end are connected with the negative input end VN of operational amplifier I905；Numerical control
Resistance I902 first terminates the output voltage VO UT of operational amplifier I905, the negative input of second end and operational amplifier I905
VN is held to be connected；Digit-control resistance I903 first terminates reference voltage VREF, the positive input terminal of second end and operational amplifier I905
VP is connected；Digit-control resistance I904 first end ground connection, second end are connected with the positive input terminal VP of operational amplifier I905.
Wherein, according to voltage divider principle, the positive input terminal VP voltage of the operational amplifier I905 is VREF*RDH/(RDC+
RDH).The negative input end VN voltage of the operational amplifier I905 is VOUT*RDC/(RDC+RDH)。
In addition, the characteristics of input terminal imaginary short positive and negative according to operational amplifier, obtains:
VREF*RDH/(RDC+RDH)=VOUT*RDC/(RDC+RDH)；
To available, VOUT=VREF*RDH/RDC；
In the present embodiment, digit-control resistance I901, I902, I903, I904 are that the total resistance value of resistance string and control digit are all identical
Four digit-control resistances, internal structure as in the first embodiment, as shown in Figure 5.Turn the number of potential circuit with pwm signal in embodiment one
Control resistance feature is identical, and this will not be repeated here for principle, then RDC=DATAC*R0, RDH=DATAH*R0, RDH/RDC=DATAH/
DATAC=Duty, it may be assumed that
VOUT=VREF*Duty；
Wherein, VOUT is the output voltage for the circuit that pwm signal of the invention turns voltage, and VREF is reference voltage, PWM_
Sampling number value between IN high period is DATAH, and the sampling number value of mono- complete cycle of input signal PWM_IN is DATAC,
Duty is the high level duty ratio of input signal PWM_IN, i.e. the height electricity of this output voltage VO UT and input signal PWM_IN signal
Flat duty ratio is in a linear relationship.Therefore, this embodiment achieves pwm signals to the linear transformation of voltage signal.
The present invention is DATAH and low electricity except through the sampling number value between the acquisition high period in above-described embodiment one
Sampling number value DATAL during flat realizes the control of each digit-control resistance, to realize that pwm signal turns to the linear of voltage signal
Change and embodiment two in acquisition high period between sampling number value DATAH and entire PWM cycle sampling number value
DATAC realizes the control of each digit-control resistance, to realize linear transformation of the pwm signal to voltage signal, can also pass through acquisition
The sampling number value DATAC of sampling number value DATAL and entire PWM cycle between low period realize the control of each digit-control resistance
System, to realize linear transformation of the pwm signal to voltage signal, this method is identical as embodiment two, as long as by between high period
Sampling number value DATAH replace with the sampling number value DATAL between low period, the present invention does not repeat them here this.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. it is a kind of for pwm signal turn voltage circuit, characterized by comprising:
PWM sample circuit, input signal is pwm signal and carries out high frequency clock sampling to the input signal, obtains described
High level sampling number value of the input signal between high period and the low level sampling number value between low period, alternatively,
High level sampling number value of the input signal between high period and the sampling number value in entire PWM cycle are obtained, or
Person obtains low level sampling number value of the input signal between low period and the sampling number value in entire PWM cycle,
Alternatively, obtaining high level sampling number value of the input signal between high period, the sampling of the low level between low period
Secondary numerical value and sampling number value in entire PWM cycle；
Count value turns potential circuit, connect with the PWM sample circuit, and each sampling number value of input is respectively controlled the meter
Numerical value turns corresponding one or more digit-control resistance in potential circuit, and each digit-control resistance is connected to form a ratio circuit, so that institute
State that count value turns the output voltage of potential circuit and the duty ratio of the input signal is in a linear relationship.
2. turning the circuit of voltage for pwm signal as described in claim 1, which is characterized in that the PWM sample circuit includes
A pair of of counter and matched a pair of of data latches, be respectively used to each sampling number value counting, refresh storage with
And lasting output, and an input PWM cycle is counted, an input PWM cycle carries out refreshing and passes through two
PWM cycle completes a PWM sampling.
3. turning the circuit of voltage for pwm signal as claimed in claim 1 or 2, which is characterized in that the PWM sample circuit
Include:
First counter, one end are connect with the output end of the first NAND gate module, and the other end is defeated with the first data latches
Enter end to connect, the first counter output high level sampling number buffer value to first data latches, described in output
High level sampling number value；
Phase inverter, one end are connect with input signal, and the other end is connect with the input terminal of the second NAND gate module；
Second counter, one end are connect with the output end of the second NAND gate module, the other end and the second data latches
Input terminal connection, second counter exports low level sampling number buffer value to second data latches, output
The low level sampling number value；
The high level sampling number buffer value be at the signal-count period and the input signal be high level when, pass through institute
State input signal enable the first NAND gate module and sampled clock signal pass through the first NAND gate module trigger institute
The numerical value that the first counter counts to get is stated, the input signal closes the second NAND gate mould by the phase inverter at this time
Block, second counter stop counting；
The low level sampling number buffer value be at the signal-count period and the input signal be low level when, pass through institute
It states input signal and closes the first NAND gate module so that first counter stops counting and the input signal is logical
It crosses the phase inverter and enables the second NAND gate module and sampled clock signal and triggered by the second NAND gate module
The numerical value that second counter counts to get.
4. turning the circuit of voltage for pwm signal as claimed in claim 3, which is characterized in that the frequency dividing of the input signal
It is the signal-count period between the high period of signal PWMX2, is a signal between the low period of the fractional frequency signal PWMX2
It is the signal-count period between the low period of the fractional frequency signal PWMX2 of refresh cycle or the input signal, described point
It is a signal refresh cycle between the high period of frequency signal PWMX2；
In the signal refresh cycle, the failing edge or rising edge of the fractional frequency signal of the input signal are by certain time
It is generated after delay and refreshes reset signal, the rising edge for refreshing reset signal or failing edge trigger the high level sampling number
Buffer value and the low level sampling number buffer value are stored in first data latches and second data latches, brush
High level sampling number value during new high level and the low level sampling number value between low period, and the refreshing resets
The failing edge or rising edge of signal trigger the reset of first counter and second counter.
5. turning the circuit of voltage for pwm signal as described in claim 1, which is characterized in that the count value turns voltage electricity
Road is internally provided with by corresponding the first digit-control resistance and the second digit-control resistance adjusted of each sampling number value；
First digit-control resistance and second digit-control resistance are connected in series；
Second digit-control resistance first end ground connection, second end are connected with the first end of first digit-control resistance, and described the
The second end of one digit-control resistance connects a reference voltage, and first digit-control resistance and the second digit-control resistance connected node
As output voltage；
When first digit-control resistance matches and second digit-control resistance and the height with the low level sampling number value
When level sampling time values match, the output voltage and the high level duty ratio of the input signal are in a linear relationship；Alternatively,
When first digit-control resistance matches and second digit-control resistance and the low level with the high level sampling number value
When sampling number value matches, the output voltage and the low level duty ratio of the input signal are in a linear relationship.
6. turning the circuit of voltage for pwm signal as claimed in claim 5, which is characterized in that first digit-control resistance and
Second digit-control resistance is resistance string, and the resistance string includes the resistance that several are serially connected, the high level sampling
Secondary numerical value and low level sampling number value are more than one bit number, the resistance number of bit digit and corresponding digit-control resistance
It is identical.
7. such as the circuit described in claim 5 or 6 for turning voltage for pwm signal, which is characterized in that each resistance is parallel with
The list of one switching circuit, the high level sampling number value or low level sampling number value and each switching circuit input terminal
Bit controls signal connection, and when the control signal controls switching circuit open circuit, the resistance value of corresponding resistance is included in resistance string
Resistance value, when the control signal controls the switching circuit short circuit, the resistance value of corresponding resistance is not counted in the resistance value of resistance string；
The resistance value of each resistance successively increases one times in sequence in the resistance string, when the digit-control resistance is by corresponding sampling time
When resistance total value after numerical value adjusting is equal to the product of the smallest resistance value and the sampling number value in resistance string, the count value
Turn the output voltage of potential circuit and the high level of the input signal or low level duty ratio are in a linear relationship.
8. turning the circuit of voltage for pwm signal as claimed in claim 1 or 2, which is characterized in that the PWM sample circuit
Include:
First counter, one end are connect with the output end of the first NAND gate module, and the other end is defeated with the first data latches
Enter end connection, first counter output high level sampling number buffer value or low level sampling number buffer value to described the
One data latches export the high level sampling number value or the low level sampling number value；
Second counter, one end are connect with the output end of the second NAND gate module, the other end and the second data latches
Input terminal connection, sampling number buffer value to second data that second counter exports entire PWM cycle latch
Device exports the sampling number value of the entire PWM cycle；
The high level sampling number buffer value be at the signal-count period and the input signal be high level when, pass through institute
State input signal enable the first NAND gate module and sampled clock signal pass through the first NAND gate module trigger institute
State the numerical value that the first counter counts to get；It is described defeated when in the signal-count period and when the input signal is low level
Enter the first NAND gate module described in signal-off, first counter stops counting；
The sampling number buffer value of the entire PWM cycle is to believe in the fractional frequency signal when the input signal as another input
Number when and the input signal fractional frequency signal be high level or low level when, by the fractional frequency signal enable described second with it is non-
Door module and sampled clock signal trigger the numerical value that second counter counts to get by the second NAND gate module；
When the fractional frequency signal of the input signal is low level or high level, which closes the second NAND gate module,
Second counter stops counting.
9. turning the circuit of voltage for pwm signal as claimed in claim 8, which is characterized in that the frequency dividing of the input signal
It is the signal-count period between the high period of signal PWMX2, is a signal between the low period of the fractional frequency signal PWMX2
It is the signal-count period between the low period of the fractional frequency signal PWMX2 of refresh cycle or the input signal, described point
It is a signal refresh cycle between the high period of frequency signal PWMX2；
In the signal refresh cycle, the failing edge or rising edge of the fractional frequency signal of the input signal are by certain time
It is generated after delay and refreshes reset signal, the rising edge for refreshing reset signal or failing edge triggering high level sampling number buffering
Value or low level sampling number buffer value and the sampling number buffer value of the entire PWM cycle are stored in the first data lock respectively
Storage and the second data latches realize the high level sampling number value or the low level sampling number value and described whole
The refreshing of the sampling number value of a PWM cycle；The failing edge for refreshing reset signal or rising edge triggering described first count
The reset of device and second counter guarantees the correct movement in next signal sampling period.
10. the circuit as claimed in claim 1 or 8 for turning voltage for pwm signal, which is characterized in that the count value turns electricity
Volt circuit is internally provided with by the first digit-control resistance and third digit-control resistance of the sampling number value adjusting of the entire PWM cycle
And the second digit-control resistance and the 4th numerical control by the high level sampling number value or low level sampling number value adjusting
Resistance；
The first end of first digit-control resistance is grounded, and second end is connected with the negative input end of an operational amplifier；Described
The output voltage of the first termination operational amplifier of two digit-control resistances, the negative input of second end and the operational amplifier
End is connected；First termination reference voltage of the third digit-control resistance, the positive input terminal of second end and the operational amplifier
It is connected；The first end of 4th digit-control resistance is grounded, and second end is connected with the positive input terminal of the operational amplifier；
The output voltage and the high level duty ratio or low level duty ratio of the input signal are in a linear relationship.
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