CN205582927U - Multicore piece is taken more and is loaded in mixture tiling clamp core packaging structure - Google Patents
Multicore piece is taken more and is loaded in mixture tiling clamp core packaging structure Download PDFInfo
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- CN205582927U CN205582927U CN201521103164.3U CN201521103164U CN205582927U CN 205582927 U CN205582927 U CN 205582927U CN 201521103164 U CN201521103164 U CN 201521103164U CN 205582927 U CN205582927 U CN 205582927U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to a multicore piece is taken more and is loaded in mixture tiling clamp core packaging structure, it includes first lead frame (21), second lead frame (22), first chip (23) and second chip (26), first chip (23) and second chip (26) press from both sides and establish between first lead frame (21) and second lead frame (22), first chip (24) the back and second chip (26) openly dispose respectively in on first lead frame (21), first lead frame (21) and second lead frame (22) outer plastic envelope material (25) of having sealed, first lead frame (21) lower surface exposes outside plastic envelope material (25). The beneficial effects of the utility model are that: have lower encapsulation resistance and package inductance, have better thermal diffusivity, whole piece product integrated into one piece, production efficiency is high.
Description
Technical field
This utility model relates to a kind of multi-chip and takes more and load in mixture tiling sandwich encapsulating structure, belongs to technical field of semiconductor encapsulation.
Background technology
In recent years, along with electronic product pursuit continuous to power density, either Diode(diode) or the encapsulation of Transistor (audion), the MOS product in especially Transistor just towards greater power, smaller szie, more rapid, more preferable trend of dispelling the heat in development.Encapsulation disposable manufacture also by single encapsulation technology slowly towards zonule even larger area high density highly difficult low cost disposable encapsulation technology spurt with challenge.
Therefore, the various electrical properties, the structure of encapsulation, the dissipation of heat sexuality of encapsulation, the reliability aspect of encapsulation and the highly difficult disposable encapsulation technology aspect that MOS product are also encapsulated in the resistance of parasitism, electric capacity, inductance etc. have had more requirement.
Traditional Diode(diode) and Transistor(audion) or the encapsulation of MOS product is general according to product attribute, the difference of power and the Consideration of cost, make use of the bonding wire mode of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thus realize electrical connection.But there is restriction and the defect of the following aspects to the performance of product in the technical approach of bonding wire:
One, the restriction with manufacture view and defect are encapsulated:
1), Weldability (Bondability) aspect: the first solder joint that usually can cause because of the parameter sheet change of Metal wire material, the change of metal pins material and equipment and instrument, performance and the change of precision and maintenance and correction management and the rosin joint of the second solder joint faying face, come off, puzzlement that breakpoint, cervical region crack, collapse line and short circuit etc. are all, yield cannot promote, cost cannot decline, the instability of reliability to result in encapsulation；
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode be nearly all use single one chips of chips to repeat load in matrix type die-attach area, the welding manner of high temperature ultrasonic single line single line adopted by tinsel.And in the case of so either the palikinesia at a high speed again of the loader of specialty, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium strip machine or copper sheet overlapping machine all cannot improving production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the unstability also improving manufacture that speed of production is same.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(audion) or the encapsulating products of MOS, it is typically all and is coated with by plastic packaging material, external pin is only stayed to be exposed to outside plastic-sealed body, owing to plastic packaging material itself is not the material of a kind of thermal conductance, so traditional Diode(diode) and Transistor(audion) or the packaging body of the very difficult plastic packaging material material that dissipates by plastic packaging material of MOS product operationally produced heat, fine tinsel can only be relied on to be interconnected at metal pins material to help the dissipation of heat energy, but the approach of this dissipation of heat is very limited amount of to the dissipation capability of heat, form the resistance of the dissipation of heat on the contrary；
2), resistivity (Resistivity) aspect: resistivity (resistivity) is used to indicate that the physical quantity of various material resistance characteristic as you know.In the case of temperature is certain, having formula R=ρ l/s ρ therein is exactly resistivity, and l is the length of material, and s is area.It can be seen that the resistance sizes of material is proportional to the length of material, and it is inversely proportional to its area.The definition of resistivity: ρ=Rs/l is understood by above formula.Traditional Diode (diode) and Transistor(audion) or the encapsulating products of MOS, bonding wire is used to form interconnection, thus can be apparent from tinsel for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, especially apply the product impact in terms of power the most obvious.
For solving the problems referred to above, industry is to traditional Diode(diode) and Transistor(audion) or the encapsulating products of MOS is improved, replace bonding wire with metal tape, metal splint, reduce packaged resistance, inductance and expectation and improve the ability of the dissipation of heat.
As it is shown in figure 1, be a kind of existing MOS encapsulating structure, in this structure, lead frame 11 comprises pipe core welding disc and pin, implants first chip the 12, second chip 13 on the pipe core welding disc of lead frame 11.The source electrode of the first chip 12 is electrically coupled to lead frame 11 by the first metal splint 14, and the grid of the first chip 12 is electrically coupled to lead frame 11 by the first metal wire 16.The source electrode of the second chip 13 is electrically coupled to lead frame 11 by the second metal splint 15, and the grid of the second chip 13 is electrically coupled to lead frame 11 by the second metal wire 17.Carry out again encapsulating, cut, the subsequent handling such as test.This MOS encapsulating structure metal splint instead of the bonding wire in conventional MOS encapsulation, reduce partial encapsulation resistance, but still there is following defect: first, drain electrode, source electrode and the grid of this MOS encapsulating structure chips forms interconnection from lead frame to use different equipment respectively, processing procedure is complicated, and the acquisition cost of equipment is higher；Secondly, this MOS encapsulating structure, when metal splint and metal wire are coupled on chip and pin, can only be carried out by a chips, it is impossible to whole piece is one-body molded, manufactures inefficient.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of multi-chip to take for above-mentioned prior art to load in mixture tiling sandwich encapsulating structure more, its technique is simple, production cost is relatively low, there is relatively low packaged resistance and package inductance, there is preferable thermal diffusivity, whole piece product can be one-body molded, and production efficiency is high.
nullThe technical scheme in the invention for solving the above technical problem is: more a kind of multi-chip is taken and loaded in mixture tiling sandwich encapsulating structure，It includes the first lead frame、Second lead frame、First chip and the second chip，Described second lead frame includes horizontal segment on first、First middle linkage section、First time horizontal segment、Horizontal segment on second、Second middle linkage section and second time horizontal segment，Described first chip and the second chip are folded on the first of the first lead frame and the second lead frame on horizontal segment and second between horizontal segment respectively，Described first chip back and the second chip front side are respectively arranged on described first lead frame，The front and back of described first chip is respectively by horizontal segment and the electric connection of the first lead frame on the first of tin cream and the second lead frame，The back side of the second chip and front are respectively by horizontal segment and the electric connection of the first lead frame on the second of tin cream and the second lead frame，Described first lead frame and the second lead frame outer encapsulating have plastic packaging material，Described first lead frame lower surface is exposed to outside plastic packaging material，First time horizontal segment lower surface and second time horizontal segment lower surface of described second lead frame ride upon on the first lead frame upper surface respectively.
The material of described first lead frame and the second lead frame can be alloyed copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
Described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip can being combined with metallic tin.
Compared with prior art, the utility model has the advantage of:
1, more a kind of multi-chip of this utility model is taken and is loaded in mixture the second lead frame of tiling sandwich encapsulating structure source electrode and grid directly with MOS chip and be electrically connected, instead of the technique utilizing metal wire to form interconnection in conventional MOS chip package, substantially reducing packaged resistance, technology of the present utility model can reduce more than at least 30% than the packaged resistance of conventional package design；
2, a kind of multi-chip of this utility model take more load in mixture tiling sandwich encapsulating structure the second lead frame be directly electrically connected by source electrode and the grid of tin cream with MOS chip, reduce or remit the interconnection operation of metal wire completely, save the metal wire interconnection cost such as the equipment purchasing of operation, operation material completely.And the second lead frame of the present utility model is that whole piece is integrated, be electrically connected with chip is also that whole piece one step completes, interconnecting chip one by one to be formed compared with the technique of interconnection with conventional metals bonding wire, sheet metal, technique is relatively simple, and production efficiency is significantly improved；
3, more a kind of multi-chip of the present utility model is taken and is loaded in mixture tiling sandwich encapsulating structure and all directly contact with lead frame due to upper and lower two surfaces of chip, the heat produced during chip operation can be shed by lead frame, and the first lead frame lower surface of the present utility model is directly exposed to outside plastic packaging material, more multi-chip of the present utility model is taken and is loaded in mixture tiling sandwich encapsulating structure and have preferable heat dispersion；And this utility model can be again according to product power, heat conduction or the difference of heat radiation additional radiator on lead frame freely, in order to increase the ability of the product dissipation of heat further；
4, more a kind of multi-chip of the present utility model is taken and is loaded in mixture tiling sandwich encapsulating structure and use upper lower platen to push down general frame to carry out Reflow Soldering, framework is difficult to when Reflow Soldering by tin cream by the cohesion institute jack-up of the cooling procedure after thermal melting, ensure the total height of frame structure, prevent movement or the rotation of chip, and can ensure that framework exposes the coplanarity of outer foot.
Accompanying drawing explanation
Fig. 1 is a kind of known MOS encapsulating structure schematic diagram.
Fig. 2 is that a kind of multi-chip of this utility model takes the side view loading in mixture tiling sandwich encapsulating structure more.
Fig. 3 (a) to Fig. 3 (h) is that a kind of multi-chip of this utility model takes the flow chart loading in mixture tiling sandwich encapsulating structure process more.
Wherein:
Lead frame 11
First chip 12
Second chip 13
First metal splint 14
Second metal splint 15
First metal wire 16
Second metal wire 17
First lead frame 21
Second lead frame 22
Horizontal segment 221 on first
First middle linkage section 222
First time horizontal segment 223
Horizontal segment 224 on second
Second middle linkage section 225
Second time horizontal segment 226
First chip 23
Tin cream 24
Plastic packaging material 25
Second chip 26.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, this utility model is described in further detail.
nullSee Fig. 2，More this utility model one multi-chip is taken and is loaded in mixture tiling sandwich encapsulating structure，It includes the first lead frame 21、Second lead frame 22、First chip 23 and the second chip 26，Described second lead frame 22 includes horizontal segment 221 on first、First middle linkage section 222、First time horizontal segment 223、Horizontal segment 224 on second、Second middle linkage section 225 and second time horizontal segment 226，Described first chip 23 and the second chip 26 are folded on the first of the first lead frame 21 and the second lead frame 22 on horizontal segment 221 and second between horizontal segment 224 respectively，Described first chip 23 back side and the second chip 26 front are respectively arranged on described first lead frame，The front and back of described first chip 23 is electrically connected with by horizontal segment 221 on tin cream 24 and the first of the second lead frame 22 and the first lead frame 21 respectively，The back side of the second chip 26 and front are electrically connected with by horizontal segment 224 on tin cream 24 and the second of the second lead frame 22 and the first lead frame 21 respectively，Described first lead frame 21 and the second lead frame 22 outer encapsulating have plastic packaging material 25，Described first lead frame 21 lower surface is both exposed to outside plastic packaging material 25，First time horizontal segment 223 lower surface and second time horizontal segment 226 lower surface of described second lead frame 22 ride upon on the first lead frame 21 upper surface respectively.
Described first lead frame 21 and the second lead frame 22 are general frame, and its material can be alloyed copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to be the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
Described first chip 23 and the second chip 26 are two pole piece sheets, three pole piece sheets or the multipole chip can being combined with metallic tin.
Its process is as follows:
Step one, see Fig. 3 (a), it is provided that the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to be the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope；
Step 2, see Fig. 3 (b), by the way of screen printing, tin cream is coated in the first lead frame Ji Dao region, purpose is that the area of thickness and opening by adjusting web plate can be accurately controlled the thickness of tin cream, area and position in order to realize follow-up first implanted chip Hou Yuji island joint；
Step 3, see Fig. 3 (c), step 2 is implanted the first chip and the second chip, the first chip back and the second chip front side respectively by tin cream and the electric connection of the first lead frame on the tin cream of the first lead frame Ji Dao region coating；
Step 4, see Fig. 3 (d), second lead frame is provided, second lead frame includes horizontal segment on first, the first middle linkage section, first time horizontal segment, horizontal segment, the second middle linkage section and second time horizontal segment on second, the material of the second lead frame is alloy copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to be the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.On the first of the second lead frame horizontal segment lower surface, first time horizontal segment lower surface, horizontal segment lower surface and second time horizontal segment lower surface coat tin cream by the way of screen printing on second, the area of thickness and opening by adjusting web plate can be accurately controlled the thickness of tin cream, area and position；
Step 5, see Fig. 3 (e), horizontal segment on horizontal segment and second on the first of second lead frame is pressed together on the first chip and second chip of the first lead frame upper surface respectively, the first chip and the second chip is made to be electrically connected by the tin cream of horizontal segment lower surface on horizontal segment lower surface and second on first with the second lead frame respectively, and second lead frame first time horizontal segment lower surface and second time horizontal segment lower surface ride upon on the first lead frame upper surface respectively, after pressing, the first lead frame and the second lead frame form general frame；
Step 6, see Fig. 3 (f), the general frame upper and lower surface pressing plate that step 5 is formed is pushed down, carries out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C；
Step 7, see Fig. 3 (g), use plastic packaging material to carry out plastic packaging step 6 general frame after Reflow Soldering；
Step 8, seeing Fig. 3 (h), the semi-finished product that step 7 completes plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, prepare multi-chip and take tiling sandwich encapsulating structure more.
In above-mentioned steps, step 2 and step 4 can be carried out by different platform simultaneously.
In addition to the implementation, this utility model also includes the technical scheme that other embodiments, all employing equivalents or equivalence substitute mode are formed, within all should falling into this utility model scope of the claims.
Claims (3)
- null1. more a multi-chip is taken and is loaded in mixture tiling sandwich encapsulating structure，It is characterized in that: it includes the first lead frame (21)、Second lead frame (22)、First chip (23) and the second chip (26)，Described second lead frame (22) includes horizontal segment on first (221)、First middle linkage section (222)、First time horizontal segment (223)、Horizontal segment (224) on second、Second middle linkage section (225) and second time horizontal segment (226)，Described first chip (23) and the second chip (26) are folded on the first of the first lead frame (21) and the second lead frame (22) on horizontal segment (221) and second between horizontal segment (224) respectively，Described first chip (23) back side and the second chip (26) front are respectively arranged on described first lead frame，The front and back of described first chip (23) passes through horizontal segment (221) and the first lead frame (21) on tin cream (24) and the first of the second lead frame (22) respectively and is electrically connected with，The back side of the second chip (26) and front are passed through horizontal segment (224) and the first lead frame (2) 1 on tin cream (24) and the second of the second lead frame (22) respectively and are electrically connected with，Described first lead frame (21) and the second lead frame (22) outer encapsulating have plastic packaging material (25)，Described first lead frame (21) lower surface is both exposed to outside plastic packaging material (25)，First time horizontal segment (223) lower surface and second time horizontal segment (226) lower surface of described second lead frame (22) ride upon on the first lead frame (21) upper surface respectively.
- More a kind of multi-chip the most according to claim 1 is taken and is loaded in mixture tiling sandwich encapsulating structure, it is characterized in that: described first lead frame and the second lead frame are general frame, its material can be alloyed copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to is 8*10^-6/ DEG C for other CTE scope The conductive material of ~ 25*10^-6/ DEG C.
- More a kind of multi-chip the most according to claim 1 is taken and is loaded in mixture tiling sandwich encapsulating structure, it is characterised in that: described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip can being combined with metallic tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521103164.3U CN205582927U (en) | 2015-12-24 | 2015-12-24 | Multicore piece is taken more and is loaded in mixture tiling clamp core packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521103164.3U CN205582927U (en) | 2015-12-24 | 2015-12-24 | Multicore piece is taken more and is loaded in mixture tiling clamp core packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205582927U true CN205582927U (en) | 2016-09-14 |
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