CN205582490U - Large capacity static RAM - Google Patents
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- CN205582490U CN205582490U CN201620302566.4U CN201620302566U CN205582490U CN 205582490 U CN205582490 U CN 205582490U CN 201620302566 U CN201620302566 U CN 201620302566U CN 205582490 U CN205582490 U CN 205582490U
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Abstract
The utility model relates to a large capacity static RAM, it connects formation to the order from bottom to top by an overall input and output modules and a plurality of memory group, decoding circuit's input address chaining is arrived on the corresponding address wire in each memory group, the memory is organized by a spine bone module and is set up the sub - static RAM module connection formation in the spine bone module left and right sides respectively, formation is connected by the local input and output modules and a plurality of memory macroblock that set up from bottom to top to sub - static RAM module, spine bone module by an inputoutput data cushion, address buffering and decoding module to and the horizontal interconnected module of a plurality of data addresss connection of equalling divide setting both sides about inputoutput data buffering, address buffering and decoding module forms, couple together with vertical metal the horizontal metal of connecting inputoutput data in the horizontal interconnected module of each data address through punching from bottom to top along spine bone pair of module linea angulata direction.
Description
Technical field
This utility model relates to SRAM field, is specially a kind of Large Copacity static random storage
Device.
Background technology
In current SOC(system on a chip) SOC and microprocessor, the area of SRAM accounts for whole
The ratio of chip area is very big, and by 2016, this ratio was already close to 90%.For some
The application of HD video, it usually needs the SRAM of megabit level is as data buffer storage.
Traditional SRAM compiler uses overall situation imput output circuit and multiple static random to deposit
Reservoir macroblock directly produces jumbo SRAM by the mode of metal wire splicing.Due to gold
Time constant RC belonging to line becomes quadratic relationship with the length of metal wire, along with the grand mould of SRAM
The increase of the capacity of block, is used for connecting multiple SRAM macroblock and overall situation imput output circuit
Metal wire can be more and more longer, time constant RC of metal wire also increases sharply, by the time of metal wire
Propagation delay caused by constant RC increase also increases sharply, and this is for requiring that quickly accessing time delay answers
With being unacceptable.
Utility model content
For problems of the prior art, this utility model provides a kind of Large Copacity static random storage
Device, it is possible to the propagation delay avoiding longer metal wire band wire, improves overall SRAM
Performance, it is ensured that the demand quickly accessed.
This utility model is to be achieved through the following technical solutions:
A kind of Large Copacity SRAM, by an overall input/output module and multiple memorizer group
From bottom to top to the formation that is linked in sequence；In each memorizer group, the input address of decoding circuit is connected to phase
In the address wire answered；Described memorizer group is by a spine module and is separately positioned on a spine module left side
The sub-SRAM module of right both sides connects formation；Two sub-SRAM modules are with ridge
The geometric center of bone module is centrosymmetric setting；Described sub-SRAM module by from lower and
One local input output module of upper setting and multiple memory macro module connect formation；Described spine
Module is buffered by an inputoutput data, address buffer and decoding module, and divides equally and be arranged on input
The horizontal interconnection module of some data addresses of the upper and lower both sides of data output buffer, address buffer and decoding module
Connect and formed；The quantity of the horizontal interconnection module of data address is equal to the bit wide of this Large Copacity random access memory；
Horizontal for each data address interconnection module will connect input from bottom to top along spine module diagonal
Transverse metal and the longitudinal metal of output data are coupled together by punching；Described inputoutput data delays
Punching, address buffer and decoding module are by an address command buffering and decoding module, and divide equally and be arranged on
Some inputoutput data buffer sublayer modules of address command buffering and the decoding module left and right sides connect shape
Become；The quantity of inputoutput data buffer sublayer module is equal to the bit wide of this Large Copacity random access memory；Described
The horizontal interconnection module of data address by address command interconnection submodule, and divide equally and be arranged on address
Some inputoutput datas interconnection submodule of the order interconnection submodule left and right sides connects formation；Input defeated
Go out the quantity bit wide equal to this Large Copacity random access memory of data interconnection submodule.
Preferably, described local input output module is by a local address order submodule, Yi Jijun
The some local input output data submodule being arranged on the local address order submodule left and right sides is divided to connect
Formed；The quantity of local input output data submodule is equal to the bit wide of this Large Copacity random access memory.
Preferably, described inputoutput data interconnection submodule includes an input of laterally homogeneous setting
Data wire and an output data line, two input data lines being longitudinally uniformly arranged and two output data
Line, and input data line connects lead to the hole site labelling VIA_Q and an output data line connects
Lead to the hole site labelling VIA_D.
Preferably, address command interconnection submodule includes an input data line and of laterally homogeneous setting
Bar output data line, and the address command line that a plurality of longitudinal direction is uniformly arranged.
Preferably, inputoutput data buffer sublayer module includes the input data buffering of separate setting
The a plurality of local address order wire of device, output data selector, and laterally homogeneous setting；Described is defeated
Enter data buffer to be made up of three buffers, input termination input data D of the first buffer, defeated
Go out termination internal input data D_INT；Second buffer input connects internal input data D_INT,
Output termination top input data D_INT_T；3rd buffer input connects internal input data
D_INT, output connects bottom input data D_INT_B；Described output data selector is by alternative
Selector, strong phase inverter and weak phase inverter composition；Two inputs of alternative selector connect local defeated respectively
Go out data Q_INT0 and local output data Q_INT1, select to control termination selector and select signal
MUX_SEL, output termination output data Q；Strong phase inverter and the cross-linked connection of weak phase inverter
The input of this locality output data Q_INT1 is connected at alternative selector.
Preferably, described local address order wire includes that selector selects signal MUX_SEL, local
Address AD D, local output enables anti-OEN, local clock pulses CLK, and local sheet enables anti-
CEN and the anti-WEN of locally-written enable.
Preferably, described address command buffering and decoding module include decoding circuit, are arranged on decoding electricity
The global address command input buffer of road input, and it is separately positioned on the signal input of decoding circuit
End and the local address commands buffer of outfan.
Compared with prior art, this utility model has a following useful technique effect:
This utility model is by adding buffer when data address interconnects, by long metal interconnection wire
It is divided into a plurality of shorter metal interconnection wire, thus avoids the mistake caused owing to macroblock capacity increases
The data address that long metal wire causes propagates the deterioration of time delay, improves Large Copacity SRAM
Performance.During splicing, the input address of decoding circuit middle in each memorizer group is connected to accordingly
In address wire, thus realize carrying out sheet by global address and select the function of respective memory group.
Accompanying drawing explanation
Fig. 1 be a kind of Large Copacity random access memory described in this utility model example structure composition signal and
It forms flow chart.
Fig. 2 is the structure chart of a local input output module described in this utility model example.
Fig. 3 is the structure chart of an inputoutput data interconnection submodule described in this utility model example.
Fig. 4 is the structure chart of an address command interconnection submodule described in this utility model example.
Fig. 5 is the structure chart of an inputoutput data buffer sublayer module described in this utility model example.
Fig. 6 is an address command buffering described in this utility model example and the structure chart of decoding module.
Detailed description of the invention
Below in conjunction with specific embodiment, this utility model is described in further detail, described in be to this
The explanation of utility model rather than restriction.
This utility model one Large Copacity SRAM, as it is shown in figure 1, it is defeated by an overall situation
Enter output module 113 and multiple memorizer group 112 from bottom to top to the formation that is linked in sequence；Each storage
In device group 112, the input address of decoding circuit 620 is connected in corresponding address wire.
Wherein, memorizer group 112 by a spine module 110 and is separately positioned on spine module 110
The sub-SRAM module 103 of the left and right sides connects formation；Two sub-SRAM moulds
Block 103 is centrosymmetric setting with the geometric center of spine module 110；Sub-SRAM module
103 by the local input output module 102 arranged from bottom to top and multiple memory macro module 101
Connect and formed；Spine module 110 is buffered by an inputoutput data, address buffer and decoding module
109, and divide equally and be arranged on inputoutput data buffering, address buffer and decoding module about 109 two
Some data addresses horizontal interconnection module 106 of side connects formation；The horizontal interconnection module of data address 106
Quantity equal to the bit wide of this Large Copacity random access memory；Along spine module 110 diagonal from lower and
On horizontal for each data address interconnection module 106 will connect the transverse metal of inputoutput data and vertical
Coupled together by punching to metal；Inputoutput data buffering, address buffer and decoding module 109 by
One address command buffering and decoding module 108, and divide equally and be arranged on address command buffering and decoding mould
Some inputoutput data buffer sublayer modules 107 of block 108 left and right sides connect formation；Input and output number
Quantity according to buffer sublayer module 107 is equal to the bit wide of this Large Copacity random access memory；Data address is the most mutual
Gang mould block 106 is by address command interconnection submodule 105, and divides equally and be arranged on address command interconnection
Some inputoutput datas interconnection submodule 104 of submodule 105 left and right sides connects formation；Input defeated
Go out the quantity bit wide equal to this Large Copacity random access memory of data interconnection submodule 104.
As in figure 2 it is shown, local input output module 102 is by a local address order submodule 201,
And divide equally the some local input output data being arranged on local address order submodule 201 left and right sides
Submodule 200 connects formation；Local input output data submodule 200 quantity equal to this Large Copacity with
The bit wide of machine memorizer.
As it is shown on figure 3, inputoutput data interconnection submodule 104 includes that of laterally homogeneous setting is defeated
Enter data wire 304 and an output data line 305, two input data lines being longitudinally uniformly arranged
300,301 and two output data lines 302,303, and an input data line connects lead to the hole site
Labelling VIA_Q and an output data line connect lead to the hole site labelling VIA_D.
As shown in Figure 4, address command interconnection submodule 105 includes an input number of laterally homogeneous setting
According to line 304 and an output data line 305, and the address command line 400-that a plurality of longitudinal direction is uniformly arranged
407。
As it is shown in figure 5, inputoutput data buffer sublayer module 107 includes the input number of separate setting
Order according to a plurality of local address of buffer 150, output data selector 151, and laterally homogeneous setting
Make line 520；Input Data Buffer 150 is made up of three buffers, the input of the first buffer 500
Termination input data D 503, output termination internal input data D_INT 504；Second buffer 501
Input termination internal input data D_INT 504, output termination top input data D_INT_T 505；
3rd buffer 502 input termination internal input data D_INT 504, output connects bottom input data
D_INT_B 506；Output data selector 151 is by alternative selector 510, strong phase inverter 511 He
Weak phase inverter 512 forms；Two inputs of alternative selector 510 connect local output data respectively
Q_INT0513 and local output data Q_INT1514, select to control termination selector and select signal
MUX_SEL 515, output termination output data Q 516；Strong phase inverter 511 and weak phase inverter 512 are handed over
The alternative selector 510 that is connected to of fork coupling connects the input of local output data Q_INT1 514
End.Wherein, local address order wire 520 includes that selector selects signal MUX_SEL, local address
ADD, local output enables anti-OEN, local clock pulses CLK, local sheet enable anti-CEN and
The anti-WEN of locally-written enable.
As shown in Figure 6, address command buffering and decoding module 108 include decoding circuit 620, are arranged on
The global address command input buffer 600 of decoding circuit 620 input, and it is separately positioned on decoding
The signal input part of circuit 620 and the local address commands buffer 640,660 of outfan.
When making, the forming step of this utility model a kind of Large Copacity random access memory, such as Fig. 1 institute
Show, comprising:
The first step, a local input output module 102 and multiple memory macro module 101 are from bottom to top
Sub-SRAM module 103 is formed to sequential concatenation；
Second step, 1/2 bit wide inputoutput data interconnection submodule 104, an address command interconnection
Submodule 105,1/2 bit wide inputoutput data interconnection submodule 104, order the most from left to right
It is spliced to form the horizontal interconnection module of data address 106；
3rd step, 1/2 bit wide inputoutput data buffer sublayer module 107, an address command buffering
And decoding module 108,1/2 bit wide inputoutput data buffer sublayer module 107, the most from left to right
Sequential concatenation forms inputoutput data buffering, address buffer and decoding module 109；
4th step, the 1/2 horizontal interconnection module of bit wide data address 106, an inputoutput data delays
Punching, address buffer and decoding module 109, the 1/2 horizontal interconnection module of bit wide data address 106 are under oneself
Spine module 110 is formed to upper sequential concatenation.When splicing, from bottom to top, to each data ground
The horizontal interconnection module in location 106 is positioned at the spine module 110 lead to the hole site from lower-left to upper right diagonal
VIA_D, VIA_Q punch, and are closed by remaining lead to the hole site, connect the horizontal stroke of inputoutput data
To metal and longitudinal metal；Concrete diagonal is as shown in the dotted line position in the 4th step in Fig. 1；
5th step, is turned over the sub-SRAM module 103 turning 90 degrees counterclockwise by one, one
Spine module 110, one is turned over the sub-SRAM module 111 turning 90 degrees transversely clockwise
Sequential concatenation forms memorizer group 112 from left to right；Diagonal described in step 4 the most from bottom to top by
Turn over sub-SRAM module 103 side turning 90 degrees counterclockwise to turning over the son turning 90 degrees clockwise
The diagonal of SRAM module 111, as shown in the dotted line position in the 5th step in Fig. 1；
6th step, an overall input/output module 113 and multiple memorizer group 112 are from bottom to top to suitable
Sequence is spliced to form a kind of jumbo SRAM；During splicing, store at each from bottom to top
Corresponding position punching in device group 112, as shown in Figure 6, by the input address of wherein decoding circuit 620
S2, S1 are connected to corresponding address wire BA_N_T<1>, BA_T<1>, BA_N_T<2>,
BA_T<2>on, i.e. carry out sheet by global address BA<2:1>and select respective memory group.Such as Fig. 6 institute
Showing, concrete hole knockout is as follows, for first memorizer group, to VIA_S1_BA_N<1>,
VIA_S2_BA_N<2>punching, by S1 and BA_N_T<1>, S2 and BA_N_T<2>connect
Come, and by remaining bore closure；For second memorizer group, to VIA_S1_BA<1>,
VIA_S2_BA_N<2>punching, by S1 and BA_T<1>, S2 and BA_N_T<2>connect
Come, and by remaining bore closure；For the 3rd memorizer group, to VIA_S1_BA_N<1>,
VIA_S2_BA<2>punching, by S1 and BA_N_T<1>, S2 and BA_T<2>couple together, and
By remaining bore closure；For the 4th memorizer group, to VIA_S1_BA<1>, VIA_S2_BA<2>
Punching, by S1 and BA_T<1>, S2 and BA_T<2>couple together, and by remaining bore closure.
As in figure 2 it is shown, Fig. 2 is a local input output module example.Its forming method is as follows, by
1/2 bit wide local input output data submodule 200, a local address order submodule 201,
1/2 bit wide local input output data submodule 200, sequential concatenation forms this most from left to right
Ground input/output module 102.
As it is shown on figure 3, Fig. 3 is an inputoutput data interconnection submodule example.Including, a horizontal stroke
To input data line 304, the output data line 305 of a horizontal line, the input data line of two longitudinal directions
300,301, the output data line 302,303 of two longitudinal directions, and position at Q and
The input data line of Q_INT0 intersection connect lead to the hole site labelling VIA_Q and position at D and
The output data line of D_INT0 intersection connects lead to the hole site labelling VIA_D.In splicing spine module
When 110, from bottom to top, interconnection module 106 horizontal to each data address is positioned at spine module
Lead to the hole site VIA_D, VIA_Q punching in 110 clinodiagonals, and remaining lead to the hole site is closed
Close, connect transverse metal and the longitudinal metal of inputoutput data.
As shown in Figure 4, Fig. 4 is an address, order interconnection submodule example.Including, one is laterally
Input data line 304, the output data line 305 of a horizontal line, a plurality of longitudinal address, order wire
400-407。
As it is shown in figure 5, Fig. 5 is an inputoutput data buffer sublayer module instance.Including, a plurality of horizontal stroke
To local address, order wire 520, Input Data Buffer 150 and output data selector 151.
Local address, order wire 520 include, local address ADD, and local clock pulses CLK is locally-written
Enabling anti-WEN, local output enables anti-OEN, and local sheet enables anti-CEN, and selector selects letter
Number MUX_SEL.Input Data Buffer 150 is made up of three buffer 500-502.Buffer
500 inputs connect input data D 503, and output connects internal input data D_INT 504.Buffer 501
Input connects internal input data D_INT 504, and output connects top input data D_INT_T 505.Buffering
Device 502 input connects internal input data D_INT 504, and output connects bottom input data D_INT_B
506.Output data selector 151 is by alternative selector 510, and two cross-linked anti-phase
Device, strong phase inverter 511, weak phase inverter 512 forms.Two inputs of alternative selector 510 are respectively
Connect local output data 0,Q_I,NT0 513, local output data 1,Q_I,NT1 514, select to control end
Meeting MUX_SEL 515, output connects output data Q 516.
As shown in Figure 6, Fig. 6 is an address command buffering and decoding module example.Including, globally
Location command input buffer 600, decoding circuit 620, local address commands buffer 640,660, with
And decoding circuit input address connects through hole labelling.Decoding circuit input address connects through hole labelling and includes:
It is positioned at the VIA_S1_BA_N<1 of S1 and BA_N<1>intersection>, it is positioned at S1 and BA<1>intersection
VIA_S1_BA<1>, be positioned at the VIA_S2_BA_N<2 of S2 and BA_N<2>intersection>, be positioned at
The VIA_S2_BA<2 of S2 and BA<2>intersection>.Global address command input buffer 600 is by delaying
Rush device 601-610 composition.Input is global address order 611, high-order anti-including group address
BA_N<2>, the high-order positive BA<2 of group address>, the high-order anti-BA_N<1 of group address time>and, group address is second highest
The positive BA<1 in position>, group address low level positive BA<0>, group address low-clock signal CLK, local address
ADD, chip selection signal CE, write enable anti-CEN, group address low level anti-BA_N<0>.It is output as top
Portion's address command 612, including top group address high anti-BA_N_T<2>, top group address high is just
BA_T<2>, the high-order anti-BA_N_T<1 in top group address time>, a top group address time high position is just
BA_T<1>, top group address low level positive BA_T<0>, top clock signal CLK_T, top
Address AD D_T, top chip selection signal CE_T, top write enables anti-CEN_T, and top group address is low
Position anti-BA_N_T<0>.
Decoding circuit 620 is inputted and doors 621 by two, just along d type flip flop 622, and buffer 623, three
Input and door 624, just along d type flip flop 625, three inputs and door 626, just along d type flip flop 627 groups
Become.Two inputs connect group address highest order S2 631 respectively with two inputs of door 621, and group address is second highest
Position S1 630, output connects just along data input pin and three input and the doors 624,626 of d type flip flop 622
One input 632.The just data input pin along d type flip flop 622 connects 632, and input end of clock connects top
Portion's clock signal clk _ T, output data connect 633.The input of buffer 623 connects just along d type flip flop
The output 633 of 622, output connects the input 634 of buffer 644,664.Three inputs and the three of door 624
Individual input connects the outfan 632 of two inputs and door 621 respectively, and top group address low level is just
BA_T<0>, top chip selection signal CE_T, output connect just along d type flip flop 625 input data terminal and
The input 635 of buffer 643.The just input data along d type flip flop 625 terminate three input and doors
The outfan 635 of 624, input end of clock connects top clock signal CLK_T, output data termination buffering
The input 636 of device 642.Three inputs input with the three of door 626 and connect the defeated of two inputs and door 621 respectively
Go out end 632, top group address low level anti-BA_T_N<0>, top chip selection signal CE_T, output just connects
Input data terminal and the input 637 of buffer 663 along d type flip flop 627.Just along d type flip flop
Input data termination three input of 627 and the outfan 637 of door 626, input end of clock connects top clock
Signal CLK_T, the input 638 of output data termination buffer 662.
Local address commands buffer 640 is made up of buffer 641-647.Buffer 641-647's is defeated
Enter to connect respectively top write and enable anti-WEN_T, just along the outfan 636 of d type flip flop 625, three inputs
The outfan 635 of NAND gate 624, the outfan 634 of buffer 623, top clock signal
CLK_T, top local address signal ADD_T.The output of buffer 641-647 connects signal 650,
Including, left part this locality anti-WEN_L of write enable signal, it is anti-that the output of left part this locality enables signal
OEN_L, left part this locality anti-CEN_L of chip selection signal, left part selector selects signal anti-
MUX_SEL_L, left part local clock pulses CLK_L and left part local address signal ADD_L.
Local address commands buffer 650 is made up of buffer 661-667.Buffer 661-667's is defeated
Enter to connect respectively top write and enable anti-WEN_T, just along the outfan 638 of d type flip flop 627, three inputs
The outfan 637 of NAND gate 627, the outfan 636 of buffer 625, top clock signal
CLK_T, top local address signal ADD_T.The output of buffer 661-667 connects signal 670,
Including, right part this locality anti-WEN_R of write enable signal, it is anti-that the output of right part this locality enables signal
OEN_R, right part this locality anti-CEN_R of chip selection signal, right part selector selects signal anti-
MUX_SEL_R, right part local clock pulses CLK_R and right part local address signal ADD_R.
Claims (7)
1. a Large Copacity SRAM, it is characterised in that by an overall input/output module
And multiple memorizer group (112) is from bottom to top to the formation that is linked in sequence (113)；Each memorizer group
(112) in, the input address of decoding circuit (620) is connected in corresponding address wire；
Described memorizer group (112) is by a spine module (110) and is separately positioned on spine mould
The sub-SRAM module (103) of block (110) left and right sides connects formation；Two sons are static
Ram module (103) is centrosymmetric setting with the geometric center of spine module (110)；
Described sub-SRAM module (103) is by the local input arranged from bottom to top
Output module (102) and multiple memory macro module (101) connect formation；
Described spine module (110) is buffered by an inputoutput data, address buffer and decoding mould
Block (109), and divide equally and be arranged on inputoutput data buffering, address buffer and decoding module
(109) the horizontal interconnection module of some data addresses (106) of both sides connect formation up and down；Data address
Laterally the quantity of interconnection module (106) is equal to the bit wide of this Large Copacity random access memory；Along spine module
(110) diagonal will connect in horizontal for each data address interconnection module (106) from bottom to top
Transverse metal and the longitudinal metal of inputoutput data are coupled together by punching；
Described inputoutput data buffering, address buffer and decoding module (109) are ordered by an address
Order buffering and decoding module (108), and divide equally be arranged on address command buffering and decoding module
(108) some inputoutput datas buffer sublayer module (107) of the left and right sides connect formation；Input defeated
Go out the quantity bit wide equal to this Large Copacity random access memory of data buffering submodule (107)；
The horizontal interconnection module of described data address (106) is by an address command interconnection submodule
(105), and divide equally be arranged on address command interconnection submodule (105) left and right sides some inputs
Output data interconnection submodule (104) connects formation；Inputoutput data interconnection submodule (104)
Quantity is equal to the bit wide of this Large Copacity random access memory.
A kind of Large Copacity SRAM the most according to claim 1, it is characterised in that institute
The local input output module (102) stated is by local address order submodule (201), Yi Jijun
Divide some local input output data being arranged on local address order submodule (201) left and right sides
Module (200) connects formation；The quantity of local input output data submodule (200) is equal to this great Rong
The bit wide of amount random access memory.
A kind of Large Copacity SRAM the most according to claim 1, it is characterised in that institute
Inputoutput data interconnection submodule (104) stated includes an input data line of laterally homogeneous setting
(304) and one output data line (305), two input data lines being longitudinally uniformly arranged (300,
301) and two output data line (302,303), and an input data line connection lead to the hole site mark
Note VIA_Q and an output data line connect lead to the hole site labelling VIA_D.
A kind of Large Copacity SRAM the most according to claim 1, it is characterised in that ground
Location order interconnection submodule (105) includes an input data line (304) and of laterally homogeneous setting
Bar output data line (305), and the address command line (400-407) that a plurality of longitudinal direction is uniformly arranged.
A kind of Large Copacity SRAM the most according to claim 1, it is characterised in that defeated
Enter data output buffer submodule (107) and include the Input Data Buffer of separate setting
(150), output data selector (151), and a plurality of local address order wire of laterally homogeneous setting
(520)；
Described Input Data Buffer (150) is made up of three buffers, the first buffer (500)
Input termination input data D (503), output termination internal input data D_INT (504)；The
Two buffers (501) input termination internal input data D_INT (504), the top input of output termination
Data D_INT_T (505)；3rd buffer (502) input termination internal input data D_INT
(504), output connects bottom input data D_INT_B (506)；
Described output data selector (151) is by alternative selector (510), strong phase inverter
(511) form with weak phase inverter (512)；Two inputs of alternative selector (510) connect respectively
Local output data Q_INT0 (513) and local output data Q_INT1 (514), select to control end
Connect selector and select signal MUX_SEL (515), output termination output data Q (516)；Strong anti-
Phase device (511) and the cross-linked alternative selector (510) that is connected to of weak phase inverter (512) connect
Connect the input of local output data Q_INT1 (514).
A kind of Large Copacity SRAM the most according to claim 1, it is characterised in that institute
The local address order wire (520) stated includes that selector selects signal MUX_SEL, local address
ADD, local output enables anti-OEN, local clock pulses CLK, local sheet enable anti-CEN and
The anti-WEN of locally-written enable.
A kind of Large Copacity SRAM the most according to claim 1, it is characterised in that institute
The address command buffering stated and decoding module (108) include decoding circuit (620), are arranged on decoding electricity
The global address command input buffer (600) of road (620) input, and it is separately positioned on decoding
The signal input part of circuit (620) and the local address commands buffer (640,660) of outfan.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810240A (en) * | 2016-04-12 | 2016-07-27 | 西安紫光国芯半导体有限公司 | High-capacity SRAM (static random access memory) and production method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810240A (en) * | 2016-04-12 | 2016-07-27 | 西安紫光国芯半导体有限公司 | High-capacity SRAM (static random access memory) and production method thereof |
| CN105810240B (en) * | 2016-04-12 | 2018-08-21 | 西安紫光国芯半导体有限公司 | A kind of large capacity Static RAM and its production method |
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