A kind of SHF wave band miniature microwave diplexer
Technical field
This utility model relates to a kind of duplexer, particularly a kind of SHF wave band miniature microwave diplexer.
Background technology
In recent years, along with the developing rapidly of miniaturization of mobile communication, satellite communication and Defensive Avionics System,
High-performance, low cost and miniaturization have become as the developing direction of microwave current/RF application, to microwave duplex
The performance of device, size, reliability and cost are all had higher requirement.The master of this component capabilities is described
Index is wanted to have: passband operating frequency range, stop band frequency range, pass band insertion loss, stopband attenuation, logical
Tape input/output voltage standing-wave ratio, insert phase shift and delay/frequency characteristic, temperature stability, volume, weight,
Reliability etc..
LTCC is a kind of Electronic Encapsulating Technology, uses multi-layer ceramics technology, it is possible to by passive element
Being built in inside medium substrate, active component can also be mounted on substrate surface makes passive/active collection simultaneously
The functional module become.LTCC technology is at cost, integration packaging, wiring live width and distance between centers of tracks, low impedance metal
Change, design diversity and the aspect such as motility and high frequency performance all show many merits, it has also become passive collection
The mainstream technology become.It has high q-factor, it is simple to embedded passive device, and thermal diffusivity is good, and reliability is high, resistance to
High temperature, rushes the advantages such as shake, utilizes LTCC technology, can well process size little, and precision is high, closely
Type is good, and little microwave device is lost.Owing to LTCC technology has the integrated advantage of 3 D stereo, at microwave frequency band
It is widely used for manufacturing various microwave passive components, it is achieved passive element highly integrated.Based on LTCC technique
Stack technology, it is possible to achieve three-dimensionally integrated so that various micro microwave filter have size little, weight
Amount is light, performance is excellent, reliability is high, batch production performance concordance is good and the plurality of advantages such as low cost, utilization
Its three-dimensionally integrated construction features, it is possible to achieve miniature microwave diplexer.
Utility model content
The purpose of this utility model is to provide a kind of SHF wave band miniature microwave diplexer, and employing LTCC technology will
Two microwave filters link together, it is achieved volume is little, lightweight, reliability is high, excellent electrical property,
Easy to use, applied widely, yield rate is high, concordance is good in batches, cost is low, temperature performance is stable
Miniature microwave diplexer.
For achieving the above object, this utility model is by the following technical solutions:
A kind of SHF wave band miniature microwave diplexer, including match circuit M, the first microwave filter F1 and the
Two microwave filter F2;
Match circuit M include input port P1, first input inductance Lin1, the first matched line L1, second
Distribution L2 and earth terminal, the first matched line L1 connects the second matched line L2 by the first input inductance Lin1,
Described first input inductance Lin1 is also connected with input port P1, the first microwave filter F1 and the second microwave
Wave filter F2 is respectively arranged on the left and right sides of match circuit M;
First microwave filter F1 includes the second input inductance Lin2, first order parallel resonance unit, the second level
Parallel resonance unit, third level parallel resonance unit, fourth stage parallel resonance unit, the first Z-shaped intersection coupling
Close electric capacity Z1, the second Z-shaped cross coupling capacitor Z2, the first outputting inductance Lout1, the first output port P2
And earth terminal, described first microwave filter F1 is located on 5 layers of circuit substrate, described 5 layers of circuit base
Plate be sequentially provided with from top to bottom the first cross coupling capacitor layer, the first loading capacitance layer, the second inductance resonant layer,
3rd loads capacitor layers and the second cross coupling capacitor layer, and the first output port P2 is located at described 5 layers of circuit base
The left side of plate, first order parallel resonance unit, second level parallel resonance unit, third level parallel resonance unit
It is disposed on the most successively on described 5 layers of circuit substrate with fourth stage parallel resonance unit, a Z
Shape cross coupling capacitor Z1 is located on the first cross coupling capacitor layer, and the second Z-shaped cross coupling capacitor Z2 sets
On the second cross coupling capacitor layer, described first Z-shaped cross coupling capacitor Z1 and described second Z-shaped intersection
The equal ground connection in coupling electric capacity Z2 two ends;
First order parallel resonance unit includes strip line L11, strip line L21 and strip line L31, strip line L11
Being located on the first loading capacitance layer, strip line L21 is located on the second inductance resonant layer, and described strip line
L21 is located at the underface of described strip line L11, and strip line L31 is located at the 3rd loading capacitor layers, and described
Strip line L31 is located at the underface of described strip line L21;
Second level parallel resonance unit includes strip line L12, strip line L22 and strip line L32, strip line L12
Being located on the first loading capacitance layer, strip line L22 is located on the second inductance resonant layer, and described strip line
L32 is located at the underface of described strip line L12, and strip line L32 is located at the 3rd loading capacitor layers, and described
Strip line L32 is located at the underface of described strip line L22;
Third level parallel resonance unit includes strip line L13, strip line L23 and strip line L33, strip line L13
Being located on the first loading capacitance layer, strip line L23 is located on the second inductance resonant layer, and described strip line
L33 is located at the underface of described strip line L13, and strip line L33 is located at the 3rd loading capacitor layers, and described
Strip line L33 is located at the underface of described strip line L23;
Fourth stage parallel resonance unit includes strip line L14, strip line L24 and strip line L34, strip line L14
Being located on the first loading capacitance layer, strip line L24 is located on the second inductance resonant layer, and described strip line
L34 is located at the underface of described strip line L14, and strip line L34 is located at the 3rd loading capacitor layers, and described
Strip line L34 is located at the underface of described strip line L24;
Described strip line L24 connects the first output port P2, strip line L21 by the first outputting inductance Lout1
The first matched line L1, strip line L11, strip line L12, strip line is connected by the second input inductance Lin2
L13 and strip line L14 is ground connection rear end, front end open circuit;Strip line L21, strip line L22, strip line L23
It is ground connection front end, rear end open circuit with strip line L24;Strip line L31, strip line L32, strip line L33 and
Strip line L34 is ground connection rear end, front end open circuit;
Second microwave filter F2 include the 3rd input inductance Lin3, level V parallel resonance unit, the 6th grade
Parallel resonance unit, the 7th grade of parallel resonance unit, the 8th grade of parallel resonance unit, the second outputting inductance
Lout2, the 3rd Z-shaped cross coupling capacitor Z3, the 4th Z-shaped cross coupling capacitor Z4, the second output port
P3 and earth terminal;
Second microwave filter F2 is located on 4 layers of circuit substrate, and described 4 layers of circuit substrate are from top to bottom
It is sequentially provided with the 3rd cross coupling capacitor layer, the 4th loading capacitance layer, the 3rd inductance resonant layer and the 4th intersection
Coupling capacitor layers, the second output port P3 is located at the right side of described 4 layers of circuit substrate, level V parallel resonance
Unit, the 6th grade of parallel resonance unit, the 7th grade of parallel resonance unit and the 8th grade of parallel resonance unit are from a left side
Being disposed on successively on described 4 layers of circuit substrate to the right side, the 3rd Z-shaped cross coupling capacitor Z3 is located at the 3rd
On cross coupling capacitor layer, the 4th Z-shaped cross coupling capacitor Z4 is located on the 4th cross coupling capacitor layer;The
Three Z-shaped cross coupling capacitor Z3 and the 4th equal ground connection in Z-shaped cross coupling capacitor Z4 two ends;
Level V parallel resonance unit includes that strip line L41 and strip line L51, strip line L41 are located at the 4th and add
Carrying in capacitor layers, strip line L51 is located on the 3rd inductance resonant layer, and described strip line L51 is located at institute
State the underface of strip line L41;
6th grade of parallel resonance unit includes that strip line L42 and strip line L52, strip line L42 are located at the 4th and add
Carrying in capacitor layers, strip line L52 is located on the 3rd inductance resonant layer, and described strip line L52 is located at institute
State the underface of strip line L42;
7th grade of parallel resonance unit includes that strip line L43 and strip line L53, strip line L43 are located at the 4th and add
Carrying in capacitor layers, strip line L53 is located on the 3rd inductance resonant layer, and described strip line L53 is located at institute
State the underface of strip line L43;
8th grade of parallel resonance unit includes that strip line L44 and strip line L54, strip line L44 are located at the 4th and add
Carrying in capacitor layers, strip line L54 is located on the 3rd inductance resonant layer, and described strip line L54 is located at institute
State the underface of strip line L44;
Described strip line L54 connects the second output port P3, strip line L51 by the second outputting inductance Lout2
The second matched line L2 is connected by the 3rd input inductance Lin3;Strip line L41, strip line L42, strip line
L43 and strip line L44 is ground connection rear end, front end open circuit;Strip line L51, strip line L52, strip line L53
It is ground connection front end, rear end open circuit with strip line L54.
Described input port P1, output port P2 and output port P3 are surface-pasted 50 ohmages
Port.
Described a kind of SHF wave band miniature microwave diplexer uses multilamellar LTCC technique to make.
A kind of SHF wave band miniature microwave diplexer described in the utility model, uses LTCC technology micro-by two
Wave filter links together, it is achieved volume is little, lightweight, reliability is high, excellent electrical property, user
Just, applied widely, that yield rate is high, concordance is good in batches, cost is low, temperature performance is stable is miniature micro-
Wave duplexer;This utility model uses multilamellar LTCC technique to realize, its low-temperature co-burning ceramic material
Sinter at a temperature of about 900 DEG C with metallic pattern and form, so having extreme high reliability and temperature stabilization
Property, owing to structure uses, 3 D stereo is integrated to be grounded with multilayer folding structure and outer surface metallic shield
And encapsulation, so that volume significantly reduces.
Accompanying drawing explanation
Fig. 1 is the contour structures schematic diagram of this utility model a kind of SHF wave band miniature microwave diplexer;
Fig. 2 is profile and the inside of match circuit in this utility model a kind of SHF wave band miniature microwave diplexer
Structural representation;
Fig. 3 is the profile of the first microwave filter in this utility model a kind of SHF wave band miniature microwave diplexer
And internal structure schematic diagram;
Fig. 4 is the profile of the second microwave filter in this utility model a kind of SHF wave band miniature microwave diplexer
And internal structure schematic diagram;
Fig. 5 is the amplitude-frequency characteristic of this utility model a kind of SHF wave band miniature microwave diplexer the first output port
Curve;
Fig. 6 is the amplitude-frequency characteristic of this utility model a kind of SHF wave band miniature microwave diplexer the second output port
Curve;
Fig. 7 is the stationary wave characteristic curve of this utility model a kind of SHF wave band miniature microwave diplexer input port.
Detailed description of the invention
A kind of SHF wave band miniature microwave diplexer as shown in Figure 1, including match circuit M, the first microwave filter
Ripple device F1 and the second microwave filter F2;
Match circuit M as shown in Figure 2 includes input port P1, the first input inductance Lin1, the first coupling
Line L1, the second matched line L2 and earth terminal, the first matched line L1 connects the by the first input inductance Lin1
Two matched line L2, described first input inductance Lin1 are also connected with input port P1, the first microwave filter
F1 and the second microwave filter F2 is respectively arranged on the left and right sides of match circuit M;
The first microwave filter F1 as shown in Figure 3 includes the second input inductance Lin2, first order parallel resonance
Unit, second level parallel resonance unit, third level parallel resonance unit, fourth stage parallel resonance unit,
One Z-shaped cross coupling capacitor Z1, the second Z-shaped cross coupling capacitor Z2, the first outputting inductance Lout1,
One output port P2 and earth terminal, described first microwave filter F1 is located on 5 layers of circuit substrate,
Described 5 layers of circuit substrate be sequentially provided with from top to bottom the first cross coupling capacitor layer, the first loading capacitance layer,
Second inductance resonant layer, the 3rd loading capacitor layers and the second cross coupling capacitor layer, the first output port P2 sets
In the left side of described 5 layers of circuit substrate, first order parallel resonance unit, second level parallel resonance unit,
Three grades of parallel resonance unit and fourth stage parallel resonance unit are disposed on described 5 layers of electricity the most successively
On base board, the first Z-shaped cross coupling capacitor Z1 is located on the first cross coupling capacitor layer, the second Z-shaped friendship
Fork coupling electric capacity Z2 be located on the second cross coupling capacitor layer, described first Z-shaped cross coupling capacitor Z1 and
The described second equal ground connection in Z-shaped cross coupling capacitor Z2 two ends;
First order parallel resonance unit includes strip line L11, strip line L21 and strip line L31, strip line L11
Being located on the first loading capacitance layer, strip line L21 is located on the second inductance resonant layer, and described strip line
L21 is located at the underface of described strip line L11, and strip line L31 is located at the 3rd loading capacitor layers, and described
Strip line L31 is located at the underface of described strip line L21;
Second level parallel resonance unit includes strip line L12, strip line L22 and strip line L32, strip line L12
Being located on the first loading capacitance layer, strip line L22 is located on the second inductance resonant layer, and described strip line
L32 is located at the underface of described strip line L12, and strip line L32 is located at the 3rd loading capacitor layers, and described
Strip line L32 is located at the underface of described strip line L22;
Third level parallel resonance unit includes strip line L13, strip line L23 and strip line L33, strip line L13
Being located on the first loading capacitance layer, strip line L23 is located on the second inductance resonant layer, and described strip line
L33 is located at the underface of described strip line L13, and strip line L33 is located at the 3rd loading capacitor layers, and described
Strip line L33 is located at the underface of described strip line L23;
Fourth stage parallel resonance unit includes strip line L14, strip line L24 and strip line L34, strip line L14
Being located on the first loading capacitance layer, strip line L24 is located on the second inductance resonant layer, and described strip line
L34 is located at the underface of described strip line L14, and strip line L34 is located at the 3rd loading capacitor layers, and described
Strip line L34 is located at the underface of described strip line L24;
Described strip line L24 connects the first output port P2, strip line L21 by the first outputting inductance Lout1
The first matched line L1, strip line L11, strip line L12, strip line is connected by the second input inductance Lin2
L13 and strip line L14 is ground connection rear end, front end open circuit;Strip line L21, strip line L22, strip line L23
It is ground connection front end, rear end open circuit with strip line L24;Strip line L31, strip line L32, strip line L33 and
Strip line L34 is ground connection rear end, front end open circuit;
The second microwave filter F2 as shown in Figure 4 includes the 3rd input inductance Lin3, level V parallel resonance
Unit, the 6th grade of parallel resonance unit, the 7th grade of parallel resonance unit, the 8th grade of parallel resonance unit,
Two outputting inductance Lout2, the 3rd Z-shaped cross coupling capacitor Z3, the 4th Z-shaped cross coupling capacitor Z4,
Two output port P3 and earth terminals;
Second microwave filter F2 is located on 4 layers of circuit substrate, and described 4 layers of circuit substrate are from top to bottom
It is sequentially provided with the 3rd cross coupling capacitor layer, the 4th loading capacitance layer, the 3rd inductance resonant layer and the 4th intersection
Coupling capacitor layers, the second output port P3 is located at the right side of described 4 layers of circuit substrate, level V parallel resonance
Unit, the 6th grade of parallel resonance unit, the 7th grade of parallel resonance unit and the 8th grade of parallel resonance unit are from a left side
Being disposed on successively on described 4 layers of circuit substrate to the right side, the 3rd Z-shaped cross coupling capacitor Z3 is located at the 3rd
On cross coupling capacitor layer, the 4th Z-shaped cross coupling capacitor Z4 is located on the 4th cross coupling capacitor layer;The
Three Z-shaped cross coupling capacitor Z3 and the 4th equal ground connection in Z-shaped cross coupling capacitor Z4 two ends;
Level V parallel resonance unit includes that strip line L41 and strip line L51, strip line L41 are located at the 4th and add
Carrying in capacitor layers, strip line L51 is located on the 3rd inductance resonant layer, and described strip line L51 is located at institute
State the underface of strip line L41;
6th grade of parallel resonance unit includes that strip line L42 and strip line L52, strip line L42 are located at the 4th and add
Carrying in capacitor layers, strip line L52 is located on the 3rd inductance resonant layer, and described strip line L52 is located at institute
State the underface of strip line L42;
7th grade of parallel resonance unit includes that strip line L43 and strip line L53, strip line L43 are located at the 4th and add
Carrying in capacitor layers, strip line L53 is located on the 3rd inductance resonant layer, and described strip line L53 is located at institute
State the underface of strip line L43;
8th grade of parallel resonance unit includes that strip line L44 and strip line L54, strip line L44 are located at the 4th and add
Carrying in capacitor layers, strip line L54 is located on the 3rd inductance resonant layer, and described strip line L54 is located at institute
State the underface of strip line L44;
Described strip line L54 connects the second output port P3, strip line L51 by the second outputting inductance Lout2
The second matched line L2 is connected by the 3rd input inductance Lin3;Strip line L41, strip line L42, strip line
L43 and strip line L44 is ground connection rear end, front end open circuit;Strip line L51, strip line L52, strip line L53
It is ground connection front end, rear end open circuit with strip line L54.
Described input port P1, output port P2 and output port P3 are surface-pasted 50 ohmages
Port.
Described a kind of SHF wave band miniature microwave diplexer uses multilamellar LTCC technique to make.
As shown in Figure 5-Figure 7, the size of a kind of SHF of this utility model wave band miniature microwave diplexer is 7.2mm
×2mm×1.5mm.Two passbands of duplexer are respectively 3.4GHz-3.8GHz and 4.9GHz-5.9GHz, defeated
Inbound port return loss is better than 13dB, and output port insertion loss is better than 1.8dB.
A kind of SHF wave band miniature microwave diplexer described in the utility model, uses LTCC technology micro-by two
Wave filter links together, it is achieved volume is little, lightweight, reliability is high, excellent electrical property, user
Just, applied widely, that yield rate is high, concordance is good in batches, cost is low, temperature performance is stable is miniature micro-
Wave duplexer;This utility model uses multilamellar LTCC technique to realize, its low-temperature co-burning ceramic material
Sinter at a temperature of about 900 DEG C with metallic pattern and form, so having extreme high reliability and temperature stabilization
Property, owing to structure uses, 3 D stereo is integrated to be grounded with multilayer folding structure and outer surface metallic shield
And encapsulation, so that volume significantly reduces.