CN205488191U - LED chip of parallelly connected structure - Google Patents
LED chip of parallelly connected structure Download PDFInfo
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- CN205488191U CN205488191U CN201620193713.9U CN201620193713U CN205488191U CN 205488191 U CN205488191 U CN 205488191U CN 201620193713 U CN201620193713 U CN 201620193713U CN 205488191 U CN205488191 U CN 205488191U
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Abstract
The utility model discloses a LED chip of parallelly connected structure, which comprises a substrate, P electrode and N electrode on being located the epitaxial structure on the substrate and being located the epitaxial structure, the epitaxial structure includes N type semiconductor layer in proper order, luminescent layer and P type semiconductor layer, a serial communication port, be formed with a plurality of shield grooves between the epitaxial structure, a plurality of isolation regions of formation are kept apart by the shield groove to the epitaxial structure, the shield groove includes the first shield groove and the second shield groove of sculpture to N type semiconductor layer of sculpture to substrate, the second septum leaves the trench in the region that first isolation marge was established, the N electrode be arranged in the second septum from the inslot and with the N type semiconductor layer of every isolation region electric connection respectively, the P electrode be arranged in first shield groove and with the P type semiconductor layer of every isolation region electric connection respectively. The utility model discloses a parallelly connected structure can make the electric current evenly distributed of LED chip, has reduced electrode and pin to a light absorption, increases the light -emitting of lateral wall, the luminous luminance that has improved the LED chip.
Description
Technical field
This utility model relates to technical field of semiconductor luminescence, particularly relates to the LED chip of a kind of parallel-connection structure.
Background technology
Light emitting diode (Light-Emitting Diode, LED) is a kind of semiconductor electronic component that can be luminous.This electronic component occurred as far back as 1962, can only send the HONGGUANG of low-light level in early days, develop other monochromatic versions afterwards, and the light that can send even to this day is throughout visible ray, infrared ray and ultraviolet, and brightness also brings up to suitable brightness.And purposes is also by the beginning as display lamp, display panel etc.；Along with the continuous progress of technology, light emitting diode has been widely used in display, has decorated and illuminate.
LED chip structure is divided into formal dress, upside-down mounting, vertical three kinds of structures at present, and currently assembling structure is that use is most.For the LED chip of positive assembling structure, along with LED chip becomes large-sized, in order to reduce voltage increase brightness, prior art is generally realized by the increase of electrode pin, but the electrode pin being to increase is unfavorable for chip light-emitting, reduces the luminosity of LED.
Therefore, for above-mentioned technical problem, it is necessary to provide the LED chip of a kind of parallel-connection structure.
Utility model content
The purpose of this utility model is to provide the LED chip of a kind of parallel-connection structure, is effectively increased the luminosity of LED chip.
To achieve these goals, the technical scheme that this utility model embodiment provides is as follows:
A kind of LED chip of parallel-connection structure, described LED chip includes substrate, the epitaxial structure being positioned on substrate and the P electrode being positioned on epitaxial structure and N electrode, described epitaxial structure includes n type semiconductor layer successively, luminescent layer and p type semiconductor layer, some isolation channels it are formed with between described epitaxial structure, epitaxial structure is formed some isolation areas by the isolation of described isolation channel, described isolation channel includes the first isolation channel being etched to substrate and is etched to the second isolation channel of n type semiconductor layer, described second isolation channel is positioned at the first isolation channel and encloses the region set, described N electrode is positioned at described second isolation channel and is electrically connected with the n type semiconductor layer in each isolation area, described P electrode is positioned at the first isolation channel and is electrically connected with the p type semiconductor layer in each isolation area.
As further improvement of the utility model, described epitaxial structure also includes the transparency conducting layer being positioned on p type semiconductor layer, and the shape of described transparency conducting layer is identical with the shape of p type semiconductor layer.
As further improvement of the utility model, also including current barrier layer in described LED chip, described current barrier layer is positioned at the first isolation channel, and described P electrode is entirely located on described current barrier layer.
As further improvement of the utility model, described LED chip also includes the first pad being electrically connected with described N electrode and the second pad being electrically connected with described P electrode.
As further improvement of the utility model, described LED chip also includes that protective layer, described protective layer at least cover described isolation area, and described first pad and the second pad are positioned at the unlapped region of protective layer.
As further improvement of the utility model, described isolation area rectangular array is distributed, and the first isolation channel is between adjacent lines isolation area and LED chip exterior lateral area, and the second isolation channel is between adjacent column isolation area.
The beneficial effects of the utility model are:
This utility model is by isolating epitaxial structure in multiple isolation areas, realize the LED chip of multiple isolation areas parallel-connection structure, structure can make the balanced current distribution of LED chip in parallel, decrease the absorption to going out light of electrode and pin, increase sidewall goes out light, improves the luminosity of LED chip.
Accompanying drawing explanation
In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is only some embodiments described in this utility model, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the planar structure schematic diagram of parallel-connection structure LED chip in this utility model one detailed description of the invention；
Fig. 2 is the sectional structure schematic diagram in Fig. 1 at parallel-connection structure LED chip A-A；
Fig. 3 is the schematic diagram that in this utility model one detailed description of the invention, single LEDs chip is divided into parallel-connection structure LED chip；
Fig. 4 a ~ 4f is the manufacturing approach craft block diagram of parallel-connection structure LED chip in this utility model one detailed description of the invention.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in this utility model, below in conjunction with the accompanying drawing in this utility model embodiment, technical scheme in this utility model embodiment is clearly and completely described, obviously, described embodiment is only a part of embodiment of this utility model rather than whole embodiments.Based on the embodiment in this utility model, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, all should belong to the scope of this utility model protection.
The utility model discloses the LED chip of a kind of parallel-connection structure, this LED chip includes substrate, the epitaxial structure being positioned on substrate and the P electrode being positioned on epitaxial structure and N electrode, epitaxial structure includes n type semiconductor layer successively, luminescent layer and p type semiconductor layer, some isolation channels it are formed with between epitaxial structure, epitaxial structure is formed some isolation areas by isolation channel isolation, isolation channel includes the first isolation channel being etched to substrate and is etched to the second isolation channel of n type semiconductor layer, second isolation channel is positioned at the first isolation channel and encloses the region set, N electrode is positioned at described second isolation channel and is electrically connected with the n type semiconductor layer in each isolation area, P electrode is positioned at the first isolation channel and is electrically connected with the p type semiconductor layer in each isolation area.
Shown in ginseng Fig. 1, Fig. 2, in a detailed description of the invention of the present utility model, the LED chip 100 of parallel-connection structure includes successively:
Substrate 10, substrate can be sapphire, Si, SiC, GaN, ZnO etc.；
N type semiconductor layer 20, n type semiconductor layer can be N-type GaN etc.；
Luminescent layer 30, luminescent layer can be GaN, InGaN etc.；
P type semiconductor layer 40, p type semiconductor layer can be p-type GaN etc.；
N electrode 50 and P electrode 60, N electrode 50 is arranged on n type semiconductor layer 20, and is electrically connected with n type semiconductor layer 20, and P electrode 60 is electrically connected with p type semiconductor layer 40.
Present embodiment epitaxial structures includes n type semiconductor layer 20, luminescent layer 30 and p type semiconductor layer 40, some isolation channels it are formed with between epitaxial structure, epitaxial structure isolation is formed some isolation areas by isolation channel, preferably, present embodiment arranges by three row two illustrate as a example by totally 6 isolation areas 101,102,103,104,105 and 106.
Wherein, isolation channel includes the first isolation channel 91 being etched to substrate 10 and is etched to the second isolation channel 92 of n type semiconductor layer 20, in the present embodiment, first isolation channel 91 is formed between three, outside frame and the isolation area of adjacent lines of epitaxial structure, second isolation channel 92 is formed between the isolation area of adjacent column, and second isolation channel 92 be positioned at the first isolation channel 91 and enclose the region set, epitaxial structure is separated into 6 isolation areas 101,102,103,104,105 and 106 by the first isolation channel 91 and the second isolation channel 92.
Preferably, in present embodiment, 4 isolation areas 101,102,103,104 are completely isolated above, n type semiconductor layer just below is not isolated from the second isolation channel 92, and the two of lower section isolation areas 105 and 106 are part isolation, other completely isolated or partially isolated modes can also be used in other embodiments, be the most no longer described in detail.
Further, being additionally provided with transparency conducting layer 70 in the present embodiment on p type semiconductor layer 40, the shape of transparency conducting layer is identical with the shape of P semiconductor layer 40, is also isolated groove isolation and lays respectively in each isolation area.Electrically conducting transparent 70 in present embodiment is transparent conductive layer, can also be ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In in other embodiments4Sn3O12, the transparency conducting layer such as NiAu, further, transparency conducting layer can be one layer, it is also possible to for two or more combination layer structure in above-mentioned transparency conducting layer.
Being formed with current barrier layer 80 in the first isolation channel 91 at the frame of three, the outside of epitaxial structure, current barrier layer 80 is by SiO2Being formed Deng insulant, P electrode 60 is formed at above this current barrier layer 80, and P electrode 60 is electrically connected with the transparency conducting layer 70 in each isolation area respectively, and then P electrode 60 is electrically connected with the most indirectly with p type semiconductor layer 40.By the setting of current barrier layer 80, the electric current below P electrode 60 can be stopped, improve light extraction efficiency.
Meanwhile, the n type semiconductor layer 20 in the second isolation channel 92 being formed with N electrode 50, owing to the n type semiconductor layer 20 in the second isolation channel 92 does not performs etching, therefore this N electrode 50 can be electrically connected with the n type semiconductor layer 20 in each isolation area respectively.
By the design of said structure, n type semiconductor layer 20 in each isolation area is all electrically connected with N electrode 50, P semiconductor layer 40 in each isolation area is all electrically connected with P electrode 60, therefore, the epitaxial structure in all isolation areas between P electrode and N electrode in parallel-connection structure.
Further, by epitaxial structure be provided above with N electrode 50 be electrically connected with the first pad 51 and with P electrode 60 be electrically connected with the second pad 61, can N electrode 50 and P electrode 60 be drawn by the first pad 51 and the second pad 61, the first pad 51 and the second pad 61 are as the extraction electrode of whole parallel-connection structure LED chip.
Correspondingly, the invention also discloses the manufacture method of the LED chip of a kind of parallel-connection structure, comprise the following steps:
One substrate is provided, at substrate Epitaxial growth n type semiconductor layer, luminescent layer and p type semiconductor layer, forms epitaxial structure；
Etching epitaxial structure, to substrate surface, forms the first isolation channel, and epitaxial structure isolation is formed several rows by the first isolation channel；
Etching epitaxial structure, to n type semiconductor layer, forms the second isolation channel, and epitaxial structure isolation is formed some row by the second isolation channel, and epitaxial structure is formed some isolation areas by the first isolation channel and the isolation of the second isolation channel；
Current barrier layer is formed in the first isolation channel outside epitaxial structure；
Forming N electrode in the second isolation channel, N electrode is electrically connected with the n type semiconductor layer in each isolation area；
Forming P electrode in the first isolation channel above current barrier layer, P electrode is electrically connected with p type semiconductor layer in each isolation area.
Below in conjunction with detailed description of the invention, the manufacture method of the LED chip of parallel-connection structure in this utility model is described further.
In this utility model, by epitaxial structure is isolated, single LEDs chip can be become the LED chip that multiple epitaxial structure is parallel-connection structure, as it is shown on figure 3, single LEDs chip can be become n row, the LED chip of m row parallel-connection structure, chip on substrate in (n, m) rectangular array distribution, for simplifying the manufacture method of LED chip, takes n=3 in present embodiment, m=2, arranges by 3 row 2 and illustrates as a example by the LED chip of totally 6 parallel-connection structures.
First pass through MOCVD epitaxial growth GaN epitaxial layer on a sapphire substrate, form the epitaxial structure including n type semiconductor layer, luminescent layer and p type semiconductor layer；
Using plasma etching machine that GaN epitaxial layer is carried out ICP etching technics, the dash area in Fig. 4 a is done deep etching, etches into Sapphire Substrate, form the first isolation channel 91, epitaxial structure isolation is formed several rows by the first isolation channel 91.The first isolation channel 91 in the present embodiment covers the side around epitaxial structure three side and some parts being parallel to each other and extended to centre by corresponding dual-side, meanwhile, is reserved with the second pad locations in the centre position of epitaxial structure；
Re-use plasma etching machine and GaN epitaxial layer is carried out the etching of N electrode contact area, n type semiconductor layer will be etched to by dash area in Fig. 4 b, forming the second isolation channel 92, epitaxial structure isolation is formed some row, this second isolation channel 92 i.e. N electrode contact area by the second isolation channel 92.The second isolation channel 92 in present embodiment is arranged with part the first isolation channel 91 square crossing, and epitaxial structure is isolated by the first isolation channel 91 and the second isolation channel 92 and formed some isolation areas.Meanwhile, epitaxial structure is also reserved with the first pad locations, this position is carried out with the second isolation channel 92 Tong Bu etching；
Then use the material such as silicon dioxide or silicon nitride to fill in part the first isolation channel 91 and form current barrier layer 80, shown in ginseng Fig. 4 c, dash area in current barrier layer 80 coverage diagram 4c, current barrier layer is located at least in three side edge of epitaxial structure, and current barrier layer at least extends to isolation area at one, for carrying the P electrode of correspondence；
Preferably, present embodiment is also formed with on the luminous zone of epitaxial structure transparency conducting layer 70, such as transparent conductive layer, in conjunction with Fig. 4 d by the first isolation channel 91 and isolation of the second isolation channel 92,6 outer isolation areas 101,102,103,104,105 and 106 that epitaxial structure is divided into matrix array to be distributed；
Finally carry out the making of metal electrode, the evaporation metal electrode respectively of shadow positions in figure 4e, form P electrode 60 and N electrode 50, and above N electrode 50 and P electrode 60, form the first pad 51 and the second pad 61 respectively, for corresponding electrode is drawn.
Specifically, need to form N electrode 50 in the second isolation channel 92, N electrode 50 is electrically connected with the n type semiconductor layer in each isolation area；In the first isolation channel 91, P electrode 60 also above current barrier layer, need to be formed, P electrode 60 is electrically connected with p type semiconductor layer in each isolation area, being arranged such i.e. available by the LED chip of 6 isolation area parallel-connection structures, the P semiconductor layer of each isolation area and n type semiconductor layer are electrically connected with P electrode and N electrode respectively.Finally form the first pad and the second pad more respectively in corresponding region.Certainly, in other embodiments, N electrode, P electrode and the first pad and the second pad can also be prepared in an evaporation process simultaneously, are the most no longer described in detail.
Preferably; as shown in fig. 4f; after having prepared N electrode 50, P electrode the 60, first pad 51 and the second pad 61; protective layer 110 can also be prepared on the surface of LED chip; using silicon dioxide or the transparent insulation material such as silicon nitride or aluminium sesquioxide LED chip to be protected, protective layer 110 covers all surfaces in addition to the first pad 51 and the second pad 61.
Should be understood that, above-mentioned embodiment arranges (the 3 of totally 6 isolation areas with 3 row 2,2) as a example by rectangular array, LED chip to parallel-connection structure has been described in detail, isolation area can also be the rectangular array distribution of other structures in other embodiments, as 3 row 2 arrange (the 3 of totally 6 isolation areas, 2) rectangular array etc., certainly, it can also be the array distribution of other shapes, as 3 row 3 arrange (the 3 of totally 9 isolation areas, 3) square array or other circle or oval-shaped array etc., citing illustrates the most one by one.
No matter using which kind of array, be both needed to isolate with the first isolation channel and the second isolation channel, meanwhile, P electrode and N electrode are electrically connected with the p type semiconductor layer in each isolation area and n type semiconductor layer respectively, to realize the parallel-connection structure of each isolation area.
Preferably, the first pad and the second pad are arranged at the centre position of LED chip, to realize the uniformly light-emitting of LED chip.
As can be seen from the above technical solutions, compared with prior art, this utility model is by isolating epitaxial structure in multiple isolation areas, realize the LED chip of multiple isolation areas parallel-connection structure, structure can make the balanced current distribution of LED chip in parallel, decreasing electrode and pin to going out the absorption of light, increase sidewall goes out light, improves the luminosity of LED chip.
It is obvious to a person skilled in the art that this utility model is not limited to the details of above-mentioned one exemplary embodiment, and in the case of without departing substantially from spirit or essential attributes of the present utility model, it is possible to realize this utility model in other specific forms.Therefore, no matter from the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, scope of the present utility model is limited by claims rather than described above, it is intended that all changes fallen in the implication of equivalency and scope of claim included in this utility model.Should not be considered as limiting involved claim by any reference in claim.
In addition, it is to be understood that, although this specification is been described by according to embodiment, but the most each embodiment only comprises an independent technical scheme, this narrating mode of description is only for clarity sake, description should can also be formed, through appropriately combined, other embodiments that it will be appreciated by those skilled in the art that as an entirety, the technical scheme in each embodiment by those skilled in the art.
Claims (6)
1. the LED chip of a parallel-connection structure, described LED chip includes substrate, the epitaxial structure being positioned on substrate and the P electrode being positioned on epitaxial structure and N electrode, described epitaxial structure includes n type semiconductor layer successively, luminescent layer and p type semiconductor layer, it is characterized in that, some isolation channels it are formed with between described epitaxial structure, epitaxial structure is formed some isolation areas by the isolation of described isolation channel, described isolation channel includes the first isolation channel being etched to substrate and is etched to the second isolation channel of n type semiconductor layer, described second isolation channel is positioned at the first isolation channel and encloses the region set, described N electrode is positioned at described second isolation channel and is electrically connected with the n type semiconductor layer in each isolation area, described P electrode is positioned at the first isolation channel and is electrically connected with the p type semiconductor layer in each isolation area.
The LED chip of parallel-connection structure the most according to claim 1, it is characterised in that described epitaxial structure also includes the transparency conducting layer being positioned on p type semiconductor layer, the shape of described transparency conducting layer is identical with the shape of p type semiconductor layer.
The LED chip of parallel-connection structure the most according to claim 1 and 2, it is characterised in that also include current barrier layer in described LED chip, described current barrier layer is positioned at the first isolation channel, and described P electrode is entirely located on described current barrier layer.
The LED chip of parallel-connection structure the most according to claim 1 and 2, it is characterised in that described LED chip also includes the first pad being electrically connected with described N electrode and the second pad being electrically connected with described P electrode.
The LED chip of parallel-connection structure the most according to claim 4, it is characterised in that described LED chip also includes that protective layer, described protective layer at least cover described isolation area, and described first pad and the second pad are positioned at the unlapped region of protective layer.
The LED chip of parallel-connection structure the most according to claim 1 and 2, it is characterised in that described isolation area rectangular array is distributed, the first isolation channel is between adjacent lines isolation area and LED chip exterior lateral area, and the second isolation channel is between adjacent column isolation area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620193713.9U CN205488191U (en) | 2016-03-14 | 2016-03-14 | LED chip of parallelly connected structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620193713.9U CN205488191U (en) | 2016-03-14 | 2016-03-14 | LED chip of parallelly connected structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789400A (en) * | 2016-03-14 | 2016-07-20 | 聚灿光电科技股份有限公司 | LED chip with parallel structure and production method thereof |
| CN108281523A (en) * | 2017-01-06 | 2018-07-13 | 首尔伟傲世有限公司 | Light-emitting component with current barrier layer |
| CN108428770A (en) * | 2018-04-19 | 2018-08-21 | 北京大学 | A kind of preparation method of coplanar waveguide structure micron LED |
| CN108615795A (en) * | 2018-03-27 | 2018-10-02 | 北京大学 | A kind of implementation method interconnected in micron of LED chip |
-
2016
- 2016-03-14 CN CN201620193713.9U patent/CN205488191U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789400A (en) * | 2016-03-14 | 2016-07-20 | 聚灿光电科技股份有限公司 | LED chip with parallel structure and production method thereof |
| CN105789400B (en) * | 2016-03-14 | 2018-08-14 | 聚灿光电科技股份有限公司 | A kind of LED chip and its manufacturing method of parallel-connection structure |
| CN108281523A (en) * | 2017-01-06 | 2018-07-13 | 首尔伟傲世有限公司 | Light-emitting component with current barrier layer |
| CN108615795A (en) * | 2018-03-27 | 2018-10-02 | 北京大学 | A kind of implementation method interconnected in micron of LED chip |
| CN108428770A (en) * | 2018-04-19 | 2018-08-21 | 北京大学 | A kind of preparation method of coplanar waveguide structure micron LED |
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Granted publication date: 20160817 Effective date of abandoning: 20180814 |