CN205319164U

CN205319164U - Transient voltage suppressor

Info

Publication number: CN205319164U
Application number: CN201620006794.7U
Authority: CN
Inventors: 冯亚宁; 张意远
Original assignee: Shanghai Microsemi Semiconductor Co Ltd
Current assignee: Shanghai Microsemi Semiconductor Co Ltd
Priority date: 2016-01-05
Filing date: 2016-01-05
Publication date: 2016-06-15
Anticipated expiration: 2026-01-05

Abstract

The utility model relates to a transient voltage suppressor, include: the chip body, the upper surface of the chip body is equipped with the first slot of a pair of parallel setting, first slot with the chip body is gone up and is formed the cutting region between the adjacent tip, cover and locate a grooved surface's first compound passivation layer, cover and locate chip body upper surface just is located a pair ofly last electrode metal level between the first slot, and cover and locate the bottom electrode metal level of chip body lower surface. Form the cutting in the outside of a pair of first slot regional, when cutting into the separate unit with the chip, gets rid of any potential inefficacy risk that probably produces small mechanical damage and bring, after the cutting, will cut the whole inoperatives districts that have stayed the chip of damage, makes any mechanical damage not involve the mesa of chip during operation to guarantee the excellent features of product effectively, had high reliability and stability.

Description

Transient Voltage Suppressor

Technical field

This utility model relates to semiconductor device, particularly relates to a kind of Transient Voltage Suppressor.

Background technology

In the prior art; the infringement that surge pulse produced by the transient voltage produced during for electronic devices and components in Protection control system effectively from electrostatic, inductive load switching or induced lightening brings, transient voltage suppressor diode has been widely used in the every field such as household electrical appliance, electronic instrument, communication apparatus, power supply, computer system. The weak point of transient voltage suppressor diode commercial at present is: adopt the glassy layer of simple monolayer as semiconductor device surface covering protection deielectric-coating; it is fixed and stops objectionable impurities that the heat stability after the contamination capability of device surface and encapsulation and reliability is all poor; product is made to be unable to reach good radiating effect; after temperature shock and power old mine pit; because of the impact of internal material thermal expansion coefficient difference, the life-span of product is short, it is high to eliminate ratio.

China is the composite inner passivation layer structure of transient voltage suppressor diode at first patent announcement number for CN201985106U invention and created name, although have employed in compound passivation layer as passivation protection. But by silicon chip carry out excision forming become a separate unit time, what adopt is the mode of machine cuts or cut, the damage that cutting causes is difficult to be avoided entirely in the process, and those adopt naked eyes, are all difficult to the milli machine damage of identification even under the microscope, being likely to so that chip also exists risk and the possibility of potential failure in follow-up encapsulation and use, hidden danger produced by chip cutting has severely impacted the reliability and stability of product.

Utility model content

The purpose of this utility model is in that to overcome the defect of prior art, it is provided that a kind of Transient Voltage Suppressor, it is possible to solve the problem that existing transient voltage suppressor diode cannot be avoided the damage of chip and affect the reliability and stability of product when excision forming.

The technical scheme realizing above-mentioned purpose is:

This utility model one Transient Voltage Suppressor, including:

Chip body, the upper surface of described chip body is provided with a pair parallel arrangement of first groove, forms cutting zone between the end that described first groove is adjacent with on described chip body;

Cover in the first layer compound passivation of described first flute surfaces;

Cover in described chip body upper surface and at upper electrode metal layer between the first groove described in a pair; And

Cover in the bottom electrode metal level of described chip body lower surface.

Further improvement is that of this utility model Transient Voltage Suppressor, described chip body includes monocrystal silicon body, cover in the upper doped layer of described monocrystal silicon body upper surface and cover in the lower doped layer of described monocrystal silicon body lower surface, the upper surface of described monocrystal silicon body is provided with the first groove described in a pair, and described upper doped layer is located at described in a pair between first groove.

Further improvement is that of this utility model Transient Voltage Suppressor, described upper electrode metal layer covers in the upper surface of described upper doped layer.

Further improvement is that of this utility model Transient Voltage Suppressor, described monocrystal silicon body lower surface is provided with the second corresponding with described first groove a pair groove, and described lower doped layer is located at described in a pair between second groove.

Further improvement is that of this utility model Transient Voltage Suppressor, described bottom electrode metal level covers in the lower surface of described lower doped layer.

Further improvement is that of this utility model Transient Voltage Suppressor, the surface of described second groove is covered with the second layer compound passivation.

Further improvement is that of this utility model Transient Voltage Suppressor, described second layer compound passivation includes covering the layer polysilicon film in described second flute surfaces, cover in the silicon nitride film layer of described layer polysilicon film lower surface and cover in the glass passivation layer of described silicon nitride film layer lower surface.

Further improvement is that of this utility model Transient Voltage Suppressor, described upper doped layer is N-type phosphorus interface or P type boron interface.

Further improvement is that of this utility model Transient Voltage Suppressor, described lower doped layer is N-type phosphorus interface or P type boron interface.

Further improvement is that of this utility model Transient Voltage Suppressor, described first layer compound passivation includes covering the layer polysilicon film in described first flute surfaces, covers the silicon nitride film layer on described layer polysilicon film and cover the glass passivation layer on described silicon nitride film layer.

Having the beneficial effect that of this utility model Transient Voltage Suppressor

Cutting zone is formed in the outside of a pair first grooves, when chip cutting is become separate unit, get rid of any possibility and produce the potential failure risk that milli machine damage brings, after dicing, cutting damage has all been stayed the nonclient area of chip, table top when making any mechanical damage be not related to chip operation, thus being effectively guaranteed the good characteristic of product, has high reliability and stability.

Accompanying drawing explanation

Fig. 1 is the structural representation of the first embodiment of this utility model Transient Voltage Suppressor.

Fig. 2 is the structural representation of the second embodiment of this utility model Transient Voltage Suppressor.

Detailed description of the invention

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

This utility model provides a kind of Transient Voltage Suppressor, for the double; two groove structure high reliability transient suppression device of passivation layer in the compound that a kind of characteristic good, stable performance, reliability are high. It is by being formed with cutting zone in the outside of double; two grooves, problem chip causing when effectively solving excision forming mechanical damage and affecting the reliability and stability of product. This utility model adopts the upper surface at chip body to arrange two double; two grooves arranged side by side and separated by a distance, covers layer compound passivation, device is played a protective role in double; two grooves. Transient Voltage Suppressor of the present utility model has high reliability and stability. Below in conjunction with accompanying drawing, this utility model Transient Voltage Suppressor is described in detail.

Consult Fig. 1, it is shown that the structural representation of the first embodiment of this utility model Transient Voltage Suppressor. Below in conjunction with Fig. 1, this utility model Transient Voltage Suppressor is illustrated.

As shown in Figure 1, this utility model Transient Voltage Suppressor includes chip body 11, first layer compound passivation 12, upper electrode metal layer 13, and bottom electrode metal level 14, the upper surface of chip body 11 is provided with a pair parallel arrangement of first groove 1111, cutting zone 16 is formed between the end that the first groove 1111 is adjacent with on chip body 11, first layer compound passivation 12 covers in the surface of the first groove 1111, upper electrode metal layer 13 covers in the upper surface of chip body 11 and between a pair first grooves 1111, upper electrode metal layer 13 is played a protective role by the layer compound passivation 12 arranged in the first groove 1111. bottom electrode metal level 14 covers in the lower surface of chip body 11.

Wherein chip body 11 includes monocrystal silicon body 111, covers in the upper doped layer 112 of monocrystal silicon body 111 upper surface and cover the lower doped layer 113 in monocrystal silicon body 11 lower surface and be provided with a pair first grooves 1111 at the upper surface of monocrystal silicon body 11, upper doped layer 112 is located between a pair first grooves 1111, and upper electrode metal layer 13 covers in the upper surface of upper doped layer 112.

The first layer compound passivation 12 covered in the first groove 1111 includes covering the layer polysilicon film 121 in the first groove 1111 surface, covers the silicon nitride film layer 122 on layer polysilicon film 121 and cover the glass passivation layer 123 on silicon nitride film layer 122. By a pair first upper doped layers 112 of groove 1111 protection and upper electrode metal layers 13.

In the present embodiment, upper doped layer 112 is N-type phosphorus interface or P type boron interface. Lower doped layer 113 is N-type phosphorus interface or P type boron interface. Namely going up doped layer 112 is N-type phosphorus interface, and lower doped layer 113 is N-type phosphorus interface; Or upper doped layer 112 is P type boron interface, and lower doped layer 113 is N-type phosphorus interface; Or upper doped layer 112 is N-type phosphorus interface, lower doped layer 113 is P type boron interface; Or upper doped layer 112 is P type boron interface, lower doped layer 113 is P type boron interface. The needs of different occasion can be met.

As shown in Figure 2, in a second embodiment, it is distinctive in that with first embodiment: the second groove 1112 that the lower surface of the monocrystal silicon body 111 of chip body 11 is provided with a pair and the first groove 1111 is corresponding, lower doped layer 113 is located between a pair second grooves 1112, and bottom electrode metal level 14 covers in the lower surface of lower doped layer 113. Being covered with the second layer compound passivation 15 on the surface of the second groove 1112, this second layer compound passivation 15 includes covering the layer polysilicon film 151 in the second groove 1112 surface, cover in the silicon nitride film layer 152 of layer polysilicon film 151 lower surface and cover in the glass passivation layer 153 of silicon nitride film layer 152 lower surface. The outside of the second groove 1112 forms cutting zone 16.

First groove 1111 of this utility model Transient Voltage Suppressor and the second groove 1112 are arc groove.

This utility model has reserved the cutting zone of machine cuts in the outside of the first groove and the second groove, avoid cutter and act directly in glass passivation layer, cutting is not use at chip to carry out on region, cutting damage layer and extension damage layer all fall within chip and do not use region, and product quality is ensured.

Above in association with accompanying drawing embodiment, this utility model being described in detail, this utility model can be made many variations example by those skilled in the art according to the above description. Thus, some details in embodiment should not constitute restriction of the present utility model, this utility model by the scope that defines using appended claims as protection domain of the present utility model.

Claims

1. a Transient Voltage Suppressor, it is characterised in that including:

Cover in the bottom electrode metal level of described chip body lower surface.

2. Transient Voltage Suppressor as claimed in claim 1, it is characterized in that, described chip body includes monocrystal silicon body, cover in the upper doped layer of described monocrystal silicon body upper surface and cover in the lower doped layer of described monocrystal silicon body lower surface, the upper surface of described monocrystal silicon body is provided with the first groove described in a pair, and described upper doped layer is located at described in a pair between first groove.

3. Transient Voltage Suppressor as claimed in claim 2, it is characterised in that described upper electrode metal layer covers in the upper surface of described upper doped layer.

4. Transient Voltage Suppressor as claimed in claim 2, it is characterised in that described monocrystal silicon body lower surface is provided with the second corresponding with described first groove a pair groove, described lower doped layer is located at described in a pair between second groove.

5. Transient Voltage Suppressor as claimed in claim 4, it is characterised in that described bottom electrode metal level covers in the lower surface of described lower doped layer.

6. Transient Voltage Suppressor as claimed in claim 4, it is characterised in that the surface of described second groove is covered with the second layer compound passivation.

7. Transient Voltage Suppressor as claimed in claim 6, it is characterized in that, described second layer compound passivation includes covering the layer polysilicon film in described second flute surfaces, cover in the silicon nitride film layer of described layer polysilicon film lower surface and cover in the glass passivation layer of described silicon nitride film layer lower surface.

8. Transient Voltage Suppressor as claimed in claim 2, it is characterised in that described upper doped layer is N-type phosphorus interface or P type boron interface.

9. Transient Voltage Suppressor as claimed in claim 2, it is characterised in that described lower doped layer is N-type phosphorus interface or P type boron interface.

10. Transient Voltage Suppressor as claimed in claim 1, it is characterized in that, described first layer compound passivation includes covering the layer polysilicon film in described first flute surfaces, covers the silicon nitride film layer on described layer polysilicon film and cover the glass passivation layer on described silicon nitride film layer.