CN110890416A - Composite inner passivation layer double-groove structure high-power rectifier device application chip - Google Patents
Composite inner passivation layer double-groove structure high-power rectifier device application chip Download PDFInfo
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- CN110890416A CN110890416A CN201811046979.0A CN201811046979A CN110890416A CN 110890416 A CN110890416 A CN 110890416A CN 201811046979 A CN201811046979 A CN 201811046979A CN 110890416 A CN110890416 A CN 110890416A
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- layer
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- double
- doped layer
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- 238000002161 passivation Methods 0.000 title claims abstract description 41
- 239000002131 composite material Substances 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000011521 glass Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 238000005520 cutting process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000000926 separation method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
Abstract
The invention provides a composite inner passivation layer double-groove structure high-power rectifier application chip, wherein a chip table top is designed with two parallel double grooves, an upper doped layer of the chip is a P-type doped layer, a lower doped layer is a substrate N-type doped layer, metal layers are electroplated on the surfaces of the upper doped layer and the lower doped layer, the side surfaces and the bottom of the grooves adopt nanoscale oxide films and passivation films made of polysilicon, silicon nitride and special glass components to protect P/N junctions of the chip, the double-groove passivation films are sequentially laminated with nanoscale micro high-purity oxide layers, polysilicon films, silicon nitride films and glass layers, the double-groove design improves damage to the side surfaces and the bottom passivation layers of the grooves caused by cutting, and the composite passivation layer material enables the chip to have the junction temperature characteristic of 500 ℃, and improves the reliability and the stability of the chip.
Description
Technical Field
The invention relates to a semiconductor device, in particular to a composite inner passivation layer double-groove structure high-power rectifying device application chip.
Background
In the field of semiconductor rectifying devices, in the prior art, different ions are doped on two sides of a monocrystalline silicon wafer to form a silicon wafer with a P/N junction and a unidirectional conduction characteristic, then the silicon wafer is corroded in the row and column directions to form a single groove, a passivation layer is arranged on the side surface and the bottom of the groove to protect the P/N junction, and the silicon wafer is cut from the middle position of the single groove to be separated into independent single chips. On one hand, when a silicon wafer is cut and formed into an independent chip, the chip is separated at the middle position of the groove by adopting a separation mode such as mechanical cutting or laser cutting, the damage to the passivation layer protective film caused by the separation mode cannot be completely avoided in the cutting process, and tiny nano-scale and micron-scale damage is formed on the passivation layer, so that the chip has potential failure risk and possibility in subsequent packaging and use; on the other hand, the substances for passivation protection of the P/N junction of the chip of the rectifier device at present are glass or SIPOS (oxygen-doped polysilicon) composite passivation films, and in view of the physical properties of the glass and SIPOS (oxygen-doped polysilicon) composite passivation films, the chip adopting the glass or SIPOS (oxygen-doped polysilicon) as the P/N junction passivation layer protection film at home at present can only meet the environmental application of 100 ℃ junction temperature and below, and has poor reliability under high-temperature or high-pressure environment, increased reverse leakage current of the chip and high chip failure proportion.
Disclosure of Invention
The invention aims to solve the technical problems of improving the damage to a groove passivation film in the silicon wafer cutting process, improving the defect of low high-temperature characteristic of glass or SIPOS (oxygen-doped polycrystalline silicon) serving as a P/N junction passivation layer protection film, and solving the problems of low reliability and poor stability of a chip from the two points.
In order to solve the problems of low reliability and poor stability of a chip, the invention provides a composite inner passivation layer double-groove structure high-power rectifier device, which adopts a double-groove passivation protection to apply the chip, and adopts a nano-scale oxide film and a composite passivation film made of polycrystalline silicon, silicon nitride and special glass components as passivation layers on the side surface and the bottom of a groove.
The chip adopts a double-groove design, the cutting position for separating the silicon wafer is not at the groove position, the damage to the passivation layers at the side surface and the bottom of the groove in the cutting process is avoided, the reliability and the stability of the chip are improved, meanwhile, the material composition of the passivation layer of the groove is changed, and the temperature characteristic and the reliability of the chip are further improved.
The chip comprises an interlayer semiconductor body and a dopant attached to the interlayer semiconductor body
A chip body consisting of the layer and the lower doping layer, a table surface, an upper electrode metal layer and a lower electrode metal layer; the upper electrode metal layer is positioned above the middle of the double-groove composite multilayer passivation region of the chip body, and the lower electrode metal layer is positioned on the outer side of the lower doped layer.
As a further improvement of the design of the doping layer of the present invention, the upper doping layer is a P-type doping layer, and the lower doping layer is a substrate N-type doping layer.
As a further improvement of the double trench design of the present invention, the double trench center spacing =4/5 chip mesa width.
The composite passive films on the side and the bottom of the double-groove are sequentially laminated with a nanoscale micro high-purity oxide layer, a polycrystalline silicon film, a silicon nitride film and a glass layer.
Compared with the prior art, the composite inner passivation layer double-groove structure high-power silicon rectifier device application chip has the following advantages: because the table top is two parallel double grooves, the side surfaces and the bottoms of the double grooves are passivation protection areas, the potential failure risk caused by any possible micro damage when a chip is separated from a silicon wafer into an independent chip can be eliminated, the damage of the chip separation of the double groove structure is completely remained in a non-working area of the chip, and the table top when the chip works is not involved in any damage, so that the excellent characteristics, the high reliability and the high stability of a product are effectively ensured.
The invention adopts a nano-scale oxide film and a composite passivation film made of polysilicon, silicon nitride and special glass components to protect the P/N junction of the groove, realizes the junction temperature of the chip to be more than 200 ℃, and combines with a silicon carbide semiconductor material to realize the junction temperature of the chip to be more than 500 ℃.
Description of the drawings:
fig. 1 is a schematic structural diagram of an embodiment of the present invention.
The labels in the figure are: the structure comprises an intermediate layer semiconductor body 100, an upper doping layer 101, a double-groove passivation protection region 102, an upper electrode metal layer 103, a lower electrode metal layer 104, a lower doping layer 105, a polysilicon film in a mesa structure region, a nanometer-level high-purity oxide layer 106 below the polysilicon film, a silicon nitride film 107 in the mesa structure region, a glass passivation layer 108 made of special glass and a reserved separation region 109.
Fig. 2 is a schematic diagram of a dual trench width.
201 distance between double trenches, 202 chip mesa width.
The specific implementation mode is as follows:
the following detailed description is made with reference to the accompanying drawings: fig. 1 shows a schematic structural diagram of an embodiment of the present invention. In the figure, the high-power silicon rectifier device with the composite inner passivation layer double-groove structure comprises a chip body, a double-groove passivation protection region 102, an upper electrode metal layer 103 and a lower electrode metal layer 104, wherein the chip body consists of an intermediate layer semiconductor body 100, an upper doping layer 101 and a lower doping layer 105 which are attached to an intermediate layer monocrystalline silicon body 100; the upper electrode metal layer 103 is positioned above the middle of the double-groove composite multilayer passivation region of the chip body, and the lower electrode metal layer 104 is positioned on the outer side of the lower doped layer. The invention can further adopt the following measures: or the upper doping layer 101 is a P-type doping region, and the lower doping layer 105 is a substrate N-type doping region; or the upper doped layer 101 is an N-type doped region and the lower doped layer 105 is a substrate P-type doped region to meet the requirements of different occasions.
The invention sets the reserved separation area, and the silicon wafer is separated in the reserved separation area when being separated into the chips, thereby avoiding the direct action in the table passivation layer, wherein the separation is carried out on the unused area of the chip, and the damaged layer and the extended damaged layer both fall in the unused area of the chip, and ensuring the product quality.
The above embodiments are not intended to limit the present invention, and all technical solutions obtained by using equivalent alternatives or equivalent permutations fall within the scope of the present invention.
Claims (5)
1. A chip applied to a high-power rectifier device with a composite inner passivation layer and a double-groove structure adopts double-groove passivation protection, and passivation layers on the side surface and the bottom of a groove adopt nano-scale oxide films and composite passivation films made of polycrystalline silicon, silicon nitride and special glass components.
2. The chip of claim 1, wherein: the chip body, the table top, the upper electrode metal layer and the lower electrode metal layer are formed by an intermediate layer semiconductor body and an upper doping layer and a lower doping layer which are attached to the intermediate layer semiconductor body; the upper electrode metal layer is positioned above the middle of the double-groove composite multilayer passivation region of the chip body, the lower electrode metal layer is positioned on the outer side of the lower doped layer, the upper doped layer is a P-type doped layer, the lower doped layer is a substrate N-type doped layer, and the metal layers are electroplated on the surfaces of the upper doped layer and the lower doped layer.
3. The double trench of claim 1, wherein: the double trench mid-position spacing =4/5 die mesa width.
4. The composite passivation film of claim 1, wherein: the composite passivation film is sequentially laminated with a nanoscale micro high-purity oxide layer, a polycrystalline silicon film, a silicon nitride film and passivation films on the side faces and the bottom of the double grooves of the glass layer.
5. The chip of claim 1, wherein: the junction temperature of the chip can reach more than 500 ℃ by combining with the silicon carbide semiconductor material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811046979.0A CN110890416A (en) | 2018-09-08 | 2018-09-08 | Composite inner passivation layer double-groove structure high-power rectifier device application chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811046979.0A CN110890416A (en) | 2018-09-08 | 2018-09-08 | Composite inner passivation layer double-groove structure high-power rectifier device application chip |
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| Publication Number | Publication Date |
|---|---|
| CN110890416A true CN110890416A (en) | 2020-03-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811046979.0A Pending CN110890416A (en) | 2018-09-08 | 2018-09-08 | Composite inner passivation layer double-groove structure high-power rectifier device application chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113223959A (en) * | 2021-04-12 | 2021-08-06 | 黄山芯微电子股份有限公司 | Method for manufacturing compression joint type diode core |
| CN115547856A (en) * | 2022-10-20 | 2022-12-30 | 安徽钜芯半导体科技有限公司 | High-performance semiconductor rectifying chip and preparation process thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201966215U (en) * | 2010-12-22 | 2011-09-07 | 上海美高森美半导体有限公司 | Large-power silicon rectifying part with composite inner passivation layer being of double-groove structure |
| CN205231039U (en) * | 2015-12-02 | 2016-05-11 | 四川上特科技有限公司 | High withstand voltage mesa diode chip |
-
2018
- 2018-09-08 CN CN201811046979.0A patent/CN110890416A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201966215U (en) * | 2010-12-22 | 2011-09-07 | 上海美高森美半导体有限公司 | Large-power silicon rectifying part with composite inner passivation layer being of double-groove structure |
| CN205231039U (en) * | 2015-12-02 | 2016-05-11 | 四川上特科技有限公司 | High withstand voltage mesa diode chip |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113223959A (en) * | 2021-04-12 | 2021-08-06 | 黄山芯微电子股份有限公司 | Method for manufacturing compression joint type diode core |
| CN115547856A (en) * | 2022-10-20 | 2022-12-30 | 安徽钜芯半导体科技有限公司 | High-performance semiconductor rectifying chip and preparation process thereof |
| CN115547856B (en) * | 2022-10-20 | 2023-05-16 | 安徽钜芯半导体科技有限公司 | High-performance semiconductor rectifying chip and preparation process thereof |
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Application publication date: 20200317 |