CN115547856A - High-performance semiconductor rectifying chip and preparation process thereof - Google Patents

High-performance semiconductor rectifying chip and preparation process thereof Download PDF

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CN115547856A
CN115547856A CN202211289838.8A CN202211289838A CN115547856A CN 115547856 A CN115547856 A CN 115547856A CN 202211289838 A CN202211289838 A CN 202211289838A CN 115547856 A CN115547856 A CN 115547856A
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silicon
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silicon nitride
aluminum
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CN115547856B (en
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曹孙根
张曹朋
冯亚宁
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Anhui Juxin Semiconductor Technology Co ltd
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Abstract

The invention discloses a high-performance semiconductor rectifier chip and a preparation process thereof, relating to the technical field of semiconductor rectifier chips and comprising the following steps: for the composite passivation of polysilicon/silicon nitride/glass, a polysilicon layer transition layer without lattice parameter difference with silicon is introduced into a passivation layer of a common power diode, and silicon nitride is used as a protective layer; preparing a low-concentration deep aluminum-doped P +/P-/N-/N + novel structure, forming a novel P +/P-/N-/N + structure by using an aluminum doping layer with controllable impurity depth, and expanding the width of a PN junction depletion layer; reverse fast recovery mechanism, multilayer doping concentration distribution; a multi-layer P-type buried layer is made on the intrinsic N layer at the bottom of the anode (less than 50 microns). The heavy metal Pt is doped in the silicon by adopting an ion injection method, the recombination life of a large injection carrier is shortened, the electric activity concentration of the silicon is improved by absorbing the Pt by utilizing the formed nano cavity, the reverse recovery time is shortened, and the reverse quick recovery is realized.

Description

High-performance semiconductor rectifying chip and preparation process thereof
Technical Field
The invention relates to the technical field of semiconductor rectifier cores, in particular to a high-performance semiconductor rectifier chip and a preparation process thereof.
Background
The rectifier chip is widely applied to the charger of household appliances, offices and communication equipment, modules such as a power supply and the like; the chip size of the small signal diode product is extremely small, and is only about 0.4 mm.
The rectifying chip is mainly made of a semiconductor material based on polycrystalline silicon/silicon nitride, the number of defects and the surface state density of the semiconductors are high, breakdown is easy to occur on the surface, and the high voltage resistance of the semiconductor rectifier cannot be effectively improved by the traditional surface passivation technology.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a high-performance semiconductor rectifier chip and a preparation process thereof, the high-performance semiconductor rectifier chip is developed by adopting methods such as a composite passivation technology, low-concentration deep aluminum doping and multilayer doping concentration distribution design and the like based on a general process for manufacturing a silicon-based semiconductor, the chip has the characteristics of low price, convenient process realization, high voltage resistance, high power, quick recovery, reverse surge resistance and the like, the requirements of the market on the high-performance high-power semiconductor rectifier chip can be met, and the problems provided in the background technology are solved.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: a preparation process of a high-performance semiconductor rectifier chip comprises the following steps: for the composite passivation of polysilicon/silicon nitride/glass, a polysilicon layer transition layer without lattice parameter difference with silicon is introduced into a passivation layer of a common power diode, and silicon nitride is used as a protective layer; preparing a low concentration deep aluminum doped P +/P-/N-/N + novel structure configured with a concentration of less than 10^17/cm -3 The impurity depth of the aluminum doped layer can be controlled, a new P +/P-/N-/N + type structure is formed, and the width of a PN junction depletion layer is expanded; reverse fast recovery mechanism, multi-layer doping concentration distribution; intrinsic N layer at the bottom of anode (less than 50 microns)And manufacturing a plurality of P-type buried layers, doping heavy metal in the rest intrinsic N layers and controlling the concentration distribution to form a composite center.
Further, a composite passivation technology is adopted, and a nano-scale polycrystalline silicon film is used as an adhesion layer of the nano-scale silicon nitride film; by adopting LPCVD (low pressure chemical vapor deposition), firstly, silane gas is activated by heat energy under lower pressure to be thermally decomposed or chemically reacted, and then the silane gas is deposited on the surface of a substrate to form a polycrystalline silicon film; and (3) growing a silicon nitride film on the surface of the polycrystalline silicon film by using dichlorosilane and ammonia gas.
Further, covering a special glass passivation material above the silicon nitride film; carrying out wet cleaning and photoetching on the substrate to selectively mask the mesa region; and (3) carrying out negative bevel groove modeling by adopting wet etching, constructing a groove structure of the table-board device, and widening the surface space charge layer of the high-concentration area.
Furthermore, wet cleaning and plasma etching dry cleaning are adopted, so that on one hand, the surface of the groove area on the surface is cleaned by the wet method to be coarsened so as to provide the adhesion force of the deposited polycrystalline silicon, and on the other hand, the surface defects of the groove are further stripped by the dry cleaning; the pressure, the temperature gradient and the gas flow of the cavity are integrally controlled through systems such as a mass flowmeter, a pressure sensor and the like of the LPCVD, and polysilicon and silicon nitride with consistent film thickness and density are generated; the boron trioxide series glass powder is used for melting and is matched with a silicon nitride interface, so that the growth of a composite layer with high quality and controllable thickness is realized.
Further, in a vacuum environment, a layer of nanoscale aluminum film is evaporated and deposited on the silicon wafer substrate through electron beams; annealing below the silicon-aluminum eutectic temperature to form a silicon-aluminum diffusion source; the portions not required for film formation are treated by Plasma Enhanced Chemical Vapor Deposition (PECVD) of a silicon nitride layer prior to the selective local drive diffusion step to prevent further oxidation from the external environment and evaporation of aluminum from the diffusion source.
Furthermore, an aluminum doped layer double-anode aluminum boron junction layer structure with controllable impurity depth is provided, and the influence caused by the resistivity of a high silicon wafer is reduced by a source coating and twice diffusion process; and selecting an N-type silicon wafer with proper resistivity and thickness, and respectively diffusing boron and phosphorus to form a P + anode layer and an N + cathode layer.
Further, preparing a heavy metal film by adopting an ion evaporation method, and forming heavy metal doping by adopting a high-temperature diffusion method; therefore, the defects of poor uniformity and abnormal surface of the device are overcome, and the accurate control of the minority carrier lifetime of the semiconductor is realized; the P-type buried layer adopts a precise ion implantation method to control the degree of layering and the thickness of the P type, and the growth of 2 to 4 layers is realized.
Further, after pre-cleaning, evaporating a 40-60 nm heavy metal layer by using an electron beam on the back of the silicon wafer, wherein the heavy metal is Pt; forming a recombination center which is 0.23eV away from the center of the forbidden band; and (4) annealing the alloy at the temperature of less than 400 ℃ under the condition of protective gas to form a uniform diffusion source.
Further, diffusing at high temperature of about 900 ℃, controlling a process time window, and forming a composite center; and (3) directly implanting by adopting low-power boron sources with different dosages, and controlling the implantation angle and time to form a multi-layer P-type buried layer.
A high-performance semiconductor rectifying chip is prepared by the above process.
(III) advantageous effects
The invention provides a high-performance semiconductor rectifying chip and a preparation process thereof. The method has the following beneficial effects:
the reverse recovery characteristic of the diode is greatly improved, and the optimal heavy metal doping concentration value of the P region is obtained. Heavy metal Pt is doped into silicon by adopting an ion injection method to form a recombination center with the center of an ion forbidden band about 0.23eV, the recombination life of a large injection carrier is shortened, the formed nanometer cavity is used for absorbing Pt to improve the electric activity concentration of the Pt, the reverse recovery time is shortened, and then the reverse rapid recovery is realized.
Drawings
FIG. 1 is a schematic view of a semiconductor rectifier chip manufacturing process of the present invention;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
Referring to fig. 1, the invention provides a preparation process of a high-performance semiconductor rectifier chip, which comprises the steps of 1, performing composite passivation on polycrystalline silicon/silicon nitride/glass, introducing a polycrystalline silicon layer transition layer without lattice parameter difference with silicon in a passivation layer of a common power diode, and using silicon nitride as a protective layer;
because the number of defects and the surface state density of the semiconductor are high, the breakdown is easy to occur on the surface, and the traditional surface passivation technology cannot effectively improve the high voltage resistance of the semiconductor rectifier.
Therefore, by researching the fringe electric field and the distribution thereof, starting from the semiconductor energy band theory, the defect energy level of the surface state in the energy band and the capture effect of the defect energy level on the carriers are researched, the vector distribution of the surface electric field is further obtained, and the relationship among the fringe electric field, the surface state and the energy level is clarified; from the angle of lattice matching, the reduction effect of the polycrystalline silicon on the surface state of the semiconductor silicon and the scattering and absorption effects of different carriers are analyzed, the relation between the surface critical electric field and the thickness of the polycrystalline silicon is researched, and a physical model is established.
Based on the method, the low-temperature preparation technology of the polysilicon and the silicon nitride is determined.
Specifically, the step 1 includes the following steps:
step 101, adopting a composite passivation technology, and taking a nano-scale polycrystalline silicon film as an adhesion layer of a nano-scale silicon nitride film;
102, activating silane gas by using heat energy under lower pressure by adopting an LPCVD (low pressure chemical vapor deposition) method, so that the silane gas is subjected to thermal decomposition or chemical reaction and is deposited on the surface of a substrate to form a polycrystalline silicon film;
103, growing a silicon nitride film on the surface of the polycrystalline silicon film by using dichlorosilane and ammonia gas;
step 104, covering a special glass passivation material on the silicon nitride film.
Step 105, carrying out wet cleaning and photoetching on the substrate to selectively mask the mesa region;
106, adopting wet etching to perform negative bevel groove modeling, constructing a groove structure of the mesa device, and widening a surface space charge layer of the high concentration region;
step 107, adopting wet cleaning and plasma etching dry cleaning, wherein on one hand, the surface of the groove area on the surface is cleaned by the wet method to roughen and provide adhesion force for depositing polycrystalline silicon, and on the other hand, the surface defects of the groove are further stripped by the dry cleaning;
and 108, integrally controlling the pressure, the temperature gradient and the gas flow of the cavity through systems such as a mass flow meter, a pressure sensor and the like of the LPCVD to generate polysilicon and silicon nitride with consistent film thickness and density.
And step 109, melting boron trioxide glass powder and matching with a silicon nitride interface to realize growth of a composite layer with high quality and controllable thickness.
When the method is used, the LPCVD temperature field setting is improved in the step, and the controllable film preparation process of polycrystal and silicon nitride is realized, so that the high-quality polysilicon layer/silicon nitride layer can be prepared, the surface recombination current of the manufactured composite passivation chip is obviously reduced, the surface critical breakdown electric field is improved, and the withstand voltage value is improved by more than 18%.
Step 2, preparing a low-concentration deep aluminum-doped P +/P-/N-/N + novel structure, configuring an aluminum-doped layer with controllable impurity depth and concentration less than 10^17/cm-3, forming a novel P +/P-/N-/N + structure, and expanding the width of a PN junction depletion layer;
the circuit can cause very high surge voltage when an inductive load or a large load is switched on or switched off, and the P +/N-/N + structure of the traditional PIN rectifier diode cannot meet the requirement of instantaneous high withstand voltage of a semiconductor rectifier.
An aluminum doping layer with controllable impurity depth and concentration less than 10^17/cm & lt-3 & gt is configured to form a novel P +/P-/N-/N + type structure, and the width of a PN junction depletion layer is expanded, so that the voltage resistance characteristic is greatly improved.
The high-power ion implantation technology and the vacuum low-temperature pre-deposition technology are used for realizing micron-sized deep aluminum implantation, the problems of easy oxidation and alloy formation during aluminum doping are solved, and strong recombination caused by doped in-vivo defects is reduced;
therefore, the longitudinal and transverse concentration distribution of aluminum doping is optimized, and the critical electric field peak value in the depletion layer is reduced.
The step 2 specifically comprises the following steps:
step 201, in a vacuum environment, electron beam evaporation deposits a layer of nanoscale aluminum film on a silicon wafer substrate;
step 202, annealing below a silicon-aluminum eutectic temperature to form a silicon-aluminum diffusion source;
step 203, before the selective local drive diffusion step, a silicon nitride layer is formed on the part which does not need to be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) so as to prevent further oxidation from the external environment and aluminum evaporation from a diffusion source;
step 204, providing a double-anode aluminum-boron junction structure of the aluminum doped layer with controllable impurity depth,
step 205, reducing the influence caused by the resistivity of the high silicon wafer through a source coating and twice diffusion process;
step 206, selecting an N-type silicon wafer with proper resistivity and thickness, and respectively diffusing boron and phosphorus to form a P + anode layer and an N + cathode layer;
when the structure is used, the simulation result verifies that the structure has the function of reducing the forward voltage drop when the chip is conducted, and effectively improves the reverse surge tolerance.
Step 3, reverse fast recovery mechanism and multilayer doping concentration distribution; and (3) manufacturing a multi-layer P-type buried layer on the intrinsic N layer at the bottom of the anode (less than 50 microns), doping heavy metal on the rest intrinsic N layers, and controlling concentration distribution to form a composite center.
With the wide application of high-voltage high-frequency rectifying devices, the working frequency range of the diode is expanded from power frequency to kHz magnitude, and higher requirements are provided for the reverse recovery time characteristics of the diode.
In the deep research of the relation between the capacitance storage effect and the reverse composite minority carrier lifetime in the reverse bias process, according to the physical theory of a semiconductor device, an electric field modulation and forbidden band energy level doping regulation and control means is adopted, a plurality of layers of P-type buried layers are manufactured on an intrinsic N layer at the bottom (less than 50 microns) of an anode, heavy metals are doped on the rest intrinsic N layers, the concentration distribution is controlled, and a composite center is formed;
through a multi-stage PN junction capacitor series mechanism and an increased recombination center, the charge-discharge time and the carrier life of the diode are greatly reduced; taking the position as a starting point, further researching the relation among the number of layers, the interlayer spacing and the capacitance of the P-type buried layer; the effect of recombination center concentration and concentration distribution on minority carrier lifetime was studied.
The step 3 specifically comprises the following steps:
301, preparing a heavy metal film by adopting an ion evaporation method, and forming heavy metal doping by adopting a high-temperature diffusion method; therefore, the defects of poor uniformity and abnormal device surface are overcome, and the accurate control of the minority carrier lifetime of the semiconductor is realized;
and step 302, controlling the layer thickness and thickness of the P type by adopting a precise ion implantation method for the P type buried layer, and realizing the growth of 2-4 layers.
Step 303, after pre-cleaning, evaporating a 40-60 nm heavy metal layer on the back of the silicon wafer by using an electron beam, wherein the heavy metal is Pt; forming a recombination center which is 0.23eV away from the center of the forbidden band;
304, annealing the alloy at a temperature of less than 400 ℃ under the condition of protective gas to form a uniform diffusion source;
305, diffusing at high temperature of about 900 ℃, controlling a process time window, and forming a composite center;
and step 306, adopting low-power boron sources with different dosages to directly implant, and controlling the implantation angle and time to form a plurality of layers of P-type buried layers.
The extra hole injection ratio of the PN junction is related to the doping concentration of the P region, so that the concentration of the P region is reduced, the density of stored charges in the drift region is reduced, and an experimental result obtained by numerical simulation of the doping layer concentration shows that the reverse recovery peak current and the reverse recovery time of the diode are reduced along with the gradual reduction of the doping concentration of the P region of the anode.
Simulation results show that: the reverse recovery characteristic of the diode is greatly improved, and the optimal heavy metal doping concentration value of the P region is obtained. Heavy metal Pt is doped into silicon by adopting an ion injection method to form a recombination center with the center of an ion forbidden band about 0.23eV, the recombination life of a large injection carrier is shortened, the formed nanometer cavity is used for absorbing Pt to improve the electric activity concentration of the Pt, the reverse recovery time is shortened, and then the reverse rapid recovery is realized.
Example 2
Referring to fig. 1, the present invention provides a high performance semiconductor rectifier chip, which is manufactured by the process of embodiment 1.
It is noted that, in this document, relational terms such as first and second, and the like, if any, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A preparation process of a high-performance semiconductor rectifying chip is characterized by comprising the following steps: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
for the composite passivation of polysilicon/silicon nitride/glass, a polysilicon layer transition layer without lattice parameter difference with silicon is introduced into a passivation layer of a common power diode, and silicon nitride is used as a protective layer;
preparing a low concentration deep aluminum doped P +/P-/N-/N + novel structure configured with a concentration of less than 10^17/cm -3 The impurity depth of the aluminum doped layer can be controlled, a new P +/P-/N-/N + type structure is formed, and the width of a PN junction depletion layer is expanded;
reverse fast recovery mechanism, multi-layer doping concentration distribution; and (3) manufacturing a plurality of P-type buried layers on the intrinsic N layer at the bottom (less than 50 microns) of the anode, doping heavy metal on the rest intrinsic N layers, and controlling concentration distribution to form a composite center.
2. The process for preparing a high-performance semiconductor rectifying chip according to claim 1, wherein:
adopting a composite passivation technology, and taking a nano-scale polycrystalline silicon film as an adhesion layer of a nano-scale silicon nitride film;
by adopting LPCVD (low pressure chemical vapor deposition), firstly, activating silane gas by using heat energy under lower pressure to ensure that the silane gas is subjected to thermal decomposition or chemical reaction and is deposited on the surface of a substrate to form a polycrystalline silicon film;
and (3) growing a silicon nitride film on the surface of the polycrystalline silicon film by using dichlorosilane and ammonia gas.
3. The process for preparing the high-performance semiconductor rectifying chip according to claim 1, wherein:
covering a special glass passivation material above the silicon nitride film;
selectively masking the mesa region on the substrate by wet cleaning and photolithography;
and (3) carrying out negative bevel groove modeling by adopting wet etching, constructing a groove structure of the table-board device, and widening the surface space charge layer of the high-concentration area.
4. The process for preparing a high-performance semiconductor rectifier chip according to claim 3, wherein:
wet cleaning and plasma etching dry cleaning are adopted, so that on one hand, the surface of the groove area on the surface is cleaned by the wet method and roughened to provide adhesion force for depositing polycrystalline silicon, and on the other hand, the surface defects of the groove are further stripped by the dry cleaning;
the pressure, the temperature gradient and the gas flow of the cavity are integrally controlled through systems such as a mass flowmeter, a pressure sensor and the like of the LPCVD, and polysilicon and silicon nitride with consistent film thickness and density are generated;
the boron trioxide series glass powder is used for melting and is matched with a silicon nitride interface, so that the growth of a composite layer with high quality and controllable thickness is realized.
5. The process for preparing a high-performance semiconductor rectifying chip according to claim 1, wherein:
in a vacuum environment, a layer of nanoscale aluminum film is evaporated and deposited on a silicon wafer substrate by an electron beam;
annealing below the silicon-aluminum eutectic temperature to form a silicon-aluminum diffusion source;
the portions not required for film formation are treated by Plasma Enhanced Chemical Vapor Deposition (PECVD) of a silicon nitride layer prior to the selective local drive diffusion step to prevent further oxidation from the external environment and evaporation of aluminum from the diffusion source.
6. The process for preparing the high-performance semiconductor rectifying chip according to claim 5, wherein:
provides a double-anode aluminum boron junction layer structure of an aluminum doping layer with controllable impurity depth,
the influence brought by the resistivity of the high silicon wafer is reduced by a source coating and twice diffusion process;
and selecting an N-type silicon wafer with proper resistivity and thickness, and respectively diffusing boron and phosphorus to form a P + anode layer and an N + cathode layer.
7. The process for preparing a high-performance semiconductor rectifying chip according to claim 1, wherein:
preparing a heavy metal film by adopting an ion evaporation method, and forming heavy metal doping by adopting a high-temperature diffusion method; therefore, the defects of poor uniformity and abnormal surface of the device are overcome, and the accurate control of the minority carrier lifetime of the semiconductor is realized;
the P-type buried layer adopts a precise ion implantation method to control the thickness and the thickness of the P-type buried layer and realize the growth of 2 to 4 layers.
8. The process for preparing a high-performance semiconductor rectifying chip according to claim 7, wherein:
after pre-cleaning, evaporating a 40-60 nm heavy metal layer on the back of the silicon wafer by using an electron beam, wherein the heavy metal is Pt; forming a recombination center which is 0.23eV away from the center of the forbidden band;
and (4) annealing the alloy at the temperature of less than 400 ℃ under the condition of protective gas to form a uniform diffusion source.
9. The process for preparing a high-performance semiconductor rectifier chip according to claim 8, wherein:
diffusing at high temperature of about 900 ℃, and controlling a process time window to form a composite center;
and (3) directly implanting by adopting low-power boron sources with different dosages, and controlling the implantation angle and time to form a plurality of layers of P-type buried layers.
10. A high performance semiconductor rectifier chip characterized in that: prepared by the process of any one of claims 1 to 9.
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