CN205210929U - A chip - Google Patents
A chip Download PDFInfo
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- CN205210929U CN205210929U CN201520172876.4U CN201520172876U CN205210929U CN 205210929 U CN205210929 U CN 205210929U CN 201520172876 U CN201520172876 U CN 201520172876U CN 205210929 U CN205210929 U CN 205210929U
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- chip
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Abstract
The utility model discloses a chip, it is arranged in solving prior art a chip and puts the defect of generating heat and leading to the cover to be blown in the surperficial resin layer emergence of a chip into production in the use. Including the stratum basale, be equipped with the fretwork hole in the middle of the stratum basale, the stratum basale superimposition is equipped with the first metal layer, and the edge in fretwork hole is equipped with the resin layer. The utility model discloses a set up the fretwork hole the stratum basale in the middle of, it is downthehole through establishing tableware bottom cover in the fretwork, can install a chip in the tableware bottom, combine through resin layer and tableware bottom marginal facies for a chip is inseparabler with the combination of tableware, guarantees that a chip is difficult for droing, improves a chip's life, just the utility model discloses the yield reaches more than 90 percent, in addition the utility model discloses a set a chip to annular, increased the effective area of reflecting region, satisfy the electrical parameter requirement of circuit, still can rationally typeset, increase its effective use area.
Description
Technical field
The utility model relates to minisize component field, is specifically related to a kind of chip.
Background technology
Along with the develop rapidly of electronics and information industry, electronic product is continuous while multifunctional multicomponent future development, and the trend of its microminiaturization is also day by day obvious, and it is multi-functional that this just requires that the components and parts of electronic product singly will not have, and the volume of components and parts is little.
In general, for meeting the technological requirement that semiconductor batch is produced, the chip part of semiconductor devices is often designed to square, because square shaped core flake products is convenient to cutting, encapsulation etc., but this is also easily with circuit and serves negative effect, as square shaped core sector-meeting produces border and edge effect simultaneously.
In addition, along with popularizing of Automated Clearing House system, prior art, by fixed chip bottom tableware, realizes intelligence clearing by the checkout station information read in chip, to accelerate clearing speed, and raising settlement efficiency; But chip by bonding or alternate manner is fixed on bottom tableware time, easily come off bottom tableware, yield rate is very low, generally about 10%, therefore have impact on the serviceable life of chip and the yield rate of making thereof.
Therefore for the problems referred to above, be necessary that a kind of new chip of design is to make up above-mentioned defect.
Utility model content
For addressing the aforementioned drawbacks, the utility model proposes a kind of chip, simply, tight with the combination of tableware, the life-span is long, and yield rate is high for its structure and making.
The technical solution of the utility model is achieved in that
A kind of chip, it comprises basalis, is provided with hollow hole in the middle of basalis; Basalis is folded and is provided with the first metal layer, the edge of hollow hole is provided with resin bed.
Wherein, foldedly on the first metal layer the second metal level is provided with.
Wherein, the first metal layer, the second metal level are annular.
Wherein, basalis is annular.
Wherein, hollow hole is circle, rectangle, triangle or rhombus.
Compared with prior art, the utility model tool has the following advantages:
(1) the utility model by arranging hollow hole in the middle of basalis, by being set in hollow hole bottom tableware, can chip be arranged on bottom tableware, combined with tableware bottom margin by resin bed, make the combination of chip and tableware tightr, ensure chip difficult drop-off, improve the serviceable life of chip, and the utility model yield rate reaches more than 90%.
(2) the utility model is by being arranged to annular by chip, increases the useful area of echo area, meets the electrical quantity requirement of circuit, also can rationally typesetting, increases its effective usable floor area.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the utility model chip.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
With reference to Fig. 1, a kind of chip 1, it comprises basalis 2, is provided with hollow hole 3 in the middle of basalis 2; Basalis 2 is folded and is provided with the first metal layer (not shown), the edge of hollow hole is provided with resin bed.The utility model basalis is annular, avoids producing border and edge effect.
In the middle of the utility model basalis, hollow hole is set, therefore those skilled in the art only need by being set in hollow hole bottom tableware, can chip be arranged on bottom tableware, combined with tableware bottom margin by resin bed, make the combination of chip and tableware tightr, ensure chip difficult drop-off, the utility model yield rate reaches more than 90%.
Wherein, foldedly on the first metal layer the second metal level (not shown) is provided with.The utility model the first metal layer and the second metal level are all integrated with circuit, are conveniently connected with external device, realize the function of chip.
The utility model the first metal layer, the second metal level are annular, the mating shapes of convenience and basalis.
The utility model hollow hole is circle, rectangle, triangle or rhombus.The shape of the utility model hollow hole is consistent with the form trait bottom service plate, and hollow hole can also be arranged to Else Rule or irregular shape according to actual conditions by those skilled in the art, only need keep consistent with the shape bottom tableware.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (5)
1. a chip, is characterized in that, it comprises basalis, is provided with hollow hole in the middle of basalis; Basalis is folded and is provided with the first metal layer, the edge of hollow hole is provided with resin bed.
2. chip as claimed in claim 1, is characterized in that, the first metal layer is folded and is provided with the second metal level.
3. chip as claimed in claim 2, it is characterized in that, the first metal layer, the second metal level are annular.
4. chip as claimed in claim 3, is characterized in that, basalis is annular.
5. the chip according to any one of claim 1-4, is characterized in that: hollow hole is circle, rectangle, triangle or rhombus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520172876.4U CN205210929U (en) | 2015-03-25 | 2015-03-25 | A chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520172876.4U CN205210929U (en) | 2015-03-25 | 2015-03-25 | A chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205210929U true CN205210929U (en) | 2016-05-04 |
Family
ID=55848634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520172876.4U Active CN205210929U (en) | 2015-03-25 | 2015-03-25 | A chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205210929U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104751222A (en) * | 2015-03-25 | 2015-07-01 | 杭州雄伟科技开发有限公司 | Chip |
-
2015
- 2015-03-25 CN CN201520172876.4U patent/CN205210929U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104751222A (en) * | 2015-03-25 | 2015-07-01 | 杭州雄伟科技开发有限公司 | Chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |