Utility model content
In order to solve the defect that prior art exists, its utility model provides a kind of can ensure that the speed regulator test device that data are stablized more and the isolation Low Drift Temperature of passage complementation accurately gathers under ensureing high-speed data isolation collection situation。
The technical scheme that this utility model provides, the speed regulator test device that a kind of passage complementation isolation Low Drift Temperature gathers, including electric power system, process system, data collecting system, signal output system and data transmission system;Described process system is connected with electric power system, data collecting system, signal output system and data transmission system respectively;Described process system includes DSP data processing circuit, telecommunication circuit and analog signal processing circuit;Described data collecting system includes analogue signal input module, 2 channel frequence input circuits, 3 channel switching amount input circuits;Described signal output system includes 2 channel analog signal output circuits, 2 channel frequence output circuits and 3 channel switching amount output circuits;The ethernet communication system that described data transmission system is is core with W5300 chip;Described analogue signal input module includes 8 passage hybrid analog-digital simulation signal input circuit and analog signal conditioner circuit, and in described 8 passage hybrid analog-digital simulation signal input circuits, each passage is all connected with an analog signal conditioner circuit。
Preferably, described analog signal conditioner circuit includes current signal conditioning circuit and voltage signal conditioning circuit;Described current signal conditioning circuit includes electric current input interface, current signal input modulate circuit, current signal isolation circuit and rear class current signal conditioning circuit;Described voltage signal conditioning circuit includes voltage input interface, voltage signal input modulate circuit, voltage signal isolation circuit and rear class voltage signal conditioning circuit;Described rear class current signal conditioning circuit and rear class voltage signal conditioning circuit are all connected with described analog signal processing circuit。
Preferably, the current signal that described current signal conditioning circuit and voltage signal conditioning circuit gather uses as complementation with voltage signal。
Preferably, described analog signal processing circuit includes current signal process circuit and voltage signal processing circuit。
Preferably, described 2 channel frequence input circuits include pressure limiting circuit, frequency signal modulate circuit, frequency signal isolation circuit and frequency signal drive circuit。
Preferably, described 2 channel frequence output circuits include Schmitt trigger circuit one, high-speed isolated photoelectric coupled circuit one and operation amplifier circuit。
Preferably, described 3 channel switching amount input circuits and 3 channel switching amount output circuits all include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two。
This utility model is relative to the beneficial effect of prior art, and analog signal channel provided by the utility model all comprises voltage and current input function;All analog signal channels are respectively provided with independent humidity drift and compensate and time drift function;Achieve 8 passage hybrid guided mode analog quantity high speed acquisition and high speed data transfer functions;Isolate in collection situation at data high-speed, it is ensured that data are more stable and accurate;This utility model ensure that the precision of stability that data transmit and data, has taken into account data high-speed collection and transmission and high-precision and high-stability, has had good market using value。
Detailed description of the invention
For the ease of understanding this utility model, below in conjunction with the drawings and specific embodiments, this utility model is described in detail。Accompanying drawing gives preferred embodiment of the present utility model。But, this utility model can realize in many different forms, however it is not limited to the embodiment described by this specification。On the contrary, the purpose providing these embodiments is to make the understanding to disclosure of the present utility model more thorough comprehensively。
It should be noted that be referred to as " being fixed on " another element when element, it can directly on another element or can also there is element placed in the middle。When an element is considered as " connection " another element, it can be directly to another element or may be simultaneously present centering elements。Term " vertical ", " level ", "left", "right" and similar statement that this specification uses are for illustrative purposes only。
Unless otherwise defined, all of technology that this specification uses and scientific terminology are identical with belonging to the implication that those skilled in the art of the present utility model are generally understood that。This specification is intended merely at term used in the description of the present utility model the purpose describing specific embodiment, is not intended to restriction this utility model。
Below in conjunction with accompanying drawing, the speed regulator test device of a kind of passage complementation isolation Low Drift Temperature collection of this utility model is elaborated。
As depicted in figs. 1 and 2, the speed regulator test device that a kind of passage complementation isolation Low Drift Temperature gathers, including electric power system, process system, data collecting system, signal output system and data transmission system;Described process system is connected with electric power system, data collecting system, signal output system and data transmission system respectively;Described process system includes DSP data processing circuit, telecommunication circuit and analog signal processing circuit;Described analog signal processing circuit includes current signal and processes circuit and voltage signal processing circuit;Described data collecting system includes analogue signal input module, 2 channel frequence input circuits, 3 channel switching amount input circuits;Described 2 channel frequence input circuits include pressure limiting circuit, frequency signal modulate circuit, frequency signal isolation circuit and frequency signal drive circuit;Described signal output system includes 2 channel analog signal output circuits, 2 channel frequence output circuits and 3 channel switching amount output circuits;Described 3 channel switching amount input circuits and 3 channel switching amount output circuits all include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two;Described 2 channel frequence output circuits include Schmitt trigger circuit one, high-speed isolated photoelectric coupled circuit one and operation amplifier circuit。
The ethernet communication system that described data transmission system is is core with W5300 chip;Described analogue signal input module includes 8 passage hybrid analog-digital simulation signal input circuit and analog signal conditioner circuit, and in described 8 passage hybrid analog-digital simulation signal input circuits, each passage is all connected with an analog signal conditioner circuit;Described analog signal conditioner circuit includes current signal conditioning circuit and voltage signal conditioning circuit;Described current signal conditioning circuit includes electric current input interface, current signal input modulate circuit, current signal isolation circuit and rear class current signal conditioning circuit;Described voltage signal conditioning circuit includes voltage input interface, voltage signal input modulate circuit, voltage signal isolation circuit and rear class voltage signal conditioning circuit;Described rear class current signal conditioning circuit and rear class voltage signal conditioning circuit are all connected with described analog signal processing circuit;The current signal that described current signal conditioning circuit and voltage signal conditioning circuit gather uses as complementation with voltage signal。
Described data collecting system includes analogue signal input module, 2 channel frequence input circuits, 3 channel switching amount input circuits, described analogue signal input module includes 8 passage hybrid analog-digital simulation signal input circuit and analog signal conditioner circuit, complete following task: 8 passage hybrid analog-digital simulation signal input circuits gather 16 analogue signals, and each passage comprises a channel current signal and a voltage signal passage;Gather 3 channel switching amount signals;Gather 2 channel frequence amount signals。
The current signal that described current signal conditioning circuit and voltage signal conditioning circuit gather uses as complementation with voltage signal, namely when appointment analog input signal passage is channel current signal, then the voltage signal that corresponding analog input signal passage collects is as the compensation calculation value of current signal;Otherwise, it is intended that when analog input signal passage is voltage signal passage, then the current signal that corresponding analog input signal passage collects is as the compensation calculation value of voltage signal。
In realizing analogue signal complementation gatherer process, DSP internal processes uses following processing method when writing:
1, for calculating simulation amount input signal values, the current signal input channel to analog input signal passage and the independent calibration of voltage signal input channel are needed when dispatching from the factory。
2, when rate determining voltage signal passage, analog digital conversion code ADCV0 measured time simultaneously by channel current signal zero load is recorded and stored in eeprom circuit;In like manner, when calibration channel current signal, analog digital conversion code ADCI0 measured time simultaneously by voltage signal passage zero load is recorded and stored in EEPROM。
3, owing to the voltage signal passage in analog input signal passage adopts identical process circuit structure with channel current signal, and it is in approximated position in circuit, therefore there is identical temperature sensation, it may have close temperature drift trend。
Therefore, carry out data acquisition set value in the application every time, if what analog input signal passage was currently used is current signal, then voltage input interface will not access signal, the temperature drift value (referring to ADC code) that the current signal relative rate timing now recorded occurs, the drift value (referring to ADC code) surveyed with voltage signal has close drift value, now deducts, by the channel current signal value collected, the drift value that voltage signal records, and gets final product the actual numerical value that corrective current signal records;If analog input signal passage uses voltage signal, then need to use channel current signal to compensate。
Analog signal conditioner circuit include input interface, with LM258 chip be core analogue signal input modulate circuit, with the IS0124 analog signal isolating circuit being core and be core with LM258 chip rear class analog signal conditioner circuit。
Described 3 channel switching amount input circuits and 3 channel switching amount output circuits all include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two, on-off model is by, after high-speed isolated photoelectric coupled circuit two, being transferred to DSP data processing circuit then through Schmitt trigger circuit two 74HC14;DSP data processing circuit drives high-speed isolated photoelectric coupled circuit two output to OC gate circuit by Schmitt trigger circuit two 74HC14, thus externally producing the on-off model of OC gate signal characteristic。
Described 2 channel analog signal output circuits, wherein a road is 4 ~ 20mA signal output apparatus, and another road is 0 ~ 10V signal output apparatus;Analog signal output circuit is with DAC chip TLV5618AID for processing core, with compound transistor MDJ122 for signal drive circuit。
Analog signal processing circuit, in SPI communication mode, carries out data communication with TLV5618AID chip after optocoupler 6N137 isolates;TLV5618AID exports the corresponding fundamental voltage analogue value to corresponding analog output channel after receiving analog signal processing circuit output order;Fundamental voltage analogue signal is output as 4 ~ 20mA current signal or 0 ~ 10V voltage signal of standard after the signal condition and drive circuit of LM358 chip and MDJ122 chip composition。
Described 2 channel frequence input circuits include pressure limiting circuit that two is core with the SM4007 chip of incorgruous parallel connection, with LF411CP chip be core frequency signal modulate circuit, isolate circuit with the TIL177 frequency signal being core and frequency signal drive circuit that Schmidt trigger 74HC14 is core。
The frequency signal of outside 0.2~300V peak value isolates circuit through pressure limiting circuit and the frequency signal that frequency signal modulate circuit conditioning rear drive TIL117 is core that LF411CP chip is core of SM4007 chip, and signal is passed to the I/O mouth circuit with capturing function by the frequency signal drive circuit that Schmidt trigger 74HC14 is core after the frequency signal isolation circuit that TIL117 is core。
2 channel frequence output circuits include Schmidt trigger 74HC14 circuit one, high-speed isolated optocoupler TIL117 circuit one and UA741C operation amplifier circuit;From DSP data processing circuit, the digital signal of 0 ~ 3.3V of output is input to, after Schmidt trigger 74HC14 circuit one and high-speed isolated optocoupler TIL117 circuit one are isolated, the signal comparator circuit that UA41C is core, is converted to the frequency output signal of-10 ~ 10V amplitude afterwards。
The ethernet communication system that described data transmission system is is core with W5300 chip, telecommunication circuit and W5300 chip carry out data interaction by the parallel bus of 16 bit widths。
Telecommunication circuit first passes through the running parameter of bus configuration W5300 chip after starting, and including IP address, COM1, operating protocol, data buffer storage parameter, W5300 chip can carry out data communication with miscellaneous equipment on Ethernet after having configured。
It should be noted that above-mentioned each technical characteristic continues to be mutually combined, form various embodiments not enumerated above, be accordingly to be regarded as the scope that this utility model description is recorded;Further, for those of ordinary skills, it is possible to improved according to the above description or convert, and all these improve and conversion all should belong to the protection domain of this utility model claims。