CN205176554U - Complementary low temperature of keeping apart of passageway floats adjuster testing arrangement of collection - Google Patents
Complementary low temperature of keeping apart of passageway floats adjuster testing arrangement of collection Download PDFInfo
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- CN205176554U CN205176554U CN201520939506.9U CN201520939506U CN205176554U CN 205176554 U CN205176554 U CN 205176554U CN 201520939506 U CN201520939506 U CN 201520939506U CN 205176554 U CN205176554 U CN 205176554U
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Abstract
The utility model provides a complementary low temperature of keeping apart of passageway floats adjuster testing arrangement of collection, includes power supply system, processing system, data acquisition system, signal output system and data transmission system, processing system includes DSP data processing circuit, communication circuit and analog signal processing circuit, data acquisition system includes analog signal input module, 2 passageway frequency input circuit, 3 channel switchs volume input circuit, the signal output system includes 2 passageways simulation signal output circuit, 2 passageway frequency output circuit and 3 channel switchs volume output circuit, analog signal input module includes mixed analog signal input circuit of 8 passageways and analog signal modulate circuit, 8 A analog signal modulate circuit is all connected to every passageway among the passageway hybrid simulation signal input circuit, the utility model discloses guarantee data transmission's the stability and the precision of data, taken into account the high -speed collection of data and transmission and high accuracy high stability, had good market using value.
Description
Technical field
The utility model relates to a kind of speed regulator proving installation, particularly relates to the adjuster proving installation that a kind of passage complementation isolation Low Drift Temperature gathers.
Background technology
Along with the continuous expansion of China's power construction scale and country are to the requirement increasingly stringent of safety in production and specification, and to the active demand that high efficiency of energy utilizes, also more and more paid attention in the detection of hydro-electric power generation equipment and maintenance work.And the performance of hydrogovernor is all very important content to water power power benefit and safe operation, also more and more higher in the demand in water power field to speed regulator tester for hydrogovernor Performance Detection.Traditional speed regulator tester realizes data high-speed collection and transmission and high-precision and high-stability aspect at the same time and cannot take into account always, and this is mainly because hyperchannel buffer circuit has power consumption greatly, poor heat radiation, high speed acquisition circuit, the problems such as precision is not enough.
Along with the construction of hydropower stations and maintenance work more and more specification, hydrogovernor is detected that requirement is also more and more higher, in speed regulator testing, also more and more pay attention to stability and the reliability of Monitoring Data.
Prior art existing defects, needs to improve.
Utility model content
In order to solve the defect that prior art exists, its utility model provides a kind of and can ensure to ensure the more stable adjuster proving installation gathered with the isolation of passage complementation accurately Low Drift Temperature of data in high-speed data isolation collection situation.
The technical scheme that the utility model provides, the adjuster proving installation that a kind of passage complementation isolation Low Drift Temperature gathers, comprises electric power system, disposal system, data acquisition system (DAS), signal output system and data transmission system; Described disposal system is connected with electric power system, data acquisition system (DAS), signal output system and data transmission system respectively; Described disposal system comprises DSP data processing circuit, telecommunication circuit and analog signal processing circuit; Described data acquisition system (DAS) comprises simulating signal load module, 2 channel frequence input circuits, 3 channel switch amount input circuits; Described signal output system comprises 2 channel analog signal output circuits, 2 channel frequence output circuits and 3 channel switch amount output circuits; The ethernet communication system that described data transmission system is is core with W5300 chip; Described simulating signal load module comprises 8 passage hybrid analog-digital simulation signal input circuits and analog signal conditioner circuit, and in described 8 passage hybrid analog-digital simulation signal input circuits, each passage all connects an analog signal conditioner circuit.
Preferably, described analog signal conditioner circuit comprises current signal conditioning circuit and voltage signal conditioning circuit; Described current signal conditioning circuit comprises electric current input interface, current signal input modulate circuit, current signal buffer circuit and rear class current signal conditioning circuit; Described voltage signal conditioning circuit comprises voltage input interface, voltage signal input modulate circuit, voltage signal buffer circuit and rear class voltage signal conditioning circuit; Described rear class current signal conditioning circuit is all connected with described analog signal processing circuit with rear class voltage signal conditioning circuit.
Preferably, the current signal that gathers of described current signal conditioning circuit and voltage signal conditioning circuit and voltage signal use as complementation.
Preferably, described analog signal processing circuit comprises current signal treatment circuit and voltage signal processing circuit.
Preferably, described 2 channel frequence input circuits comprise pressure limiting circuit, frequency signal modulate circuit, frequency signal buffer circuit and frequency signal driving circuit.
Preferably, described 2 channel frequence output circuits comprise Schmitt trigger circuit one, high-speed isolated photoelectric coupled circuit one and operation amplifier circuit.
Preferably, described 3 channel switch amount input circuits and 3 channel switch amount output circuits include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two.
The utility model is relative to the beneficial effect of prior art, and analog signal channel provided by the utility model all comprises voltage and current input function; All analog signal channels all have independent humidity drift and compensate and time drift function; Achieve 8 passage hybrid guided mode analog quantity high speed acquisition and high speed data transfer functions; In data high-speed isolation collection situation, ensure that data are more stable and accurate; The utility model ensure that the precision of the stability that data are transmitted and data, has taken into account data high-speed collection and transmission and high-precision and high-stability, has had good market using value.
Accompanying drawing explanation
Fig. 1 is the utility model integrated connection schematic diagram;
Fig. 2 is utility model analog signal conditioner circuit connection diagram.
Embodiment
For the ease of understanding the utility model, below in conjunction with the drawings and specific embodiments, the utility model is described in detail.Preferred embodiment of the present utility model is given in accompanying drawing.But the utility model can realize in many different forms, is not limited to the embodiment described by this instructions.On the contrary, provide the object of these embodiments be make the understanding of disclosure of the present utility model more comprehensively thorough.
It should be noted that, when element is called as " being fixed on " another element, directly can there is element placed in the middle in it on another element or also.When an element is considered to " connection " another element, it can be directly connected to another element or may there is centering elements simultaneously.The term " vertical " that this instructions uses, " level ", "left", "right" and similar statement are just for illustrative purposes.
Unless otherwise defined, all technology of using of this instructions and scientific terminology are identical with belonging to the implication that those skilled in the art of the present utility model understand usually.The object of the term used in instructions of the present utility model in this instructions just in order to describe specific embodiment is not for limiting the utility model.
Elaborate below in conjunction with the adjuster proving installation of accompanying drawing to the collection of a kind of passage complementation of the utility model isolation Low Drift Temperature.
As depicted in figs. 1 and 2, the adjuster proving installation that a kind of passage complementation isolation Low Drift Temperature gathers, comprises electric power system, disposal system, data acquisition system (DAS), signal output system and data transmission system; Described disposal system is connected with electric power system, data acquisition system (DAS), signal output system and data transmission system respectively; Described disposal system comprises DSP data processing circuit, telecommunication circuit and analog signal processing circuit; Described analog signal processing circuit comprises current signal treatment circuit and voltage signal processing circuit; Described data acquisition system (DAS) comprises simulating signal load module, 2 channel frequence input circuits, 3 channel switch amount input circuits; Described 2 channel frequence input circuits comprise pressure limiting circuit, frequency signal modulate circuit, frequency signal buffer circuit and frequency signal driving circuit; Described signal output system comprises 2 channel analog signal output circuits, 2 channel frequence output circuits and 3 channel switch amount output circuits; Described 3 channel switch amount input circuits and 3 channel switch amount output circuits include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two; Described 2 channel frequence output circuits comprise Schmitt trigger circuit one, high-speed isolated photoelectric coupled circuit one and operation amplifier circuit.
The ethernet communication system that described data transmission system is is core with W5300 chip; Described simulating signal load module comprises 8 passage hybrid analog-digital simulation signal input circuits and analog signal conditioner circuit, and in described 8 passage hybrid analog-digital simulation signal input circuits, each passage all connects an analog signal conditioner circuit; Described analog signal conditioner circuit comprises current signal conditioning circuit and voltage signal conditioning circuit; Described current signal conditioning circuit comprises electric current input interface, current signal input modulate circuit, current signal buffer circuit and rear class current signal conditioning circuit; Described voltage signal conditioning circuit comprises voltage input interface, voltage signal input modulate circuit, voltage signal buffer circuit and rear class voltage signal conditioning circuit; Described rear class current signal conditioning circuit is all connected with described analog signal processing circuit with rear class voltage signal conditioning circuit; The current signal that described current signal conditioning circuit and voltage signal conditioning circuit gather and voltage signal use as complementation.
Described data acquisition system (DAS) comprises simulating signal load module, 2 channel frequence input circuits, 3 channel switch amount input circuits, described simulating signal load module comprises 8 passage hybrid analog-digital simulation signal input circuits and analog signal conditioner circuit, complete following task: 8 passage hybrid analog-digital simulation signal input circuits gather 16 simulating signals, each passage comprises a channel current signal and a voltage signal passage; Gather 3 channel switch amount signals; Gather 2 channel frequence amount signals.
The current signal that described current signal conditioning circuit and voltage signal conditioning circuit gather and voltage signal use as complementation, when namely specifying analog input signal passage to be channel current signal, then the voltage signal that collects of corresponding analog input signal passage is as the compensation calculation value of current signal; Otherwise when specifying analog input signal passage to be voltage signal passage, then the current signal that collects of corresponding analog input signal passage is as the compensation calculation value of voltage signal.
Realizing, in the complementary gatherer process of simulating signal, when DSP internal processes is write, using following disposal route:
1, in order to calculating simulation amount input signal values, the current signal input channel to analog input signal passage and the independent calibration of voltage signal input channel is needed when dispatching from the factory.
2, when rate determining voltage signal passage, measured analog to digital conversion code ADCV0 during channel current signal zero load is recorded and is stored in eeprom circuit simultaneously; In like manner, when calibration channel current signal, measured analog to digital conversion code ADCI0 during the zero load of voltage signal passage is recorded and is stored in EEPROM simultaneously.
3, because the voltage signal passage in analog input signal passage and channel current signal adopt identical treatment circuit structure, and be in approximated position in circuit, therefore there is identical temperature sensation, also there is close temperature drift trend.
Therefore, carry out data acquisition set value in the application at every turn, if analog input signal passage is current use current signal, then voltage input interface will not access signal, the temperature drift value (referring to ADC code) that the current signal relative rate timing now recorded occurs, the drift value (referring to ADC code) surveyed with voltage signal has close drift value, now deducts by the channel current signal value collected the drift value that voltage signal records, can the actual numerical value that records of corrective current signal; If analog input signal passage uses voltage signal, then need to use channel current signal to compensate.
Analog signal conditioner circuit comprises input interface, with the LM258 chip simulating signal input modulate circuit that is core, take IS0124 as the analog signal isolating circuit of core and the rear class analog signal conditioner circuit that is core with LM258 chip.
Described 3 channel switch amount input circuits and 3 channel switch amount output circuits include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two, on-off model by after high-speed isolated photoelectric coupled circuit two, then is transferred to DSP data processing circuit through Schmitt trigger circuit two 74HC14; DSP data processing circuit drives high-speed isolated photoelectric coupled circuit two to output to OC gate circuit by Schmitt trigger circuit two 74HC14, thus externally produces the on-off model of OC gate signal characteristic.
Described 2 channel analog signal output circuits, wherein a road is 4 ~ 20mA signal output apparatus, and another road is 0 ~ 10V signal output apparatus; Analog signal output circuit with DAC chip TLV5618AID for process core, with compound transistor MDJ122 for signal drive circuit.
Analog signal processing circuit, with SPI communication mode, carries out data communication with TLV5618AID chip after optocoupler 6N137 isolates; TLV5618AID exports the corresponding fundamental voltage analogue value to corresponding analog output channel after receiving analog signal processing circuit output order; It is 4 ~ 20mA current signal or 0 ~ 10V voltage signal of standard that fundamental voltage simulating signal exports after signal condition and the driving circuit of LM358 chip and MDJ122 chip composition.
Described 2 channel frequence input circuits comprise pressure limiting circuit that two is core with the SM4007 chip of incorgruous parallel connection, with the LF411CP chip frequency signal modulate circuit that is core, the frequency signal driving circuit that take TIL177 as the frequency signal buffer circuit of core and Schmidt trigger 74HC14 is core.
The frequency signal of outside 0.2 ~ 300V peak value is the frequency signal buffer circuit of core through the frequency signal modulate circuit conditioning rear drive TIL117 that the pressure limiting circuit of SM4007 chip and LF411CP chip are core, and the frequency signal driving circuit that signal is core by Schmidt trigger 74HC14 after the frequency signal buffer circuit that TIL117 is core passes to the I/O mouth circuit with capturing function.
2 channel frequence output circuits comprise Schmidt trigger 74HC14 circuit one, high-speed isolated optocoupler TIL117 circuit one and UA741C operation amplifier circuit; The digital signal of the 0 ~ 3.3V exported from DSP data processing circuit is input to the signal comparator circuit that UA41C is core after Schmidt trigger 74HC14 circuit one and the isolation of high-speed isolated optocoupler TIL117 circuit one, is converted to the frequency output signal of-10 ~ 10V amplitude afterwards.
The ethernet communication system that described data transmission system is is core with W5300 chip, telecommunication circuit and W5300 chip carry out data interaction by the parallel bus of 16 bit widths.
After telecommunication circuit starts, first by the running parameter of bus configuration W5300 chip, comprise IP address, communication port, operating protocol, data buffer storage parameter, after W5300 chip configuration completes, data communication can be carried out with miscellaneous equipment on Ethernet.
It should be noted that, above-mentioned each technical characteristic continues combination mutually, is formed not in above-named various embodiment, is all considered as the scope that the utility model instructions is recorded; Further, for those of ordinary skills, can be improved according to the above description or convert, and all these improve and convert the protection domain that all should belong to the utility model claims.
Claims (7)
1. an adjuster proving installation for passage complementation isolation Low Drift Temperature collection, is characterized in that, comprise electric power system, disposal system, data acquisition system (DAS), signal output system and data transmission system; Described disposal system is connected with electric power system, data acquisition system (DAS), signal output system and data transmission system respectively; Described disposal system comprises DSP data processing circuit, telecommunication circuit and analog signal processing circuit; Described data acquisition system (DAS) comprises simulating signal load module, 2 channel frequence input circuits, 3 channel switch amount input circuits; Described signal output system comprises 2 channel analog signal output circuits, 2 channel frequence output circuits and 3 channel switch amount output circuits; The ethernet communication system that described data transmission system is is core with W5300 chip; Described simulating signal load module comprises 8 passage hybrid analog-digital simulation signal input circuits and analog signal conditioner circuit, and in described 8 passage hybrid analog-digital simulation signal input circuits, each passage all connects an analog signal conditioner circuit.
2. the adjuster proving installation of a kind of passage complementation isolation Low Drift Temperature collection according to claim 1, it is characterized in that, described analog signal conditioner circuit comprises current signal conditioning circuit and voltage signal conditioning circuit; Described current signal conditioning circuit comprises electric current input interface, current signal input modulate circuit, current signal buffer circuit and rear class current signal conditioning circuit; Described voltage signal conditioning circuit comprises voltage input interface, voltage signal input modulate circuit, voltage signal buffer circuit and rear class voltage signal conditioning circuit; Described rear class current signal conditioning circuit is all connected with described analog signal processing circuit with rear class voltage signal conditioning circuit.
3. the adjuster proving installation of a kind of passage complementation isolation Low Drift Temperature collection according to claim 2, it is characterized in that, the current signal that described current signal conditioning circuit and voltage signal conditioning circuit gather and voltage signal use as complementation.
4. the adjuster proving installation of a kind of passage complementation isolation Low Drift Temperature collection according to claim 1, it is characterized in that, described analog signal processing circuit comprises current signal treatment circuit and voltage signal processing circuit.
5. the adjuster proving installation of a kind of passage complementation isolation Low Drift Temperature collection according to claim 1, it is characterized in that, described 2 channel frequence input circuits comprise pressure limiting circuit, frequency signal modulate circuit, frequency signal buffer circuit and frequency signal driving circuit.
6. the adjuster proving installation of a kind of passage complementation isolation Low Drift Temperature collection according to claim 1, it is characterized in that, described 2 channel frequence output circuits comprise Schmitt trigger circuit one, high-speed isolated photoelectric coupled circuit one and operation amplifier circuit.
7. the adjuster proving installation of a kind of passage complementation isolation Low Drift Temperature collection according to claim 1, it is characterized in that, described 3 channel switch amount input circuits and 3 channel switch amount output circuits include high-speed isolated photoelectric coupled circuit two and Schmitt trigger circuit two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520939506.9U CN205176554U9 (en) | 2015-11-23 | 2015-11-23 | Complementary low temperature of keeping apart of passageway floats speed regulator testing arrangement of collection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520939506.9U CN205176554U9 (en) | 2015-11-23 | 2015-11-23 | Complementary low temperature of keeping apart of passageway floats speed regulator testing arrangement of collection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN205176554U true CN205176554U (en) | 2016-04-20 |
| CN205176554U9 CN205176554U9 (en) | 2016-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520939506.9U Expired - Fee Related CN205176554U9 (en) | 2015-11-23 | 2015-11-23 | Complementary low temperature of keeping apart of passageway floats speed regulator testing arrangement of collection |
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| Country | Link |
|---|---|
| CN (1) | CN205176554U9 (en) |
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2015
- 2015-11-23 CN CN201520939506.9U patent/CN205176554U9/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN205176554U9 (en) | 2016-06-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information |
Inventor after: Ma Shuiliang Inventor after: Meng Zuohong Inventor after: Yu Renxin Inventor after: Shu Rong Inventor after: Zheng Yingbing Inventor before: Guo Huosheng Inventor before: Yuan Mingdao Inventor before: Xu Yunqian Inventor before: He Huimin Inventor before: Zhang Xuhui |
|
| COR | Change of bibliographic data | ||
| CGPU | Change to patent or to utility model | ||
| CU01 | Correction of utility model patent |
Correction item: Denomination of Utility Model|Inventor Correct: Speed regulator testing device for channel complementary isolation low temperature drift collection|Ma Shuiliang|Meng Zuohong|Yu Renxin|Shu Rong|Zheng Yingbing False: Regulator testing device for channel complementary isolation low temperature drift collection|Guo Huosheng|Yuan Mingdao|Xu Yunqian|He Huimin|Zhang Xuhui Number: 16 Page: full text Volume: 32 |
|
| CU03 | Correction of utility model patent gazette |
Correction item: Denomination of Utility Model|Inventor Correct: Speed regulator testing device for channel complementary isolation low temperature drift collection|Ma Shuiliang|Meng Zuohong|Yu Renxin|Shu Rong|Zheng Yingbing False: Regulator testing device for channel complementary isolation low temperature drift collection|Guo Huosheng|Yuan Mingdao|Xu Yunqian|He Huimin|Zhang Xuhui Number: 16 Volume: 32 |
|
| ERR | Gazette correction | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160420 Termination date: 20161123 |