CN205122562U - Chip embedded package structure with additional strengthening - Google Patents
Chip embedded package structure with additional strengthening Download PDFInfo
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- CN205122562U CN205122562U CN201520928590.4U CN201520928590U CN205122562U CN 205122562 U CN205122562 U CN 205122562U CN 201520928590 U CN201520928590 U CN 201520928590U CN 205122562 U CN205122562 U CN 205122562U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a chip embedded package structure with additional strengthening belongs to the semiconductor packaging technology field. It includes chip monomer and film enveloping body, one or more than one the chip monomer is in by back embedded thin film enveloping body free upper surface of chip and film enveloping body's upper surface cover insulating thin -film layer, and in I opening of insulating thin -film layer is seted up to the upper surface of chip electrode, at insulating thin -film layer's upper surface formation rewiring metal level, electric connection is realized with the chip electrode respectively to the rewiring metal level, at the outmost I/O end that is equipped with of rewiring metal level I/O end department forms the connecting piece, film enveloping body's the back sets up silica -based reinforcing plate. The utility model discloses an attenuate product thickness, improved product reliability and realized multi -chip packaging structure.
Description
Technical field
The utility model relates to a kind of chip embedded encapsulating structure with strengthening structure, belongs to technical field of semiconductor encapsulation.
Background technology
Along with the development of semiconductor silicon technique, the critical size of chip is more and more less, in order to reduce costs, tends to the chip fabrication technique selecting more advanced integrated level higher when carrying out chip manufacturing, this just makes the size of chip more and more less, and the I/O density of chip surface is also more and more higher.But meanwhile the manufacturing process of printed circuit board (PCB) and surface mounting technology do not have greatly improved.For the chip that this I/O density ratio is higher, if carry out wafer level packaging, can form interconnection in order to ensure chip to be packaged and printed substrate must be low-density packaging pin by highdensity I/O fan-out, that is carry out the encapsulation of level chip fan-out, as shown in Figure 1, its chip to be packaged (1-1) realizes fan-out connection by substrate (1-6).But along with further developing of portable electric appts, electronic installation as mobile phone one class has been converted into the integrated system of comprehensive multifrequency nature from single communication tool, become versatile exquisite instrument, the deficiency of existing level chip fan-out packaging structure highlights day by day:
1, existing level chip fan-out packaging structure needs substrate (1-6) to realize fan-out, for the little chip with high number of pins then need multilager base plate (1-6) repeatedly fan-out could complete interconnection with printed substrate, not only increase mismatch probability and the heat radiation difficulty of ever-increasing interconnect pitch, reduce the reliability of product, and the existence of substrate (1-6) makes the thickness of whole encapsulating structure reduce, the body thickness of general existing level chip fan-out packaging structure is at 700 ~ 1500 microns;
2, existing level chip fan-out packaging structure needs substrate (1-6) to realize fan-out, often limits adding of the various chips with difference in functionality, is unfavorable for the integrated development of portable electric appts.
Utility model content
The purpose of this utility model is the deficiency overcoming current chip packages structure, the chip embedded encapsulating structure with reinforcement structure of the multi-chip package that provides a kind of thinning product thickness, improves product reliability, realizes.
the purpose of this utility model realizes like this:
A kind of chip embedded encapsulating structure with strengthening structure of the utility model, it comprises the chip monomer that upper surface has chip electrode and related circuit layout, the upper surface of the chip body of described chip monomer covers chip surface passivation layer and offers chip surface passivation layer opening, the upper surface exposed chip surface passivation layer opening of chip electrode
Also comprise thin film encapsulation body, chip monomer described in one or more embeds in thin film encapsulation body by the back side, insulating thin layer I is covered at the upper surface of described chip monomer and the upper surface of thin film encapsulation body, and offer insulating thin layer I opening in the upper surface of described chip electrode, discontinuous interconnection metal layer again and insulating thin layer II is optionally formed at the upper surface of insulating thin layer I, described interconnection metal layer again fills insulating thin layer I opening, described interconnection metal layer again and chip electrode described in each realize being electrically connected, and optionally realize two or more association described chip electrode between electric connection, input/output terminal is provided with at the outermost layer of interconnection metal layer again, described insulating thin layer II covers interconnection metal layer again and exposes its input/output terminal, connector is formed at described input/output terminal place, the back side of described thin film encapsulation body arranges silica-based stiffener, described silica-based stiffener arranges integrated structure towards the one side of thin film encapsulation body.
Described integrated structure is a plurality of protrusion or is depressed in the texture structure of described silica-based stiffener towards that face of thin film encapsulation body.
Described integrated structure is a kind of or several arbitrarily combination of fusiform structure, dots structure, wave structure.
The thickness range of described silica-based stiffener is for being not more than 200 microns.
The thickness range of described silica-based stiffener is 50 ~ 100 microns.
Described interconnection metal layer is again single or multiple lift.
The input/output terminal of described interconnection metal layer is again arranged at the periphery of the vertical area of chip monomer.
Described insulating thin layer I opening is implanted into metal column, and described metal column connects interconnection metal layer and ni/au layers again.
The size of described insulating thin layer I opening is not more than the size of chip surface passivation layer opening.
Described connector is solder bumps, welding block or metal derby.
Compare and existing scheme, the beneficial effects of the utility model are:
1, by thin film technique, in conjunction with wafer level, interconnection metal layer technology and flip-chip technology realize the fan-out packaging structure of single or multiple lift to the utility model again, be low-density packaging pin to guarantee that the little chip of the especially high number of pins of chip to be packaged or super tiny chip and printed substrate can realize highdensity I/O fan-out, do not need substrate, insert or underfill, be thinned whole encapsulating structure;
2, the utility model adopts the restructuring wafer encapsulation technology of chip package system collaborative design and advanced person and reliable interconnection technique, achieve the multichip packaging structure of difference in functionality, be conducive to the integrated development of portable electric appts, achieve the miniaturization of encapsulating structure, slimming and lightweight simultaneously;
3, the utility model apply materials, adopts thin-film material to be embedded in wherein by chip to be packaged, makes all around four faces and the back side of chip to be packaged all obtain physics and electic protection, prevent external interference, improve the reliability of encapsulating products;
4, the utility model utilizes film Filming Technology to replace existing technology, reduce the requirement of packaging technology to equipment, the film back side is provided with the intensity that the silica-based stiffener strengthening structure not only further enhances thin film encapsulation body simultaneously, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer, contribute to the reliability improving encapsulating products.
Accompanying drawing explanation
Fig. 1 is the generalized section of existing level chip fan-out packaging structure;
Fig. 2 A is the generalized section of the embodiment one of a kind of chip embedded encapsulating structure with reinforcement structure of the utility model;
Fig. 2 B is the front schematic view of thin film encapsulation body in Fig. 2 A, chip monomer, soldered ball position relationship;
Fig. 2 C is the distortion of Fig. 2 A;
Fig. 3 A is the generalized section of the embodiment two of a kind of chip embedded encapsulating structure with reinforcement structure of the utility model;
Fig. 3 B is the front schematic view of thin film encapsulation body in Fig. 3 A, chip monomer, soldered ball position relationship;
Fig. 4 is the generalized section of the embodiment three of a kind of chip embedded encapsulating structure with reinforcement structure of the utility model;
In figure:
IC wafers 100
Chip monomer 10, chip monomer 20
Chip body 11, chip body 21
Chip electrode 13, chip electrode 23
Chip surface passivation layer 15, chip surface passivation layer 25
Chip surface passivation layer opening 151, chip surface passivation layer opening 251
Thin film encapsulation body 3
Plural layer is Wiring technique layer 4 again
Interconnection metal layer 41 again
Input/output terminal 411
Insulating thin layer I 51
Insulating thin layer I opening 511
Insulating thin layer II 52
Connector 6
Silica-based stiffener 7.
Embodiment
Describe the utility model more fully hereinafter with reference to accompanying drawing now, exemplary embodiment of the present utility model shown in the drawings, thus scope of the present utility model is conveyed to those skilled in the art by the disclosure fully.But the utility model can realize in many different forms, and should not be interpreted as being limited to the embodiment set forth here.
Embodiment one, see Fig. 2 A and Fig. 2 B
Fig. 2 A is the generalized section of the embodiment one of a kind of chip embedded encapsulating structure with reinforcement structure of the utility model, chip embedded encapsulating structure of the present utility model comprises the chip monomer 10 that a back side embeds thin film encapsulation body 3, the upper surface of the chip body 11 of chip monomer 10 is with chip electrode 13 and related circuit layout thereof, chip surface passivation layer 15 covers the upper surface of chip body 11 and offers chip surface passivation layer opening 151, the upper surface exposed chip surface passivation layer opening 151 of chip electrode 13.The material of thin film encapsulation body 3 includes but not limited to epoxy-plastic packaging material; it is generally curing agent with High Performance Phenolic Resins; adding silicon powder etc. is filler; and add multiple additive mixture and form; it is first in molten condition at high temperature 175 ~ 185 DEG C; all around four faces and the back side of tight parcel chip monomer 10; can harden gradually after cooling; final molding; all around four faces and the back side of chip monomer 10 is made all to obtain physics and electic protection; prevent external interference, to improve its reliability.
Insulating thin layer I 51 covers the upper surface of chip monomer 10 and the upper surface of thin film encapsulation body 3, and offer insulating thin layer I opening 511 in the upper surface of chip electrode 13 by photoetching process or laser technology, the size of insulating thin layer I opening 511 is not more than the size of chip surface passivation layer opening 151, the rounded or polygon such as quadrangle, hexagon of the shape of its cross section.The material of insulating thin layer I 51 is generally the macromolecule such as epoxy resin, polyimides organic insulating material.Discontinuous interconnection metal layer again 41 is optionally formed at the upper surface of insulating thin layer I 51 and fills insulating thin layer I opening 511.Also can implant the metal column that copper etc. has conducting function in insulating thin layer I opening 511, described metal column connects interconnection metal layer 41 and ni/au layers 17 again.Interconnection metal layer 41 and chip electrode 13 realize being electrically connected again.Interconnection metal layer 41 can be individual layer again, and as shown in Figure 2 A, be provided with input/output terminal 411 at the outermost layer of interconnection metal layer 41 again, the number of input/output terminal 411 is arranged according to actual needs.For little chip or the super tiny chip of high number of pins, its input/output terminal 411 can be made to be arranged at the periphery of the vertical area of little chip or super tiny chip by the epitaxy technology of wafer level interconnection metal layer again, so that electrode signal fan-out that is individuality is less, electrode comparatively dense connects.As little for 1 × 1mm chip made 3 × 3mm encapsulating structure, I/O:20, pitch:0.4mm.Connector 6 can be formed at input/output terminal 411 place; connector 6 can be solder bumps, welding block or other metal connecting piece; solder bumps for connector 6 in Fig. 2 B; show the front schematic view of chip monomer 10 and the position relationship of thin film encapsulation body 3, solder bumps; visible chip monomer 10 is arranged at the inside of thin film encapsulation body 3; it all obtains physics and electic protection in four faces and the back side all around, improves its reliability.
The back side of thin film encapsulation body 3 arranges the silica-based stiffener 7 of silicon material, its thickness range is for being not more than 200 microns, and be good with its thickness range 50 ~ 100 microns, not only strengthen the intensity of thin film encapsulation body 3, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer 10, contribute to the reliability improving encapsulating products.
A kind of encapsulating structure with strengthening the chip embedded encapsulating structure of structure and can obtain body thickness 500 ~ 800 microns of the utility model, thinner more than traditional encapsulating structure, gentlier, less.Further, this silica-based stiffener is provided with the integrated structure of the shape such as fusiform structure, dots structure, wave structure of a plurality of protrusion or depression towards the one side of thin film encapsulation body, to strengthen the adhesion with thin film encapsulation body 3, also the reliability improving encapsulating products is contributed to, as shown in Figure 2 A.This integrated structure also can be the mixing composition several arbitrarily of the shapes such as fusiform structure, dots structure, wave structure.Integrated structure is generally a surface of the prior silica-based stiffener 7 that is shaped by dry method or wet etching, also simply can be shaped by physical method, such as, use forming tool to apply the shaping surface of external force at silica-based stiffener 7.
By adding the additive with functions such as that resist warping, antistatic, reinforcement particles in thin film encapsulation body 3, the proper property of thin film encapsulation body 3 can be strengthened.Silica-based stiffener 7 can be made in the encapsulating structure of some product to remove completely, to make the thickness of whole encapsulating structure thinning further, as shown in Figure 2 C.
Embodiment two, see Fig. 3 A and Fig. 3 B
The number of chip monomer can be more than one, adopts chip package system collaborative design, can realize the chip package of more difference in functionalitys.
Fig. 3 A is the generalized section of the embodiment two of a kind of chip embedded encapsulating structure with reinforcement structure of the utility model, chip embedded encapsulating structure of the present utility model comprises chip monomer 10 and the chip monomer 20 that two back sides embed thin film encapsulation body 3, and its upper surface is generally flush formation.The material of thin film encapsulation body 3 includes but not limited to epoxy-plastic packaging material; it is generally curing agent with High Performance Phenolic Resins; adding silicon powder etc. is filler; and add multiple additive mixture and form, it is first in molten condition at high temperature 175 ~ 185 DEG C, then can harden gradually; final molding; make all around four faces and the back side of chip monomer 10 and chip monomer 20 all obtain physics and electic protection, prevent external interference, to improve its reliability.
The upper surface of the chip body 11 of chip monomer 10 is with chip electrode 13 and related circuit layout thereof, chip surface passivation layer 15 covers the upper surface of chip body 11 and offers chip surface passivation layer opening 151, the upper surface exposed chip surface passivation layer opening 151 of chip electrode 13.The upper surface of the chip body 21 of chip monomer 20 is with chip electrode 23 and related circuit layout thereof, chip surface passivation layer 25 covers the upper surface of chip body 21 and offers chip surface passivation layer opening 251, the upper surface exposed chip surface passivation layer opening 251 of chip electrode 23.Insulating thin layer I 51 covers the upper surface of chip monomer 10, the upper surface of chip monomer 20 and the upper surface of thin film encapsulation body 3, and offer insulating thin layer I opening 511 in the upper surface of chip electrode 13, the size of insulating thin layer I opening 511 is not more than the size of chip surface passivation layer opening 151, chip surface passivation layer opening 251, the rounded or polygon such as quadrangle, hexagon of the shape of its cross section.Interconnection metal layer 41 is formed at the upper surface of insulating thin layer I 51 and fills insulating thin layer I opening 511 again.Also the metal column that copper etc. has conducting function can be implanted in insulating thin layer I opening 511.Interconnection metal layer 41 realizes being electrically connected with chip electrode 13, chip electrode 23 respectively again.Interconnection metal layer 41 can be individual layer again, as shown in Figure 3A, the local of chip monomer 10 and chip monomer 20 adjacent again interconnection metal layer 41 plays a part to be connected chip monomer 10 and chip monomer 20 simultaneously, makes to realize between chip monomer 10 and chip monomer 20 being electrically connected.In actual package structure, if the number of chip monomer is more than three or three, non-conterminous but also can realize being electrically connected by interconnection metal layer again between two or more chip electrodes be associated.Be provided with input/output terminal 411 at the outermost layer of interconnection metal layer 41 again, the parameter such as number, position, shape of input/output terminal 411 is arranged according to actual needs.Connector 6 can be formed at input/output terminal 411 place; connector 6 can be solder bumps, welding block or other metal connecting piece; solder bumps for connector 6 in Fig. 3 B; show the front schematic view of chip monomer 10, chip monomer 20 and the position relationship of thin film encapsulation body 3, solder bumps; visible chip monomer 10, chip monomer 20 are arranged at the inside of thin film encapsulation body 3; it all obtains physics and electic protection in four faces and the back side all around, improves its reliability.
The back side of thin film encapsulation body 3 arranges the silica-based stiffener 7 of silicon material, not only further enhance the intensity of thin film encapsulation body 3, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer 10, also contribute to the reliability improving encapsulating products.
Embodiment three, see Fig. 4
The encapsulating structure of embodiment three and embodiment one, embodiment two are similar; difference is: interconnection metal layer 41 also can be two-layer or two-layer above formation plural layer Wiring technique layer more again; all around four faces and the back side all obtain physics and electic protection for they; improve its reliability, as shown in Figure 4.Plural layer again Wiring technique layer with three layers of example; comprise again interconnection metal layer 41, again interconnection metal layer 43, again interconnection metal layer 45; be communicated with to meet multi information; and insulating thin layer II 52 is also multilayer; with plural layer again Wiring technique layer mate; be separately positioned on wherein, play the effects such as insulation, protection, reinforcing.The material of insulating thin layer II 52 is generally the macromolecule such as epoxy resin, polyimides organic insulating material.Plural layer again Wiring technique layer needs by repeatedly interconnection metal layer process forming again.
Be provided with input/output terminal at the outermost layer of plural layer Wiring technique layer again, the number of input/output terminal is arranged according to actual needs.Plural layer again Wiring technique layer input/output terminal place formed connector 6, connector 6 can be solder bumps, welding block or other metal connecting piece.
A kind of chip embedded encapsulating structure with strengthening structure of the utility model is not limited to above preferred embodiment, chip monomer 10 of the present utility model, chip monomer 20 is for IC chip, because it can reduce body thickness effectively, improve the flexibility of encapsulation, at the advantage highly significant of slim and microminiaturized application aspect, and its good heat dispersion, the application of this encapsulation also can expand to many different fields, as wireless, optics etc., but be not limited to this, any those skilled in the art are not departing from spirit and scope of the present utility model, according to any amendment that technical spirit of the present utility model is done above embodiment, equivalent variations and modification, all fall in protection range that the utility model claim defines.
Claims (10)
1. the chip embedded encapsulating structure with reinforcement structure, it comprises the chip monomer (10) that upper surface has chip electrode (13) and related circuit layout, the upper surface of the chip body (11) of described chip monomer (10) covers chip surface passivation layer (15) and offers chip surface passivation layer opening (151), upper surface exposed chip surface passivation layer opening (151) of chip electrode (13)
It is characterized in that: also comprise thin film encapsulation body (3), chip monomer (10) described in one or more embeds in thin film encapsulation body (3) by the back side, insulating thin layer I (51) is covered at the upper surface of described chip monomer (10) and the upper surface of thin film encapsulation body (3), and offer insulating thin layer I opening (511) in the upper surface of described chip electrode (13), discontinuous interconnection metal layer again (41) and insulating thin layer II (52) is optionally formed at the upper surface of insulating thin layer I (51), described interconnection metal layer again (41) fills insulating thin layer I opening (511), described interconnection metal layer again (41) realizes being electrically connected with chip electrode (13) described in each, and optionally realize two or more association described chip electrode between electric connection, input/output terminal (411) is provided with at the outermost layer of interconnection metal layer (41) again, described insulating thin layer II (52) covers interconnection metal layer (41) again and exposes its input/output terminal (411), connector (6) is formed at described input/output terminal (411) place, the back side of described thin film encapsulation body (3) arranges silica-based stiffener (7), described silica-based stiffener (7) arranges integrated structure towards the one side of thin film encapsulation body (3).
2. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: described integrated structure is a plurality of protrusion or is depressed in the texture structure of described silica-based stiffener (7) towards that face of thin film encapsulation body (3).
3. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1 and 2, is characterized in that: described integrated structure is a kind of or several arbitrarily combination of fusiform structure, dots structure, wave structure.
4. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: the thickness range of described silica-based stiffener (7) is for being not more than 200 microns.
5. a kind of chip embedded encapsulating structure with strengthening structure according to claim 4, is characterized in that: the thickness range of described silica-based stiffener (7) is 50 ~ 100 microns.
6. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: described interconnection metal layer again (41) is single or multiple lift.
7. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1 or 6, is characterized in that: the input/output terminal (411) of described interconnection metal layer again (41) is arranged at the periphery of the vertical area of chip monomer.
8. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, it is characterized in that: described insulating thin layer I opening (511) is implanted into metal column, described metal column connects interconnection metal layer and ni/au layers (17) again.
9. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1 or 8, is characterized in that: the size of described insulating thin layer I opening (511) is not more than the size of chip surface passivation layer opening.
10. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: described connector (6) is solder bumps, welding block or metal derby.
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| CN201520928590.4U CN205122562U (en) | 2015-11-20 | 2015-11-20 | Chip embedded package structure with additional strengthening |
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| CN201520928590.4U CN205122562U (en) | 2015-11-20 | 2015-11-20 | Chip embedded package structure with additional strengthening |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304586A (en) * | 2015-11-20 | 2016-02-03 | 江阴长电先进封装有限公司 | Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304586A (en) * | 2015-11-20 | 2016-02-03 | 江阴长电先进封装有限公司 | Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same |
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