CN205016525U - Capacitive diode cluster spare - Google Patents
Capacitive diode cluster spare Download PDFInfo
- Publication number
- CN205016525U CN205016525U CN201520633924.5U CN201520633924U CN205016525U CN 205016525 U CN205016525 U CN 205016525U CN 201520633924 U CN201520633924 U CN 201520633924U CN 205016525 U CN205016525 U CN 205016525U
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- active area
- diode
- semiconductor substrate
- epitaxial loayer
- doped region
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Abstract
Capacitive diode cluster spare is disclosed. Capacitive diode cluster spare includes: a conductivity type's semiconductor substrate, lie in the 2nd conductivity type's on the semiconductor substrate epitaxial layer, the 2nd conductivity type is different with a conductivity type, a conductivity type's isolation region passes the epitaxial layer from the surface of epitaxial layer and extends to among the semiconductor substrate to inject the first active area of first diode and the second active area of second diode in the epitaxial layer, and separate first active area and second active area each other, a conductivity type's first doped region is in first active area extends to the epitaxial layer from the epitaxial layer surface, the 2nd conductivity type's second doped region is in the second active area extends to the epitaxial layer from the epitaxial layer surface, and electrically conductive passageway, in first active area gets into semiconductor substrate from epitaxial layer surface extension for epitaxial layer and semiconductor substrate electricity each other connect. This capacitive diode cluster spare can regard as nonpolarity capacity cell, can improve the transient response speed of transient voltage inhibitor.
Description
Technical field
The utility model relates to microelectronics technology, more specifically, relates to capacitive diode assembly.
Background technology
Transient Voltage Suppressor TVS (TransientVoltageSuppressor) is the high-effect circuit brake developed on voltage-stabiliser tube basis.Profile and the common voltage-stabiliser tube of TVS diode are as good as, but due to the design of special Structure and energy, the transient response speed of TVS diode and surge absoption ability are far above common voltage-stabiliser tube.Such as, the response time of TVS diode is only 10
-12second, and the surge power up to thousands of watts can be absorbed.Under applied in reverse condition, when bearing a high-octane large pulse, the working impedance of TVS diode can be down to extremely low conduction value fast, thus allows big current to pass through, meanwhile, by voltage clamp at predeterminated level.Therefore, TVS diode can protect the precision components in electronic circuit from the damage of various surge pulse effectively.
The manufacturing process of traditional TVS diode is fairly simple, is generally by special shaped doped direct formation PN junction on P+ substrate/N+ substrate.The response speed of TVS diode and its electric capacity closely related.Traditional TVS diode is mainly used in the data terminal in consumer electronics product, as keyboard, side switch and power line etc.Because this type of terminal speed is comparatively slow, less demanding to the transient response speed of TVS diode, electric capacity is generally at more than 20pF.But video data line has high data transmission rate (up to 480M, some video data transmission rates reach more than 1G to its data transmission rate).Therefore, for the protection of video line, the transient response speed of traditional TVS diode just can not meet instructions for use.In transmission of video, the capacitance requirements of TVS diode is less than 1.0pF.
In existing TVS device, common rectifier diode, as the additional capacitor of small capacitances value, is connected with Zener diode.The capacitance of this TVS device will depend on the capacitance of additional capacitor.Due to the unilateal conduction characteristic of rectifier diode, this TVS device is also unidirectional device, can realize one-way low-capacitance ESD safeguard function.But due to ghost effect and dispel the heat bad, this TVS device is difficult to reach higher transient power.
Therefore, for the application of TVS device, expect the capacitive device of development of new, while raising transient response speed, take into account unidirectional and bidirectional applications requirement, reduce process complexity and cost, and high protection voltage is provided.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of capacitive diode assembly that may be used for unidirectional or two-way TVS device, and this capacitive diode assembly has ultra-low capacitance, thus improves the transient response speed of TVS device.
According to one side of the present utility model, a kind of capacitive diode assembly is provided, comprises: the Semiconductor substrate of the first conduction type; Be positioned at the epitaxial loayer of the second conduction type in Semiconductor substrate, the second conduction type is different from the first conduction type; The isolated area of the first conduction type, extend to Semiconductor substrate from the surface of epitaxial loayer through epitaxial loayer, thus in epitaxial loayer, limit the first active area of the first diode and the second active area of the second diode, and by the first active area and the second active area spaced; First doped region of the first conduction type, extends to epitaxial loayer in the first active area from epi-layer surface; Second doped region of the second conduction type, extends to epitaxial loayer in the second active area from epi-layer surface; And conductive channel, extend into Semiconductor substrate in the first active area from epi-layer surface, epitaxial loayer and Semiconductor substrate are electrically connected to each other.
Preferably, described capacitive diode assembly also comprises: be positioned at the insulating barrier on epitaxial loayer; And interconnecting line, through insulating barrier arrive the first doped region and and the second doped region, and to be electrically connected with the two.
Preferably, between the first doped region and epitaxial loayer, form the PN junction of the first diode, between Semiconductor substrate and epitaxial loayer, form the PN junction of the second diode.
Preferably, the first diode and the second diode adopt Semiconductor substrate and interconnecting line to be connected in antiparallel.
Preferably, the doping content of the first doped region is greater than 1.0 × 10
18cm
-3, the doping content of the second doped region is greater than 8.0 × 10
19cm
-3.
Preferably, the thickness of epitaxial loayer is greater than 2 μm.
Preferably, the first conduction type is one of N-type and P type, and the second conduction type is another in N-type and P type.
According to another aspect of the present utility model, provide a kind of method manufacturing capacitive diode assembly, comprising: in the Semiconductor substrate of the first conduction type, form the epitaxial loayer of the second conduction type, the second conduction type is different from the first conduction type; Adopt the first doping process, form the isolated area of the first conduction type, isolated area extends to Semiconductor substrate from the surface of epitaxial loayer through epitaxial loayer, thus in epitaxial loayer, limit the first active area of the first diode and the second active area of the second diode, and by the first active area and the second active area spaced; Adopt the second doping process, form the first doped region of the first conduction type, the first doped region extends to epitaxial loayer in the first active area from epi-layer surface; Adopt the 3rd doping process, form the second doped region of the second conduction type, the second doped region extends to epitaxial loayer in the first active area from epi-layer surface; And formation conductive channel, described conductive channel extends into Semiconductor substrate in the first active area from epi-layer surface, and epitaxial loayer and Semiconductor substrate are electrically connected to each other.
Preferably, the step forming conductive channel comprises: on epitaxial loayer, form insulating barrier; And the conductive channel formed through insulating barrier.
Preferably, described method also comprises the interconnecting line formed through insulating barrier, and interconnecting line is electrically connected with the first doped region with the second doped region.
Preferably, the first conduction type is one of N-type and P type, and the second conduction type is another in N-type and P type.
Comprise the first diode and second diode of reverse parallel connection according to the capacitive diode assembly of embodiment of the present utility model, there is almost identical forward characteristic in the two directions, thus can as non-polar electric capacity.Described ultra-low capacitance capacitive diode assembly can realize on very little chip area, drastically increases the applicability of semiconductor device integration packaging, makes device architecture be applicable to multiple different packing forms.Because Semiconductor substrate is directly drawn as another electrode, can reduce by 1 bonding gold wire when encapsulating, cost of manufacture can be reduced significantly, being conducive to industrialization.The utility model namely provide a kind of like this can the ultra-low capacitance biphase rectification construction module of batch making.In addition, the manufacture method of this product and the bipolar process of standard mutually compatible.
This capacitive diode assembly and Zener diode are connected in series, and form unidirectional or bidirectional transient voltage suppressor.Only can increase the conduction voltage drop of 0.7V when described ultra-low capacitance capacitive diode assembly is connected with any TVS device on the voltage of former TVS device, change the electrology characteristic of former TVS device hardly.Such as, by described ultra-low capacitance capacitive diode assembly and a forward voltage 0.8V, reverse breakdown voltage 20V, electric capacity is that the unidirectional TVS device Series Package of 20pF is in a shell, a forward voltage 1.5V will be obtained, reverse breakdown voltage 20.7V, and electric capacity only has the ultra-low capacitance TVS device less than 1pF.
Described capacitive diode assembly just always bears transient power by diode.When surge occurs, forward diode will to be less than 10
-12second speed open instantaneously, while producing a minimum pressure drop, surge current is passed through smoothly, ensures that self is not damaged, continue the effect keeping reduction electric capacity.
Because capacitive diode assembly has ultralow capacitance, therefore, the response speed of TVS device can be improved, widen the range of application of all kinds of device greatly.Such as, after some traditional TVS protection devices and described ultra-low capacitance capacitive diode assembly combine, electric capacity is reduced greatly, also can be applied in the data transmission network of high frequency.
In Transient Voltage Suppressor; if capacitive diode assembly and Zener diode are formed on different semiconductor chips; manufacturing process both then can optimizing respectively more neatly; make capacitive diode assembly provide low capacitance to improve the transient response speed of TVS device, Zener diode provides high-breakdown-voltage to obtain required protection voltage level.After forming capacitive diode assembly and Zener diode respectively, adopt both bonding line connections, and be encapsulated in a shell.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the utility model embodiment, above-mentioned and other objects, features and advantages of the present utility model will be more clear, in the accompanying drawings:
Fig. 1 illustrates the structural representation of the capacitive diode assembly according to the utility model first embodiment; And
Fig. 2 a to 2g illustrates the sectional view in each stage of manufacture method of the capacitive diode assembly according to the utility model second embodiment.
Embodiment
In more detail the utility model is described hereinafter with reference to accompanying drawing.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.In addition, may some known part not shown.
Be to be understood that, when describing certain structure, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if this structure overturn, this one deck, a region will be positioned at another layer, another region " below " or " below ".If the form of presentation of " A is directly on B " or " A also adjoins with it on B " in order to describe the situation being located immediately at another layer, another over, will be adopted herein.
In addition, mention the first conduction type and the second conduction type when describing the conduction type of semi-conducting material, wherein the first conduction type is one of P type and N-type, and the second conduction type is another in P type and N-type.
The utility model can present in a variety of manners, below will describe some of them example.
Fig. 1 illustrates the structural representation of the capacitive diode assembly according to the utility model first embodiment.This capacitive diode assembly comprises the diode of two reverse parallel connections formed on a semiconductor substrate.
As shown in Figure 1, P++ type Semiconductor substrate 101 forms N-type epitaxial loayer 103.The thickness of epitaxial loayer 103 is such as greater than 2 μm.P+ type isolated area 104 extends to Semiconductor substrate 101 from the surface of epitaxial loayer 103 through epitaxial loayer 103, thus in epitaxial loayer 103, limit the first active area of the first diode and the second active area of the second diode.Isolated area 104 by the first active area and the second active area spaced.Correspondingly, isolated area 104 comprises the peripheral part around the first active area and the second active area, and by the spaced mid portion in the first active area and the second active area.
P++ type doped region 110 is positioned at the first active area, extends to epitaxial loayer 103 from epitaxial loayer 103 surface.Such as, the doping content of doped region 110 is for being greater than 1.0 × 10
18cm
-3.N++ doped region 111 is positioned at the second active area, extends to epitaxial loayer 103 from epitaxial loayer 103 surface.Such as, the doping content of doped region 111 is for being greater than 8.0 × 10
19cm
-3.
Insulating barrier 120 is positioned at above epitaxial loayer 103.Conductive channel 107, through insulating barrier 120 and epitaxial loayer 103, enters in Semiconductor substrate 101, thus epitaxial loayer 103 and Semiconductor substrate 101 is electrically connected to each other.Interconnecting line 108 arrives the top surface of doped region 110 and 111 through insulating barrier 120, thus the two is electrically connected to each other.Interconnecting line 108 also for the electrical connection between external circuit, such as, as signal end I/O.
In the capacitive diode assembly of this embodiment, adopt conductive channel 107 by epitaxial loayer 103 and Semiconductor substrate 101 short circuit each other, make that doped region 110, epitaxial loayer 103, current path (as indicated by a dashed arrow in the figure) between conductive channel 107 and Semiconductor substrate 101 only exist a PN junction.Thus, form the PN junction of the first diode between doped region 110 and epitaxial loayer 103, between Semiconductor substrate 101 and epitaxial loayer 103, form the PN junction of the second diode, thus realize the basic structure of the first diode and the second diode respectively.
Metal layer on back 160 is formed, as earth terminal GND at the back side of Semiconductor substrate 101.First diode and the second diode adopt Semiconductor substrate 101 and interconnecting line 108 to be connected in antiparallel.
This capacitive diode assembly comprises the first diode and second diode of reverse parallel connection, utilizes the low pressure drop of diode forward and the characteristic of low on-resistance to realize the electrical characteristics of ultra-low capacitance biphase rectification.This capacitive diode assembly can be used for unidirectional or two-way TVS device as non-polar electric capacity.
Fig. 2 a to 2g illustrates the sectional view in each stage of manufacture method of the capacitive diode assembly according to the utility model second embodiment.In the following description, the conduction type describing semi-conducting material is specially one of P type and N-type.Be appreciated that if the conduction type of each semi-conducting material that reverses, also can obtain the semiconductor device of identical function.
As shown in Figure 2 a, P++ type Semiconductor substrate 101 forms N-type epitaxial loayer 103 and insulating barrier 120 successively.
Semiconductor substrate 101 is such as monocrystalline substrate, and N-type epitaxy layer 103 is such as silicon epitaxy layer, and adopts suitable dopant to be doping to the conduction type of expectation respectively.In order to form P type or n type semiconductor layer or region, the dopant of respective type can be mixed in semiconductor layer and region.Such as, P-type dopant comprises boron, and N-type dopant comprises phosphorus or arsenic.In this embodiment, Semiconductor substrate 101 for doping content be 10
19cm
-3the heavy doping P++ substrate of magnitude, its resistivity is about 0.004 ~ 0.006 Ω cm.
Epitaxial loayer 103 can adopt known depositing operation to be formed.Such as, depositing operation can be selected from the one in electron beam evaporation (EBM), chemical vapour deposition (CVD) (CVD), ald (ALD), sputtering.In this embodiment, epitaxial loayer 103 is light dope N-epitaxial loayer, and its resistivity is not less than 5.5 Ω cm, and thickness is not less than 5.5 μm.
Insulating barrier 120 can adopt sputtering or thermal oxidation to be formed.Such as, insulating barrier 120 is silicon oxide layers that thermal oxidation is formed, in follow-up doping step, insulating barrier 120 as protective layer, and using the interlayer insulating film as resulting devices.
Subsequently, in epitaxial loayer, the isolated area 104 of P+ type is made, as shown in Figure 2 b.This isolated area 104 limits the active area of two diodes, and is isolated from each other the active area of two diodes.In this embodiment, isolated area 104 is such as B
30the doping content that latex source technique makes is 4.0 × 10
19cm
-3p++ isolated area.Isolated area 104 to be formed in epitaxial loayer 103 and to extend to Semiconductor substrate 101.Described isolated area will be connected from the back side with Semiconductor substrate 101 and draw.Isolated area concentration will affect the conducting resistance of rectifying device, and those skilled in the art can control isolated area concentration according to device requirement, but too low isolated area concentration will seriously restrict the current capacity of rectifying device, therefore should control be not less than 10
19cm
-3the order of magnitude.
Subsequently, in the active area of the first diode, the doped region 110 of P++ type is made, as shown in Figure 2 c.In this embodiment, doped region 110 for the concentration that latex source diffuses to form be 1.0 × 10
18~ 9.9 × 10
19cm
-3heavily doped region.Those skilled in the art can use ion implantation or other method of diffusion to form described doped region 110 according to actual processing conditions.Described doped region 110 concentration should be not less than the doping content of described epitaxial loayer 103.
Subsequently, make N++ doped region 111 in the active area of the second diode, and make N++ doped region 112 in the active area of the first diode, as shown in Figure 2 d.Described doped region 112 is across the interface between the first active area and the peripheral part of isolated area.Preferably, doped region 112 is also around doped region 110, thus stop ring in coating-forming voltage.In this embodiment, the concentration that doped region 112 makes for phosphoric diffusion technology is about 8.0 × 10
19cm
-3~ 2.0 × 10
20cm
-3n++ doped region.
It will be appreciated by those skilled in the art that can the position of each doped region of appropriate design, size and doping content to control the electric capacity of rectifying tube, obtain satisfactory ultra-low capacitance capacitive diode assembly.
Open the access opening on insulating barrier 120 and lead-in wire electrode hole subsequently, as shown in Figure 2 e.It should be noted that described lead-in wire electrode hole must retain the contact window that can expose doped region 112 and isolated area 104 simultaneously.
After insulating barrier 120 forms access opening, carve a part for epitaxial loayer 103 and Semiconductor substrate 101 further via this pitting, until the desired depth place entering Semiconductor substrate 101 stops.
Subsequently, conductive channel and interconnecting line is made, as shown in figure 2f.Conductive channel 107, through insulating barrier 120 and epitaxial loayer 103, enters in Semiconductor substrate 101.In this embodiment, use metallic aluminium as conductive channel and interconnecting line.Conductive channel 107 is by epitaxial loayer 103 and Semiconductor substrate 101 short circuit electrical connection.The doped region 110 being produced on the first active area is electrically connected with the doped region 111 being produced on the second active area by interconnecting line 108, and can by extraction as signal end I/O.
Subsequently, by chip thinning and back face metalization, as shown in Figure 2 g.Metal layer on back 160 is formed, as earth terminal GND at the back side of Semiconductor substrate 101.
In this embodiment, use gold as metal layer on back 106.Those skilled in the art can select different metal or metal alloy as metal layer on back according to packing forms, as gold, silver, copper, titanium silver, titanium nickel gold etc.
It should be noted that P+ or P++ represents the heavy doping of P type in the above-described example, N+ or N++ represents N-type heavy doping, and N-represents N-type light dope.Here, heavy doping and light dope are relative concepts, represent that heavily doped doping content is greater than lightly doped doping content, and the restriction not to concrete doping content scope.
Can find out, according to device of the present utility model, ultra-low capacitance capacitive diode assembly can be prepared with simple step.Contact with P++ Semiconductor substrate 101 by P+ isolated area 104 is extended to, using P++ Semiconductor substrate 101 as earth terminal GND, and will not draw from front by earth terminal.So not only be conducive to reducing chip size, device architecture can also be made to be applicable to multiple different packing forms.In addition, P++ Semiconductor substrate 101 is directly drawn as ground connection GND electrode, can reduce by 1 bonding gold wire when encapsulating, cost of manufacture can be reduced significantly, being beneficial to industrialization.According to the utility model make ultra-low capacitance capacitive diode assembly according to different environments for use, can free definition signal end I/O and earth terminal GND.
If capacitive diode assembly is formed on a semiconductor chip, as independent device, the Zener diode tandem compound that the ultra-low capacitance capacitive diode assembly that then only the utility model need be used to provide and traditional handicraft make encapsulates, a ultra-low capacitance Zener diode can be obtained, almost whole electrology characteristics that the Zener diode possessing the making of described traditional handicraft possesses by this diode, obtain ultralow capacitance simultaneously.
In the above description, known structural element and step are not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, corresponding structural element and step can be realized.In addition, in order to form identical structural element, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.
Above embodiment of the present utility model is described.But these embodiments are only used to the object illustrated, and are not intended to limit scope of the present utility model.Scope of the present utility model is by claims and equivalents thereof.Do not depart from scope of the present utility model, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should drop within scope of the present utility model.
Claims (6)
1. a capacitive diode assembly, is characterized in that, comprising:
The Semiconductor substrate of the first conduction type;
Be positioned at the epitaxial loayer of the second conduction type in Semiconductor substrate, the second conduction type is different from the first conduction type;
The isolated area of the first conduction type, extend to Semiconductor substrate from the surface of epitaxial loayer through epitaxial loayer, thus in epitaxial loayer, limit the first active area of the first diode and the second active area of the second diode, and by the first active area and the second active area spaced;
First doped region of the first conduction type, extends to epitaxial loayer in the first active area from epi-layer surface;
Second doped region of the second conduction type, extends to epitaxial loayer in the second active area from epi-layer surface; And
Conductive channel, extends into Semiconductor substrate in the first active area from epi-layer surface, and epitaxial loayer and Semiconductor substrate are electrically connected to each other.
2. capacitive diode assembly according to claim 1, is characterized in that, also comprise:
Be positioned at the insulating barrier on epitaxial loayer; And
Interconnecting line, through insulating barrier arrive the first doped region and and the second doped region, and to be electrically connected with the two.
3. capacitive diode assembly according to claim 1, is characterized in that, forms the PN junction of the first diode between the first doped region and epitaxial loayer, forms the PN junction of the second diode between Semiconductor substrate and epitaxial loayer.
4. capacitive diode assembly according to claim 2, is characterized in that, the first diode and the second diode adopt Semiconductor substrate and interconnecting line to be connected in antiparallel.
5. capacitive diode assembly according to claim 1, wherein, the thickness of epitaxial loayer is greater than 2 μm.
6. capacitive diode assembly according to any one of claim 1 to 5, is characterized in that, the first conduction type is one of N-type and P type, and the second conduction type is another in N-type and P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520633924.5U CN205016525U (en) | 2015-08-20 | 2015-08-20 | Capacitive diode cluster spare |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520633924.5U CN205016525U (en) | 2015-08-20 | 2015-08-20 | Capacitive diode cluster spare |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205016525U true CN205016525U (en) | 2016-02-03 |
Family
ID=55215113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520633924.5U Withdrawn - After Issue CN205016525U (en) | 2015-08-20 | 2015-08-20 | Capacitive diode cluster spare |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205016525U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185783A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
-
2015
- 2015-08-20 CN CN201520633924.5U patent/CN205016525U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185783A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN105185783B (en) * | 2015-08-20 | 2018-08-24 | 北京燕东微电子有限公司 | Capacitive diode assembly and its manufacturing method |
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| GR01 | Patent grant | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20160323 Address after: 101500 Beijing Qingyuan Miyun Road Economic Development Zone No. 3 building 2-3 Patentee after: Beijing East Semiconductor Technology Co., Ltd. Address before: 100015 Beijing city Chaoyang District Dongzhimen West eight room Wanhong No. 2 West Street Patentee before: Beijing Yandong Microelectronic Co., Ltd. |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20160203 Effective date of abandoning: 20180824 |
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| AV01 | Patent right actively abandoned |