CN204991716U - Ultra -thin IGBT chip of low concentration - Google Patents
Ultra -thin IGBT chip of low concentration Download PDFInfo
- Publication number
- CN204991716U CN204991716U CN201520585638.6U CN201520585638U CN204991716U CN 204991716 U CN204991716 U CN 204991716U CN 201520585638 U CN201520585638 U CN 201520585638U CN 204991716 U CN204991716 U CN 204991716U
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- ultra
- low concentration
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides an ultra -thin IGBT chip of low concentration, belongs to semiconductor device and makes the field. Including substrate (1) of P type, be equipped with first epitaxial layer (2) and second epitaxial layer (3) of N type in proper order on substrate (1), set up the MOS structure on second epitaxial layer (3), the cover of chip the top has metal level (4), its characterized in that: the doping concentration of substrate (1) is 1015-1017 cm3, and the thickness of substrate (1) is 1-20 mu m. This ultra -thin IGBT chip of low concentration, with the thickness attenuate of substrate, simultaneously the concentration with the substrate reduces, thereby has promoted the frequency of operation that the shutoff speed of chip promoted the product, has saved for improving the process that its frequency of operation shines electron irradiation and high temperature annealing in the PT type IGBT manufacture process to and processing procedure back technology and laser scanning's complicated process in the NPT type IGBT manufacture process, improve chip flow efficiency and reduce cost.
Description
Technical field
The igbt chip that low concentration is ultra-thin, belongs to field of manufacturing semiconductor devices.
Background technology
The structure of traditional PT type igbt chip is as shown in Figure 2: take turns doing the first epitaxial loayer 2 and the second epitaxial loayer 3 on substrate 1, then on the second epitaxial loayer 3, do MOS structure and complete chip manufacturing.Applicant finds, when actual fabrication, the thickness of this substrate 1 is approximately 200 ~ 400 μm.Because the thickness of substrate 1 is thicker, therefore impedance is comparatively large, thus loss when causing conducting is larger.For reducing loss during conducting, requiring higher to the doping content of substrate 1, being about 10
18~ 10
19individual/cm
3, but so, cause again the number of cavities entering epitaxial loayer during conducting a lot, turn-off speed is slow, and conditions of streaking is comparatively serious.
In order to head it off, in the prior art, after chip is finished, carry out electron irradiation or PT doping or other techniques to chip make to produce defect in chip, accelerate the consumption of hole and electronics, but after producing defect by chip during corresponding technique, defect can produce equally in the MOS structure of the second epitaxial loayer 3, for ensureing the quality of product, also to carry out defect repair by high annealing, this complex process, process conditions are difficult to grasp, larger difference is there is between batch, simultaneously in the whole course of processing, higher to the requirement of process equipment, equipment costly, therefore production cost is high.
Summary of the invention
The technical problems to be solved in the utility model is: overcome the deficiencies in the prior art, provides a kind of and the doping content of IGBT substrate is reduced, simultaneously reduced thickness, have turn-off speed fast, reduce the igbt chip that the low concentration of conditions of streaking advantage is ultra-thin.
The utility model solves the technical scheme that its technical problem adopts: the igbt chip that this low concentration is ultra-thin, comprise the substrate of P type, substrate is provided with the first epitaxial loayer and second epitaxial loayer of N-type successively, second epitaxial loayer arranges MOS structure, chip the top is coated with metal level, it is characterized in that: the doping content of substrate is 10
15~ 10
17individual/cm
3, the thickness of substrate is 1 ~ 20 μm.
Preferably, the thickness of described substrate is 1 ~ 10 μm.
The igbt chip that a kind of low concentration is ultra-thin, comprise the substrate of N-type, substrate is provided with the first epitaxial loayer and second epitaxial loayer of P type successively, the second epitaxial loayer arranges MOS structure, chip the top is coated with metal level, it is characterized in that: the doping content of substrate is 10
15~ 10
17individual/cm
3, the thickness of substrate is 1 ~ 20 μm.
Preferably, the thickness of described substrate is 1 ~ 10 μm.
Compared with prior art, the beneficial effect that the utility model has is:
1, to compare prior art, in the igbt chip that this low concentration is ultra-thin, the thickness of substrate is carried out thinning, reduce the impedance of substrate, the doping content of substrate is reduced simultaneously, make the number of cavities entering epitaxial layer region relatively less, therefore there is turn-off speed fast, reduce the advantage of conditions of streaking, effectively improve the operating frequency of product.
2, because thinning and doped in concentrations profiled all belong to routine techniques means, therefore complex process degree reduces greatly.Eliminating the operation of shining electron irradiation and high annealing in PT type IGBT manufacture process for improving its operating frequency simultaneously, improving chip flow efficiency and greatly reducing production cost simultaneously.
3, in the igbt chip that this concentration is ultra-thin, the type of substrate and epitaxial loayer can be replaced, then applicable in the chip of the IGBT of P channel.
4, the application is also applicable to the production of other high-voltage switch gear semiconductor element.
Accompanying drawing explanation
Fig. 1 is the ultra-thin igbt chip structural representation of low concentration.
Fig. 2 is the T-shaped igbt chip structural representation of conventional P.
Wherein: 1, substrate 2, first epitaxial loayer 3, second epitaxial loayer 4, metal level.
Embodiment
Fig. 1 is most preferred embodiment of the present utility model, is described further below in conjunction with accompanying drawing 1 ~ 2 pair of the utility model.
Embodiment 1:
As shown in Figure 1, the igbt chip that low concentration is ultra-thin, comprises substrate 1, is disposed with the first epitaxial loayer 2 and the second epitaxial loayer 3 on substrate 1, above the second epitaxial loayer 3, makes MOS structure, then at the top covering metal layer 4 of chip.In the present embodiment, substrate 1 is P type, and the first epitaxial loayer 2 and the second epitaxial loayer 3 are respectively N-type.
In the igbt chip that this low concentration is ultra-thin, the doping content of substrate 1 is lower, and its doping content is 10
15~ 10
17individual/cm3, carry out thinning to substrate 1 after making the MOS structure above the first epitaxial loayer 2, second epitaxial loayer 3 and the second epitaxial loayer 3 on substrate 1, its thickness is kept to 1 ~ 20 μm, and preferred thickness is 1 ~ 10 μm.
In the igbt chip that this low concentration is ultra-thin, thinning owing to carry out substrate 1, therefore reach the effect reducing substrate 1 impedance.Reduce the doping content of substrate 1, the number of cavities therefore entering epitaxial layer region when conducting is relatively less simultaneously, therefore has turn-off speed fast simultaneously, reduces the advantage of conditions of streaking, effectively improves the operating frequency of product.
Because thinning and doped in concentrations profiled all belong to routine techniques means, therefore complex process degree reduces greatly.Eliminating the operation of shining electron irradiation and high annealing in PT type IGBT manufacture process for improving its operating frequency simultaneously, improving chip flow efficiency and greatly reducing production cost simultaneously.
Embodiment 2:
Embodiment 2 is with the difference of embodiment 1: in the present embodiment, the type of semiconductor is contrary with embodiment 1, and wherein substrate 1 is N-type, and the second epitaxial loayer 2 and the 3rd epitaxial loayer 3 are P type, its course of work and operation principle identical with embodiment 1.
The execution mode of the igbt chip that this low concentration is ultra-thin is applicable in the production of other thyristors simultaneously.
The above, it is only preferred embodiment of the present utility model, be not restriction the utility model being made to other form, any those skilled in the art may utilize the technology contents of above-mentioned announcement to be changed or be modified as the Equivalent embodiments of equivalent variations.But everyly do not depart from technical solutions of the utility model content, any simple modification, equivalent variations and the remodeling done above embodiment according to technical spirit of the present utility model, still belong to the protection range of technical solutions of the utility model.
Claims (4)
1. the igbt chip that a low concentration is ultra-thin, comprise the substrate (1) of P type, substrate (1) is provided with the first epitaxial loayer (2) and second epitaxial loayer (3) of N-type successively, second epitaxial loayer (3) arranges MOS structure, chip the top is coated with metal level (4), it is characterized in that: the doping content of substrate (1) is 10
15~ 10
17individual/cm
3, the thickness of substrate (1) is 1 ~ 20 μm.
2. the igbt chip that low concentration according to claim 1 is ultra-thin, is characterized in that: the thickness of described substrate (1) is 1 ~ 10 μm.
3. the igbt chip that a low concentration is ultra-thin, comprise the substrate (1) of N-type, substrate (1) is provided with the first epitaxial loayer (2) and second epitaxial loayer (3) of P type successively, second epitaxial loayer (3) arranges MOS structure, chip the top is coated with metal level (4), it is characterized in that: the doping content of substrate (1) is 10
15~ 10
17individual/cm
3, the thickness of substrate (1) is 1 ~ 20 μm.
4. the igbt chip that low concentration according to claim 3 is ultra-thin, is characterized in that: the thickness of described substrate (1) is 1 ~ 10 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520585638.6U CN204991716U (en) | 2015-08-06 | 2015-08-06 | Ultra -thin IGBT chip of low concentration |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201520585638.6U CN204991716U (en) | 2015-08-06 | 2015-08-06 | Ultra -thin IGBT chip of low concentration |
Publications (1)
Publication Number | Publication Date |
---|---|
CN204991716U true CN204991716U (en) | 2016-01-20 |
Family
ID=55126051
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201520585638.6U Active CN204991716U (en) | 2015-08-06 | 2015-08-06 | Ultra -thin IGBT chip of low concentration |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN204991716U (en) |
-
2015
- 2015-08-06 CN CN201520585638.6U patent/CN204991716U/en active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101640186B (en) | Manufacturing method of isolated gate bipolar transistor integrated fast recovery diode | |
CN104404626B (en) | The phosphorus diffusion method of Physical Metallurgy polysilicon solar cell | |
CN113161230B (en) | Diffusion process of phosphorus-boron synchronous one-time diffusion graded junction chip | |
CN104409507B (en) | low on-resistance VDMOS device and preparation method | |
CN103367157A (en) | Preparation method of super junction MOSFET | |
CN112271214A (en) | IGBT device with shielding gate structure and manufacturing method | |
CN103022099B (en) | A kind of IGBT collector structure and preparation method thereof | |
CN105374668B (en) | Heavily doped silicon substrate high quality shielding type diffusion method | |
CN103117328A (en) | Phosphorous gettering method of metallurgy polycrystalline silicon wafer, silicon wafer and solar cell prepared by silicon wafer | |
US9391182B2 (en) | Trench insulated-gate bipolar transistor and manufacture method thereof | |
CN204991716U (en) | Ultra -thin IGBT chip of low concentration | |
CN102244096A (en) | 3300V planar non-punch-through insulated gate bipolar transistor chip and manufacturing process thereof | |
CN104659159A (en) | Preparation method of selective emitting electrode crystalline silicon solar cell | |
CN109671620B (en) | Impurity diffusion process in semiconductor device manufacturing process | |
CN107403727A (en) | The manufacture method and fast recovery diode of a kind of fast recovery diode | |
CN102270701A (en) | One-step diffusion process of silicon solar cell with selective emitter | |
CN104616986A (en) | Preparation method of fast recovery diode | |
CN204332965U (en) | A kind of planar gate IGBT | |
CN207367981U (en) | A kind of high-frequency I GBT chips of multilayer epitaxial | |
CN102931223B (en) | IGBT collector structure | |
CN104393032A (en) | Plane gate insulated gate bipolar transistor (IGBT) and manufacturing method thereof | |
CN102110603B (en) | Structural design for PN junction embedded glass passivated device | |
CN106653835A (en) | IGBT structure and manufacturing method of back side of IGBT structure | |
CN201699018U (en) | High-power planar junction unilateral TVS diode chip | |
CN201699017U (en) | High-power bidirectional TVS diode chip adopting planar junction |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |