CN204948030U - Low-power consumption ultra-wideband low-noise amplifier - Google Patents
Low-power consumption ultra-wideband low-noise amplifier Download PDFInfo
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- CN204948030U CN204948030U CN201520755064.2U CN201520755064U CN204948030U CN 204948030 U CN204948030 U CN 204948030U CN 201520755064 U CN201520755064 U CN 201520755064U CN 204948030 U CN204948030 U CN 204948030U
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Abstract
The utility model provides a kind of low-power consumption ultra-wideband low-noise amplifier, is operated in 3-8GHz frequency band.This amplifier comprises: input stage circuit, the input connection signal input of this input stage circuit, the input signal of Received signal strength input input; Two-stage cascode resistance-capacitance coupling amplification grade circuit, the input of this two-stage cascode resistance-capacitance coupling amplification grade circuit connects the output of described input stage circuit, amplifies described input signal, and exports the signal after amplifying; Export buffer stage circuit, the input of this output buffer stage circuit is connected with the output of described two-stage cascode resistance-capacitance coupling amplification grade circuit, exports the signal after described amplification to signal output part.Amplifier of the present utility model have low noise, low in energy consumption, with wide advantage.
Description
Technical field
The utility model relates to technical field of radio frequency integrated circuits, refers to a kind of low-power consumption ultra-wideband low-noise amplifier especially.
Background technology
Along with the development of technology for radio frequency, the requirement of people to high-speed radio-frequency communication quality is more and more higher, and as the first order of radio front end receiver, traditional low noise amplifier obviously can not meet the multiple requirement of people for transfer of data.Due to the short-distance wireless communication technology that ultra-wide band radio-frequency communication system is more high-quality, safer and faster speed, so ultra-wideband low-noise amplifier can better meet the demand of people.
Because the receiver of carrying radio-frequency information function needs to continue the state being in wait state or information transmit-receive, low noise amplifier is again the module that in whole receiver, power consumption is larger, so its power problems is the focus that people study always, the low noise amplifier therefore designing and Implementing low-power consumption is the key problem solving radio-frequency transmitter flying power.
But it is high to there is power consumption in existing low noise amplifier, the problem that frequency band is narrow.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of low-power consumption ultra-wideband low-noise amplifier, and this amplifier can be operated in 3-8GHz frequency range, is solved that custom low noise amplifier power consumption is high, the problem of narrow bandwidth.
For solving the problems of the technologies described above, embodiment of the present utility model provides a kind of low-power consumption ultra-wideband low-noise amplifier, comprising:
Input stage circuit, the input signal of the input Received signal strength input input of this input stage circuit;
Two-stage cascode resistance-capacitance coupling amplification grade circuit, the input of this two-stage cascode resistance-capacitance coupling amplification grade circuit connects the output of described input stage circuit, amplifies described input signal, and exports the signal after amplifying;
Export buffer stage circuit, the input of this output buffer stage circuit is connected with the output of described two-stage cascode resistance-capacitance coupling amplification grade circuit, exports the signal after described amplification to signal output part.
Wherein, described input stage electrical equipment comprises: the first heterojunction bipolar transistor and the second heterojunction bipolar transistor; Wherein,
The base stage of described first heterojunction bipolar transistor is connected with the first end of the second end of the 3rd resistance, the second end of the 5th inductance and the 5th electric capacity respectively;
The emitter of described first heterojunction bipolar transistor is connected with the second end of the 5th electric capacity and the first end of the 7th inductance respectively;
The collector electrode of described first heterojunction bipolar transistor is connected with the emitter of the second heterojunction bipolar transistor;
The collector electrode of described second heterojunction bipolar transistor respectively with the second end of the 3rd inductance and the first end of the 4th electric capacity, and the described first end of the 3rd inductance is connected with the second end of the first resistance.
Wherein, described two-stage cascode resistance-capacitance coupling amplification grade circuit comprises: the 3rd heterojunction bipolar transistor and the 4th heterojunction bipolar transistor; Wherein,
The base stage of described 3rd heterojunction bipolar transistor is connected with the second end of the 4th electric capacity;
The collector electrode of described 3rd heterojunction bipolar transistor is connected with the second end of the 3rd electric capacity and the second end of the 4th inductance respectively;
The emitter of described 3rd heterojunction bipolar transistor is connected with the first end of the 6th inductance;
The base stage of described 4th heterojunction bipolar transistor is connected with the first end of the 3rd electric capacity and the second end of the second resistance respectively, and the first end of described second resistance is connected with the first end of described second inductance;
The collector electrode of described 4th heterojunction bipolar transistor is connected with the first end of the second end of the second inductance and the second end of the first inductance and the second electric capacity respectively;
The emitter of described 4th heterojunction bipolar transistor is connected with the first end of the first electric capacity and the first end of the 4th inductance respectively.
Wherein, described output buffer stage circuit comprises: the 5th heterojunction bipolar transistor; Wherein,
The base stage of described 5th heterojunction bipolar transistor is connected with the second end of the second electric capacity and the second end of the 4th resistance respectively;
The collector electrode of described 5th heterojunction bipolar transistor is connected with the second end of the 6th inductance and the first end of the 6th electric capacity respectively;
The emitter of described 5th heterojunction bipolar transistor is connected with the first end of the 5th resistance.
Wherein, the base stage of described second heterojunction bipolar transistor is all connected with the first voltage source with the first end of the first resistance;
The first end of described first inductance connects the second voltage source;
The first end of described 3rd resistance connects tertiary voltage source;
The first end of described 4th resistance connects the 4th voltage source;
Second end of described 7th inductance, the second end of the first electric capacity, the second end of the 6th electric capacity and the second end of the 5th resistance are all connected with earth terminal;
Described signal input part connects the first end of the 5th inductance;
The emitter of described 5th heterojunction bipolar transistor is all connected with signal output part with the first end of the 5th resistance.
Wherein, described first heterojunction bipolar transistor, the second heterojunction bipolar transistor, the 3rd heterojunction bipolar transistor, the 4th heterojunction bipolar transistor and the 5th heterojunction bipolar transistor are silicon germanium heterojunction bipolar transistor.
Wherein, described second voltage source provides DC offset voltage, and the voltage of the second voltage source equals 2.84V.
The beneficial effect of technique scheme of the present utility model is as follows:
The utility model circuit structure, by adopting Cascode structure as input stage circuit, while raising is gain, achieves input resistant matching and noise matching; Two-stage cascode resistance-capacitance coupling amplifying stage has carried out secondary amplification to signal, wherein the load of the 4th heterojunction bipolar transistor (Q4) adopts the parallel feedback of shunt peaking inductance L 1 and L2 and R2, add the gain flatness of Circuits System, and expand the bandwidth of system; Export the output impedance coupling of buffer stage circuit realiration system.Two-stage cascode resistance-capacitance coupling amplifying stage and output buffer stage adopt the cascade of current multiplexing technology, are operated in a DC channel, greatly reduce the power consumption of system.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of 3-8GHz low-power consumption ultra-wide band low noise amplifier of the present utility model;
Fig. 2 is the circuit diagram of 3-8GHz low-power consumption ultra-wide band low noise amplifier described in the utility model;
Fig. 3 is the Input matching of 3-8GHz low-power consumption ultra-wide band low noise amplifier described in the utility model, the simulation result of output matching;
Fig. 4 is the simulation result of 3-8GHz low-power consumption ultra-wide band low noise amplifier described in the utility model gain;
Fig. 5 is the simulation result of 3-8GHz low-power consumption ultra-wide band low noise amplifier noise factor described in the utility model.
Embodiment
For making the technical problems to be solved in the utility model, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
As shown in Figure 1, a kind of low-power consumption ultra-wideband low-noise amplifier, can be operated in 3-8GHz frequency band, comprise:
Input stage circuit, the input connection signal input RF of this input stage circuit
in, Received signal strength input RF
inthe input signal of input;
Two-stage cascode resistance-capacitance coupling amplification grade circuit, the input of this two-stage cascode resistance-capacitance coupling amplification grade circuit connects the output of described input stage circuit, amplifies described input signal, and exports the signal after amplifying;
Export buffer stage circuit, the input of this output buffer stage circuit is connected with the output of described two-stage cascode resistance-capacitance coupling amplification grade circuit, exports the signal after described amplification to signal output part RF
out.
In embodiment of the present utility model, described amplifier is made up of Cascode input stage, two-stage cascode resistance-capacitance coupling amplifying stage and output buffer stage.Adopt current multiplexing technology that two-stage cascode resistance-capacitance coupling amplifying stage and output buffer stage are coupled together, greatly reduce the power consumption of this low noise amplifier.Wherein the load of two-stage cascode resistance-capacitance coupling amplifying stage adopts the parallel feedback of shunt peaking inductance L 1 and L2 and R2, adds the gain flatness of Circuits System, and has expanded the bandwidth of system.
As shown in Figure 2, described input stage electrical equipment comprises: the first heterojunction bipolar transistor Q1 and the second heterojunction bipolar transistor Q2; Wherein, the base stage of described first heterojunction bipolar transistor Q1 is connected with the first end of second end of the 3rd resistance R3, the second end of the 5th inductance L 5 and the 5th electric capacity C5 respectively;
The emitter of described first heterojunction bipolar transistor Q1 is connected with second end of the 5th electric capacity C5 and the first end of the 7th inductance L 7 respectively;
The collector electrode of described first heterojunction bipolar transistor Q1 is connected with the emitter of the second heterojunction bipolar transistor Q2;
The collector electrode of described second heterojunction bipolar transistor Q2 respectively with the second end of the 3rd inductance L 3 and the first end of the 4th electric capacity C4, and the first end of described 3rd inductance L 3 is connected with second end of the first resistance R1.
In embodiment of the present utility model, the Cascode structure that first heterojunction bipolar transistor Q1 and the second heterojunction bipolar transistor Q2 is formed is as input stage circuit, while raising is gain, achieve input resistant matching and noise matching, bias voltage is provided by V3 and V1 respectively, makes it be operated in saturation condition, improves the gain of circuit, L5, R3, C5 and L7 form input matching network, achieve input resistant matching and the noise matching of system.Wherein V1=1.54V, V3=0.97V, R1=2 Ω, R3=245 Ω, L3=7.26nH, L5=0.9nH, L7=0.4nH, C5=0.18pF.
As shown in Figure 2, described two-stage cascode resistance-capacitance coupling amplification grade circuit comprises: the 3rd heterojunction bipolar transistor Q3 and the 4th heterojunction bipolar transistor Q4; Wherein, the base stage of described 3rd heterojunction bipolar transistor Q3 is connected with second end of the 4th electric capacity C4;
The collector electrode of described 3rd heterojunction bipolar transistor Q3 is connected with second end of the 3rd electric capacity C3 and the second end of the 4th inductance L 4 respectively;
The emitter of described 3rd heterojunction bipolar transistor Q3 is connected with the first end of the 6th inductance L 6;
The base stage of described 4th heterojunction bipolar transistor Q4 is connected with the first end of the 3rd electric capacity C3 and second end of the second resistance R2 respectively, and the first end of described second resistance R2 is connected with the first end of described second inductance L 2;
The collector electrode of described 4th heterojunction bipolar transistor Q4 is connected with the first end of the second end of the second inductance L 2 and the second end of the first inductance L 1 and the second electric capacity C2 respectively;
The emitter of described 4th heterojunction bipolar transistor Q4 is connected with the first end of the first electric capacity C1 and the first end of the 4th inductance L 4 respectively.
In embodiment of the present utility model, 3rd heterojunction bipolar transistor Q3 and the 4th heterojunction bipolar transistor Q4 forms two-stage cascode resistance-capacitance coupling structure for amplifying, L4 intercepts the emitter of the AC signal after Q3 amplifies to Q4, C1 provides AC deposition, the base stage making the AC signal after Q3 cascode amplifies deliver to Q4 by coupling capacitance C3 carries out the amplification of secondary cascode, deliver to output buffer stage through coupling capacitance C2 again, thus further increase the gain of system.In order to expand bandwidth, add the parallel feedback of shunt peaking inductance L 1 and L2 and R2, the parallel feedback of L2 and R2 also improves gain flatness and the stability of system simultaneously.Wherein V2=2.84V, C1=3.25pF, C2=0.41pF, C3=0.6pF, L1=31.53nH, L2=3.04nH, L4=2.79nH, R2=5K Ω.
As shown in Figure 2, described output buffer stage circuit comprises: the 5th heterojunction bipolar transistor Q5; Wherein, the base stage of described 5th heterojunction bipolar transistor Q5 is connected with second end of the second electric capacity C2 and second end of the 4th resistance R4 respectively;
The collector electrode of described 5th heterojunction bipolar transistor Q5 is connected with the second end of the 6th inductance L 6 and the first end of the 6th electric capacity C6 respectively;
The emitter of described 5th heterojunction bipolar transistor Q5 is connected with the first end of the 5th resistance R5.
In embodiment of the present utility model, the base stage of described second heterojunction bipolar transistor Q2 is all connected with the first voltage source V 1 with the first end of the first resistance R1; The first end of described first inductance L 1 connects the second voltage source V 2; The first end of described 3rd resistance R3 connects tertiary voltage source V3; The first end of described 4th resistance R4 connects the 4th voltage source V 4; Second end of described 7th inductance L 7, second end of the first electric capacity C1, second end of the 6th electric capacity C6 and second end of the 5th resistance R5 all connect earth terminal; Described signal input part RF
inconnect the first end of the 5th inductance L 5; The emitter of described 5th heterojunction bipolar transistor Q5 and the first end of the 5th resistance R5 all with signal output part RF
outconnect.
In embodiment of the present utility model, the 5th heterojunction bipolar transistor Q5 constitutes the output buffer stage of system, achieves the output impedance coupling of system, provide biased by V4 and R4 while playing voltage buffer.Wherein V4=0.93V, R4=263 Ω, L6=12nH, C6=0.5pF, R6=71 Ω.Adopt current multiplexing technology that Q4, Q3, Q5 are coupled together, thus greatly reduce the power consumption of system.
Adopt Jazz0.35umSiGeHBT technology library herein, utilize the radio frequency integrated circuit design tool ADS of Agilent company to carry out simulating, verifying to circuit.
Fig. 3 is the simulation result of 3-8GHz low-power consumption ultra-wideband low-noise amplifier described in the utility model input, output matching.This shows, in 3-8GHz frequency band range, S11 (input reflection coefficient) and S22 (output reflection coefficient), below-13.5dB, shows that low noise amplifier of the present utility model achieves good input and output impedance matching in whole frequency band.
Fig. 4 is the simulation result of 3-8GHz low-power consumption ultra-wideband low-noise amplifier described in the utility model gain.This shows, in 3-8GHz frequency band range, average gain (S21) is 19.2dB, and least gain is 18.8dB, and maximum gain is 19.6dB, shows that low noise amplifier of the present utility model gain flatness in whole frequency band is good.
Fig. 5 is the simulation result of 3-8GHz low-power consumption ultra-wideband low-noise amplifier noise factor described in the utility model.This shows, in 3-8GHz frequency band range, NF (noise factor), at below 2.8dB, shows that low noise amplifier of the present utility model has good noise factor in whole frequency band.
The utility model adopts Cascode structure as input stage, while raising is gain, achieves noise matching and input resistant matching; Two-stage cascode resistance-capacitance coupling amplifying stage has carried out secondary amplification to signal, further increase the gain of system, wherein the load of the 4th heterojunction bipolar transistor Q4 adopts the parallel feedback of shunt peaking inductance L 1 and L2 and R2, add the gain flatness of Circuits System, and expand the bandwidth of system; Export the output impedance coupling that buffer stage achieves system.Wherein two-stage cascode resistance-capacitance coupling amplifying stage and output buffer stage adopt the cascade of current multiplexing technology, are operated in a DC channel, greatly reduce the power consumption of system.
Above embodiment only in order to circuit structure of the present utility model to be described, is not intended to limit.Although be described in detail the utility model with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be modified to the circuit structure described in foregoing embodiments, or carries out equivalent replacement to wherein part circuit structure; And these amendments or replacement, do not make the essence of related circuit structure depart from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (7)
1. a low-power consumption ultra-wideband low-noise amplifier, is characterized in that, comprising:
Input stage circuit, the input signal of the input Received signal strength input input of this input stage circuit;
Two-stage cascode resistance-capacitance coupling amplification grade circuit, the input of this two-stage cascode resistance-capacitance coupling amplification grade circuit connects the output of described input stage circuit, amplifies described input signal, and exports the signal after amplifying;
Export buffer stage circuit, the input of this output buffer stage circuit is connected with the output of described two-stage cascode resistance-capacitance coupling amplification grade circuit, exports the signal after described amplification to signal output part.
2. low-power consumption ultra-wideband low-noise amplifier according to claim 1, is characterized in that, described input stage electrical equipment comprises: the first heterojunction bipolar transistor (Q1) and the second heterojunction bipolar transistor (Q2); Wherein,
The base stage of described first heterojunction bipolar transistor (Q1) is connected with the first end of the second end of the 3rd resistance (R3), the second end of the 5th inductance (L5) and the 5th electric capacity (C5) respectively;
The emitter of described first heterojunction bipolar transistor (Q1) is connected with the second end of the 5th electric capacity (C5) and the first end of the 7th inductance (L7) respectively;
The collector electrode of described first heterojunction bipolar transistor (Q1) is connected with the emitter of the second heterojunction bipolar transistor (Q2);
The collector electrode of described second heterojunction bipolar transistor (Q2) respectively with the second end of the 3rd inductance (L3) and the first end of the 4th electric capacity (C4), and the first end of described 3rd inductance (L3) is connected with the second end of the first resistance (R1).
3. low-power consumption ultra-wideband low-noise amplifier according to claim 2, it is characterized in that, described two-stage cascode resistance-capacitance coupling amplification grade circuit comprises: the 3rd heterojunction bipolar transistor (Q3) and the 4th heterojunction bipolar transistor (Q4); Wherein,
The base stage of described 3rd heterojunction bipolar transistor (Q3) is connected with the second end of the 4th electric capacity (C4);
The collector electrode of described 3rd heterojunction bipolar transistor (Q3) is connected with the second end of the 3rd electric capacity (C3) and the second end of the 4th inductance (L4) respectively;
The emitter of described 3rd heterojunction bipolar transistor (Q3) is connected with the first end of the 6th inductance (L6);
The base stage of described 4th heterojunction bipolar transistor (Q4) is connected with the first end of the 3rd electric capacity (C3) and the second end of the second resistance (R2) respectively, and the first end of described second resistance (R2) is connected with the first end of described second inductance (L2);
The collector electrode of described 4th heterojunction bipolar transistor (Q4) is connected with the first end of the second end of the second inductance (L2) and the second end of the first inductance (L1) and the second electric capacity (C2) respectively;
The emitter of described 4th heterojunction bipolar transistor (Q4) is connected with the first end of the first electric capacity (C1) and the first end of the 4th inductance (L4) respectively.
4. low-power consumption ultra-wideband low-noise amplifier according to claim 3, is characterized in that, described output buffer stage circuit comprises: the 5th heterojunction bipolar transistor (Q5); Wherein,
The base stage of described 5th heterojunction bipolar transistor (Q5) is connected with the second end of the second electric capacity (C2) and the second end of the 4th resistance (R4) respectively;
The collector electrode of described 5th heterojunction bipolar transistor (Q5) is connected with the second end of the 6th inductance (L6) and the first end of the 6th electric capacity (C6) respectively;
The emitter of described 5th heterojunction bipolar transistor (Q5) is connected with the first end of the 5th resistance (R5).
5. low-power consumption ultra-wideband low-noise amplifier according to claim 4, is characterized in that,
The base stage of described second heterojunction bipolar transistor (Q2) is all connected with the first voltage source (V1) with the first end of the first resistance (R1);
The first end of described first inductance (L1) connects the second voltage source (V2);
The first end of described 3rd resistance (R3) connects tertiary voltage source (V3);
The first end of described 4th resistance (R4) connects the 4th voltage source (V4);
Second end of described 7th inductance (L7), the second end of the first electric capacity (C1), the second end of the 6th electric capacity (C6) and the second end of the 5th resistance (R5) are all connected with earth terminal;
Described signal input part connects the first end of the 5th inductance (L5);
The emitter of described 5th heterojunction bipolar transistor (Q5) is all connected with signal output part with the first end of the 5th resistance (R5).
6. low-power consumption ultra-wideband low-noise amplifier according to claim 5, it is characterized in that, described first heterojunction bipolar transistor (Q1), the second heterojunction bipolar transistor (Q2), the 3rd heterojunction bipolar transistor (Q3), the 4th heterojunction bipolar transistor (Q4) and the 5th heterojunction bipolar transistor (Q5) are silicon germanium heterojunction bipolar transistor.
7. low-power consumption ultra-wideband low-noise amplifier according to claim 6, is characterized in that, described second voltage source (V2) provides DC offset voltage, and the voltage of the second voltage source equals 2.84V.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105141268A (en) * | 2015-09-25 | 2015-12-09 | 北京华朔物联网科技有限公司 | Amplifier with low power consumption, ultra-wide band and low noise |
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|---|---|---|---|---|
| CN105141268A (en) * | 2015-09-25 | 2015-12-09 | 北京华朔物联网科技有限公司 | Amplifier with low power consumption, ultra-wide band and low noise |
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