CN204834604U

CN204834604U - Semiconductor device of high heat dissipating ability

Info

Publication number: CN204834604U
Application number: CN201520680233.0U
Authority: CN
Inventors: 陈一峰; 李春江
Original assignee: Chengdu Gastone Technology Co Ltd
Current assignee: Chengdu Hiwafer Technology Co Ltd
Priority date: 2015-09-02
Filing date: 2015-09-02
Publication date: 2015-12-02
Anticipated expiration: 2025-09-02

Abstract

The utility model provides a semiconductor device of high heat dissipating ability. This semiconductor device includes: substrate, substrate have a plurality of through -holes, and the through -hole runs through to the lower surface of substrate from the upper surface of substrate, the epitaxial wafer, the epitaxial wafer is grown on the substrate, wherein, the epitaxial wafer including the nucleation layer that is located crossgrowth on the substrate with be located the device structure on the nucleation layer. In this way, the utility model discloses device heat dispersion can be improved, device operating temperature is effectively reduced.

Description

The semiconductor device of high heat dispersion

Technical field

The utility model relates to semiconductor device processing technology field, particularly relates to a kind of semiconductor device of high heat dispersion.

Background technology

Large power semiconductor device, especially with the third generation semiconductor device that GaN, SiC are representative, has broad application prospects in field of power electronics and the communications field.In field of power electronics, third generation semiconductor device has the following advantages: ON resistance is little, is conducive to raising equipment efficiency and saves the energy; Operating frequency can reach more than 1MHz, is conducive to improving integrated level, reducing equipment volume.In the communications field, third generation semiconductor device energy gap is large, working temperature is high, operating voltage is high, is conducive to being widely applied to high-frequency high-power occasion.

But semiconductor device is under high power work condition, and caloric value is very large, channel temperature can reach more than 150 DEG C, and along with the rising of channel temperature, the performance of device is by sharp-decay, even device will lose efficacy, and this seriously constrains the development of power semiconductor.In fact, along with the development of science and technology, semiconductor device application at high temperature under high pressure increases gradually, such as, power electronic device is generally used for processing high voltage, big current, voltage process range is from tens volts to several kilovolts, and current capacity reaches as high as a few kiloampere, is commonly used to do frequency conversion, transformation, unsteady flow, power management etc.Therefore, the working temperature reducing semiconductor device is further one of study hotspot always.

Rational heat dissipation design is utilized to be reduce one of semiconductor device working temperature main path.Current, existing heat dissipation design is generally the form adopting support plate at semiconductor device outward, is unfavorable for the integrated further of device.

Utility model content

The technical problem that the utility model mainly solves is to provide a kind of semiconductor device of high heat dispersion, can improve device heat dispersion, effectively reduce device operating temperature.

For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: the semiconductor device providing a kind of high heat dispersion, comprise: substrate, described substrate has multiple through hole, and described through hole is through to the lower surface of described substrate from the upper surface of described substrate; Epitaxial wafer, described epitaxial wafer growth is over the substrate; Wherein, described epitaxial wafer comprises the nucleating layer being positioned at cross growth on described substrate and the device architecture be positioned on described nucleating layer.

Preferably, described substrate is SiC substrate, GaN substrate, Si substrate, Sapphire Substrate or GaAs substrate.

Preferably, described through hole is uniformly distributed over the substrate.

Preferably, the shape of described through hole is circular, ellipse, triangle or quadrangle.

Preferably, the size of described through hole is 1-500 μm, and the spacing of described through hole is 5-800 μm.

Preferably, described nucleating layer is GaN film or SiC film.

Preferably, the thickness of described nucleating layer is 0-1mm.

Preferably, condensing agent is filled with in described through hole.

Preferably, described device architecture comprises the channel layer and barrier layer that stack gradually from the bottom to top, described barrier layer is formed with source electrode, grid, drain electrode and covers the dielectric layer of described barrier layer, source electrode, grid and drain electrode.

Be different from the situation of prior art, the beneficial effects of the utility model are: because substrate has multiple through hole, heat can be distributed by through hole, thus device heat dispersion can be improved, effectively reduce device operating temperature, and due to the existence of through hole, the nucleating layer of cross growth and the lattice adaptation of substrate little, between each layer of epitaxial wafer, stress is little, higher than traditional epitaxial wafer quality, so have better device performance.

Accompanying drawing explanation

Fig. 1 is the schematic cross-section of the semiconductor device of the utility model one embodiment high heat dispersion.

Fig. 2 is the schematic top plan view of the substrate of the semiconductor device shown in Fig. 1.

Fig. 3 is the schematic cross-section of the semiconductor device of another embodiment high heat dispersion of the utility model.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only a part of embodiment of the present utility model, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.

In the lump see Fig. 1 and Fig. 2, the utility model provides a kind of semiconductor device of high heat dispersion, and it comprises substrate 1 and epitaxial wafer 2.Substrate 1 has multiple through hole 11, and through hole 11 is through to the lower surface of substrate 1 from the upper surface of substrate 1.Epitaxial wafer 2 grows on substrate 1, and epitaxial wafer 2 comprises the nucleating layer 20 being positioned at cross growth on substrate 1 and the device architecture 30 be positioned on nucleating layer 20.

In the present embodiment, substrate 1 is SiC substrate, GaN substrate, Si substrate, Sapphire Substrate or GaAs substrate, certainly, also can be the substrate of other materials.

Through hole 11 is uniformly distributed on substrate 1, and as shown in Figure 2, through hole 11 is arranged as array on substrate 1.Alternatively, the size of through hole 11 is 1-500 μm, and the spacing of through hole 11 is 5-800 μm.It should be noted that the utility model is not construed as limiting the arrangement mode of through hole 11, in some other embodiment, through hole 11 also can non-uniform Distribution on substrate 1.The shape of through hole 11 can be regular figure, and be such as circular, ellipse, triangle or quadrangle, also can be irregular figure, in the present embodiment, the shape of through hole 11 be square.

Due to the existence of through hole 11, the heat of semiconductor device can distribute from through hole 11, in the present embodiment, is filled with condensing agent in through hole 11, to improve the radiating rate of through hole 11.Certainly, in some other embodiment, can not condensing agent be filled in through hole 11, and utilize air draught to improve radiating rate.Further, substrate 1 can be as far as possible thinning, can be more conducive to heat radiation, and such as, substrate 1 can be thinning by mechanical lapping, also can be thinning by chemical etching.

Nucleating layer 20 can be GaN film or SiC film.GaN film or SiC film not only have good cross growth characteristic, and little with the lattice adaptation of substrate 1, and the stress between each layer of the epitaxial wafer 2 finally obtained is also little.Alternatively, the thickness of nucleating layer 20 is 0-1mm.

See Fig. 3, it is the schematic cross-section of the semiconductor device of another embodiment high heat dispersion of the utility model.In the semiconductor device of the present embodiment, device architecture 30 specifically comprises the channel layer 31 and barrier layer 32 that stack gradually from the bottom to top, barrier layer 32 is formed source electrode 33, grid 34, drain electrode 35 and cover barrier layer 32, source electrode 33, grid 34 and drain electrode 35 dielectric layer 36.

By the way, the semiconductor device of the high heat dispersion of the utility model embodiment is multiple through hole because substrate has, heat can be distributed by through hole, thus device heat dispersion can be improved, effectively reduce device operating temperature, and due to the existence of through hole, the nucleating layer of cross growth and the lattice adaptation of substrate little, between each layer of epitaxial wafer, stress is little, higher than traditional epitaxial wafer quality, so have better device performance.

The foregoing is only embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every utilize the utility model specification and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.

Claims

1. a semiconductor device for high heat dispersion, is characterized in that, comprising:

Substrate, described substrate has multiple through hole, and described through hole is through to the lower surface of described substrate from the upper surface of described substrate;

Epitaxial wafer, described epitaxial wafer growth is over the substrate;

Wherein, described epitaxial wafer comprises the nucleating layer being positioned at cross growth on described substrate and the device architecture be positioned on described nucleating layer.

2. semiconductor device according to claim 1, is characterized in that, described substrate is SiC substrate, GaN substrate, Si substrate, Sapphire Substrate or GaAs substrate.

3. the semiconductor device of high heat dispersion according to claim 1 and 2, is characterized in that, described through hole is uniformly distributed over the substrate.

4. semiconductor device according to claim 3, is characterized in that, the shape of described through hole is circular, ellipse, triangle or quadrangle.

5. semiconductor device according to claim 3, is characterized in that, the size of described through hole is 1-500 μm, and the spacing of described through hole is 5-800 μm.

6. semiconductor device according to claim 1, is characterized in that, described nucleating layer is GaN film or SiC film.

7. semiconductor device according to claim 6, is characterized in that, the thickness of described nucleating layer is 0-1mm.

8. semiconductor device according to claim 1, is characterized in that, is filled with condensing agent in described through hole.

9. semiconductor device according to claim 1, it is characterized in that, described device architecture comprises the channel layer and barrier layer that stack gradually from the bottom to top, described barrier layer is formed with source electrode, grid, drain electrode and covers the dielectric layer of described barrier layer, source electrode, grid and drain electrode.