CN212136452U

CN212136452U - Semiconductor structure

Info

Publication number: CN212136452U
Application number: CN202020552104.4U
Authority: CN
Inventors: 程凯
Original assignee: Enkris Semiconductor Inc
Current assignee: Enkris Semiconductor Inc
Priority date: 2020-04-14
Filing date: 2020-04-14
Publication date: 2020-12-11
Anticipated expiration: 2030-04-14

Abstract

The present application provides a semiconductor structure. The semiconductor structure includes: a substrate; a nucleation layer, a buffer layer, a back barrier layer, a channel layer and a barrier layer which are sequentially arranged on the substrate in a stacking mode; a source and a drain in contact with the barrier layer; a cap layer provided on the barrier layer in a region other than the source electrode and the drain electrode; the passivation layer is arranged in the region except the source electrode, the drain electrode and the grid electrode on the cap layer; the grid electrode is arranged on the cap layer; wherein the material of the nucleation layer is AlN; the thickness of the back barrier layer is more than 1 nm; the thickness of the channel layer is less than 300 nm; the thickness of the barrier layer is 1nm-10 nm; the thickness of the cap layer is more than 0.1 nm; the semiconductor structure further includes: the buffer layer is arranged on the back barrier layer, the transition layer is arranged between the buffer layer and the back barrier layer, and the insertion layer is arranged between the back barrier layer and the channel layer. The performance of the device can be further improved by setting the overall structure of the semiconductor structure and the thickness of the key structure layer.

Description

Semiconductor structure

Technical Field

The present application relates to the field of semiconductors, and more particularly, to a semiconductor structure.

Background

At present, the third generation wide bandgap semiconductor material gallium nitride has the characteristics of large forbidden bandwidth, high electron saturation drift velocity, high breakdown field strength, good heat conduction performance and the like, so that the material is more suitable for manufacturing devices with high temperature, high frequency, high voltage and high power than silicon and gallium arsenide. The gallium nitride device has a good application prospect in the aspect of high-frequency high-power microwave devices, and the development of the gallium nitride device is one of hot spots of electronic device research from the 20 th century to the present 90 th. Due to the lack of an intrinsic substrate for gallium nitride, gallium nitride devices are all fabricated on foreign substrates such as sapphire, silicon carbide and silicon. Among these substrates, the substrate made of silicon has the largest size (200mm) and the lowest price, so growing gallium nitride materials and devices on the substrate has attracted much attention.

However, it is very difficult to grow an epitaxial film of gallium nitride on a substrate due to the large lattice mismatch and thermal mismatch between the silicon material and the nitride. Firstly, aluminum nitride needs to be grown to prevent the reaction between gallium atoms and the substrate, and the gallium atoms can play a role in etching the substrate in an ammonia atmosphere. In addition, the wetting of gallium nitride on the substrate is poor, making it very difficult to obtain a uniform and continuous epitaxial film of gallium nitride. Therefore, how to effectively inhibit the formation of misfit dislocation and reduce the dislocation density is a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

The application provides a semiconductor structure, through the overall structure who sets up semiconductor structure and the thickness of key structure layer, can further improve the performance of device.

To achieve the above object, according to an embodiment of the present application, there is provided a semiconductor structure including:

a substrate;

the nucleation layer, the buffer layer, the back barrier layer, the channel layer and the barrier layer are sequentially arranged on the substrate in a laminated mode;

a source and a drain in contact with the barrier layer;

a cap layer provided on the barrier layer in a region other than the source electrode and the drain electrode;

the grid electrode is arranged on the cap layer;

the passivation layer is arranged in the region except the source electrode, the drain electrode and the grid electrode on the cap layer;

wherein the material of the nucleation layer is AlN; the thickness of the back barrier layer is more than 1 nm; the thickness of the channel layer is less than 300 nm; the thickness of the barrier layer is 1nm-10 nm; the thickness of the cap layer is more than 0.1 nm;

the semiconductor structure further includes:

the transition layer is arranged between the buffer layer and the back barrier layer;

the insertion layer is arranged between the back barrier layer and the channel layer, and the insertion layer is made of InGaN.

Optionally, the material of the buffer layer includes one of GaN, AlGaN, and AlN.

Optionally, the material of the back barrier layer includes one of GaN, AlGaN, and AlN.

Optionally, the material of the channel layer includes one of GaN and InGaN.

Optionally, the barrier layer is made of one of AlN, GaN, and AlGaN.

Optionally, the cap layer is made of a material including one of SiN and GaN.

Optionally, the material of the substrate comprises Si, SiC and Al₂O₃One kind of (1).

Optionally, the material of the passivation layer includes Al₂O₃SiN, GaN, AlN; wherein AlN is in a polycrystalline state or in an amorphous state.

In the semiconductor structure of the above embodiment, the performance of the device can be further improved by setting the overall structure of the semiconductor structure and the thickness of the key structure layer. Specifically, by generating a nucleation layer made of AlN on the substrate, the gallium nitride epitaxial layer is grown on the nucleation layer made of AlN, the formation of misfit dislocation can be effectively inhibited, and the dislocation density can be reduced, so that the beneficial effect of effectively controlling the dislocation density is achieved; in addition, the back barrier layer is arranged in the semiconductor structure, so that the carrier confinement can be improved, and the main channel carriers cannot be conducted through the leakage of the buffer layer in an off state; furthermore, the performance of the device can be further improved by setting the thickness of the key structure layer.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

Description of the reference numerals

Substrate 1

Nucleation layer 2

Buffer layer 3

Back barrier layer 4

Channel layer 5

Barrier layer 6

Capping layer 7

Passivation layer 8

Grid 9

Source electrode 10

Drain electrode 11

Transition layer 12

The insertion layer 13

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "plurality" includes two, and is equivalent to at least two. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

As shown in fig. 1, the present embodiment provides a semiconductor structure. The semiconductor structure includes: a nucleation layer 2, a buffer layer 3, a back barrier layer 4, a channel layer 5 and a barrier layer 6 which are sequentially arranged on a substrate 1 in a laminated manner; a source electrode 10 and a drain electrode 11 in contact with the barrier layer 6; a cap layer 7 provided on the barrier layer 6 in a region other than the source electrode 10 and the drain electrode 11; the passivation layer 8 is arranged on the cap layer 7 except for the source electrode 10, the drain electrode 11 and the grid electrode 9; a gate 9 disposed on the cap layer 7; wherein, the material of the nucleation layer 2 is AlN; the thickness of the back barrier layer 4 is greater than 1 nm; the thickness of the channel layer 5 is less than 300 nm; the thickness of the barrier layer 6 is 1nm-10 nm; the cap layer 7 has a thickness of more than 0.1 nm.

Thus, by generating the AlN nucleating layer 2 on the substrate 1 and growing the GaN epitaxial layer on the AlN nucleating layer 2, the formation of misfit dislocation can be effectively inhibited and the dislocation density can be reduced, thereby achieving the beneficial effect of effectively controlling the dislocation density; in addition, the back barrier layer 4 is provided in the semiconductor structure, which can improve carrier confinement, so that the main channel carrier is not conducted by leakage of current through the buffer layer 3 in an off state. Furthermore, the performance of the device can be further improved by setting the thickness of the key structure layer.

The back barrier layer raises the conduction band bottom energy of the channel layer 5 and improves the electron mobility. The density and thickness of the back barrier affect the density of the 2DEG, and the back barrier can reach the thickness of more than 1nm under certain concentration, so that the leakage of the device can be reduced and the performance of the device can be improved on the basis of ensuring the formation of the back barrier layer 4 with high uniformity.

Under certain conditions, the two-dimensional electron gas and electrical characteristics show a parabolic characteristic along with the increase of the thickness of the channel layer 5, and the control of the thickness of the channel layer 5 to be less than 300nm is to ensure the excellent device characteristics.

When the thickness of the barrier layer 6 is 1nm-10nm, the barrier layer can be combined with the thickness limitation of the channel layer 5 to ensure the two-dimensional electron gas density.

The cap layer 7 with the thickness higher than 0.1nm can well reduce the surface state of the nitride semiconductor, play roles of passivation and protection on the surface and reduce the current collapse effect of the device.

The semiconductor structure further comprises a transition layer 12 and an insertion layer 13.

The transition layer 12 is provided between the buffer layer 3 and the back barrier layer 4, and the concentration of the Al component in the transition layer 12 gradually increases from the side near the buffer layer 3 to the side near the back barrier layer 4. In this way, by providing the transition layer 12 between the buffer layer 3 and the back barrier layer 4 and increasing the concentration of the Al component in the transition layer 12 from the side close to the buffer layer 3 to the side close to the back barrier layer 4, the grown epitaxial layer can be made less defective, and the performance of the device can be further improved.

The insertion layer 13 is disposed between the back barrier layer 4 and the channel layer 5, and the material of the insertion layer 13 is InGaN. In this way, by providing the insertion layer 13 made of InGaN between the back barrier layer 4 and the channel layer 5, an effect of smoothing an electric field can be obtained.

The material of the buffer layer 3 includes one or a combination of GaN, AlGaN, and AlN. The buffer layer 3 is doped with Fe or C, and the doping concentration of the Fe or C is more than 1e17cm^-3. By doping Fe or C, a highly intrinsic layer can be formed, the insulativity is improved, and the electric leakage problem of the buffer layer 3 is improved; and the doping concentration of Fe or C is set to be more than 1e17cm^-3This is because the doping concentration needs to be limited to some extent.

The Al composition in the back barrier layer 4 is greater than 70%. The material of the back barrier layer 4 comprises one or a combination of GaN, AlGaN, AlN.

The material of the channel layer 5 includes one or a combination of GaN and InGaN.

The Al composition in the barrier layer 6 is greater than 70%. The material of the barrier layer 6 includes one or a combination of AlN, GaN, and AlGaN.

The cap layer 7 is made of SiN or GaN or a combination of the SiN and the GaN. The material of the substrate 1 includes Si, SiC, Al₂O₃One or more of the above.

The material of the passivation layer 8 includes Al₂O₃SiN, GaN and AlN; wherein AlN is in a polycrystalline state or in an amorphous state.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor structure, comprising:

a substrate;

a source and a drain in contact with the barrier layer;

the grid electrode is arranged on the cap layer;

the semiconductor structure further includes:

2. The semiconductor structure of claim 1, wherein the material of the buffer layer comprises one of GaN, AlGaN, AlN.

3. The semiconductor structure of claim 1, wherein the material of the back barrier layer comprises one of GaN, AlGaN, AlN.

4. The semiconductor structure of claim 1, wherein the material of the channel layer comprises one of GaN, InGaN.

5. The semiconductor structure of claim 1, wherein the material of the barrier layer comprises one of AlN, GaN, AlGaN.

6. The semiconductor structure of claim 1, wherein a material of the cap layer comprises one of SiN, GaN.

7. The semiconductor structure of claim 1, in which the material of the substrate comprises Si, SiC, Al₂O₃One kind of (1).

8. The semiconductor structure of claim 1, in which a material of the passivation layer comprises Al₂O₃SiN, GaN, AlN; wherein AlN is in a polycrystalline state or in an amorphous state.