CN204808315U - System based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol - Google Patents
System based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol Download PDFInfo
- Publication number
- CN204808315U CN204808315U CN201520537432.6U CN201520537432U CN204808315U CN 204808315 U CN204808315 U CN 204808315U CN 201520537432 U CN201520537432 U CN 201520537432U CN 204808315 U CN204808315 U CN 204808315U
- Authority
- CN
- China
- Prior art keywords
- spi
- master control
- serial peripheral
- control borad
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Communication Control (AREA)
- Bus Control (AREA)
Abstract
The utility model discloses a system based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol, control boards including the main control board and with main control board communication connection's a plurality of the follow, just all be provided with the CPU treater on main control board, the follow accuse board, still include: still set up logic controller, SPI serial peripheral hardware interface with CPU communication connection on main control board, the follow accuse board, the main control board with from the accuse board through setting up data bus and then the communication connection on the SPI interface. The utility model provides a system based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol, it can have simple structure, and two -way data communication and transmission efficiency are high, and the accuracy is good, the strong effect of stability.
Description
Technical field
The utility model relates to a kind of communication system used in electron device data communication situation.More particularly, the utility model relates to a kind of system realizing communication between plates based on SPI serial peripheral interface protocol being used in electron device data communication situation.
Background technology
Day by day complicated along with communication facilities, the requirement of functional interfaces is also varied, in order to the satisfied electron device caused thus increases the requirement with user's configurability and extensibility, the mode of current equipment many employings master control borad multiple function subcard collaborative work, function subcard can increase and decrease according to the configuration of equipment and demand arbitrarily or replace.For requirements such as equipment collaboration work and network management configuration, need exchanges data, and will realize the general management to distinct device between equipment plate card, need at master control borad and different between control plate, set up a kind of communication mechanism, formation can safeguard manageable passage.
At present, in distributing real communication system, HDLC due to its busy line number less, transmission data are reliably selected as the communication between plates bus of interactive maintenance information, be widely used between master control borad and interface board, it can meet the application that point-to-point application can adapt to again point-to-multipoint, in system operation, multi-site shares a HDLC bus, master control borad sends order and configuration data by HDLC down going channel to each interface board, adopt the mode of poll to carry out acquisition interface plate information simultaneously, interface board feeds back current board state and other information by HDLC data feedback channel to master control borad, transfer rate is maximum reaches 10Mbit/S.
But when adopting HDLC bus to be used for communication between plates, also there is corresponding problem, one, it is on synchronization up direction, an interface board is only allowed to send data to bus, make master control borad be in passive position, have no idea to realize the active access to from control plate, and then make the data communication mode without duplex therebetween; They are two years old, when it sends data from control plate to bus, depend on and limit from the difference of the I/O interface level of control plate CPU, easily occur that interface board sends the problems such as misdata bag to master control borad, the interface board that serious words can affect other communicates with master control borad, affects transfer efficiency; Its three, when it adopts HDLC bus for communication between plates, in order to ensure data transmission reliability, it needs extra increase control circuit, complex system degree increase.
Utility model content
An object of the present utility model solves at least the problems referred to above and/or defect, and provide the advantage will illustrated at least below.
The utility model also has an object to be to provide a kind of system realizing communication between plates based on SPI serial peripheral interface protocol, and it is simple that it can have structure, bidirectional data communication and transfer efficiency is high, and accuracy is good, the effect that stability is strong.
In order to realize according to these objects of the present utility model and other advantage, provide a kind of system realizing communication between plates based on SPI serial peripheral interface protocol, comprise master control borad and with master control borad communicate to connect multiple from controlling plate, and described master control borad, from control plate be provided with CPU processor, also comprise:
Described master control borad described is also provided with the logic controller and SPI Serial Peripheral Interface (SPI) that are connected with respective CPU processor with each from control plate;
Wherein, described master control borad described is undertaken being connected to set up bidirectional data communication link from controlling plate by the spi bus be connected between respective SPI Serial Peripheral Interface (SPI) with each, and the logic controller being in described bidirectional data communication link receiving end carries out break-make control to the bidirectional data communication link through spi bus, and then realize master control borad and each described from the bidirectional data communication controlled between plate by the CPU processor of making a start.
Preferably, wherein, described logic controller is any one in FPGA field programmable gate array or CPLD CPLD.
Preferably, wherein, described master control borad, from control plate SPI interface in, its clock signal CCLK, input data signal CI, outputting data signals CO and chip selection signal CS share, and,
CPU or logical control device on master control borad as the holotype of SPI serial peripheral data communication, the CPU or logical control device on each daughter board as data communication from pattern.
Preferably, wherein, described master control borad, from the CPU andlogic control device of control plate all by AD bus and then realize communicating to connect, and be connected with the external interrupt of at least one CPU.
Preferably, wherein, be provided with storer described in each from control plate, each described storer includes and is respectively used to store the multiple special registers from the type and concrete business controlling plate
Preferably, wherein, described master control borad is provided with each from controlling board type and respectively carrying out mapping the local register stored from controlling special register number information plate to what inquire.
Preferably, wherein, the CPU processor of described master control borad and the mainboard of external unit communicate to connect, and then carry out online upgrading configuration by spi bus to each FPGA from control plate.
The utility model at least comprises following beneficial effect: one, signal wiring is carried out by spi bus due to its master control borad and from controlling between plate, its communication between plates is made to become duplex from traditional single work, only allow a communication link to carry out data communication relative to traditional synchronization, its data communication efficiency is significantly improved.
They are two years old, its master control borad and from the break-make controlling the two-way communication data link set up by spi bus between plate, is realized by snoop logic controller, controls break-make relative to traditional by the I/O interface of CPU, it is high that it has accuracy, the effect of good stability.
Part is embodied by explanation below by other advantage of the present utility model, target and feature, part also will by research and practice of the present utility model by those skilled in the art is understood.
Accompanying drawing explanation
Fig. 1 is the structural representation of the system realizing communication between plates in an embodiment of the present utility model based on SPI serial peripheral interface protocol;
Fig. 2 is the data flow diagram of the system realizing communication between plates in another embodiment of the present utility model based on SPI serial peripheral interface protocol.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail, can implements according to this with reference to instructions word to make those skilled in the art.
Should be appreciated that used hereinly such as " to have ", other element one or more do not allotted in " comprising " and " comprising " term or the existence of its combination or interpolation.
Fig. 1 shows according to a kind of system way of realization realizing communication between plates based on SPI serial peripheral interface protocol of the present utility model, comprise master control borad 1 and with master control borad communicate to connect multiple from controlling plate 2, and described master control borad, from control plate be provided with CPU processor 10,20, comprising:
Described master control borad described is also provided with the logic controller 11,21 and SPI Serial Peripheral Interface (SPI) (not shown) that are connected with respective CPU processor with each from control plate;
Wherein, described master control borad described is undertaken being connected to set up bidirectional data communication link from controlling plate by the spi bus 3 be connected between respective SPI Serial Peripheral Interface (SPI) with each, and the logic controller being in described bidirectional data communication link receiving end carries out break-make control to the bidirectional data communication link through spi bus, and then realize master control borad and each described from the bidirectional data communication controlled between plate by the CPU processor of making a start.
Adopt this scheme its relative to traditional communication between plates mode, because which employs the combination of CPU+ logic controller, simultaneously its master control borad with each from controlling the SPI interface that plate is arranged respectively, make its communication between plates can carry out exchanges data by SPI data bus, it can realize the communication pattern of duplex, the transfer efficiency of the data greatly improved, secondly one is only allowed to send for information from control plate to master control borad relative to traditional synchronization, it can realize in synchronization permission multiple from controlling plate to the data access of master control borad, in addition, the combination of CPU+ logic controller also makes to which reduce extra dedicated control circuit, simplify system architecture, have can implementation result good, transfer efficiency is high, the favourable part of good stability.Further, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.
In another kind of example, described logic controller is any one in FPGA field programmable gate array or CPLD CPLD.This scheme is adopted to make traditional communication between plates realize the break-make of data link by the I/O interface of CPU processor, change to the break-make being realized data link by logic controller, there is accuracy good, can the favourable part of good, the good stability of implementation result.Further, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.
In another kind of example, described master control borad, from control plate SPI interface in, its clock signal CCLK, input data signal CI, outputting data signals CO and chip selection signal CS share, and,
CPU or logical control device on master control borad as the holotype of SPI serial peripheral data communication, the CPU or logical control device on each daughter board as data communication from pattern.Adopt this scheme for master control borad with distinguish from controlling plate, to distinguish its data access mode, there is the favourable part that exploitativeness is good.Further, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.
In another kind of example, described master control borad, from the CPU andlogic control device of control plate all by AD bus 4 and then realize communicating to connect, and be connected with the external interrupt of at least one CPU.This scheme is adopted to have the favourable part of good stability.Further, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.
In another kind of example, storer is provided with from control plate described in each, each described storer includes and is respectively used to store the multiple special registers from the type and concrete business controlling plate, adopt in this scheme each from control plate special register address can be identical, then unification is mapped to the FPGA of master control borad, there is data query and have certificate, the favourable part that implementation result is good.Further, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.
In another kind of example, described master control borad is provided with each from controlling board type and respectively carrying out mapping the local register stored from controlling special register number information plate to what inquire.As shown in Figure 2, the mapping mode in this scheme is adopted to be: master control borad is after FPGA starts, first judge have how many to be connected to master control borad from control plate, and through each type from control plate in place of SPI interface polls, FPGA storer the effective information such as register number, and it is inner relevant information to be extracted the local register address being stored in master control borad; Secondly the FPGA of master control borad knows connection thereon each after effective register number of control plate, the special register that automatic regular polling is respectively corresponding from control plate, and is mapped by the data message in it in the local register interval be stored on master control borad; Then each mapping address from control plate that the CPU of master control borad is corresponding in AD bus inquiry master control borad FPGA is to obtain respectively from the register information of control plate; Finally, master control borad CPU carries out relevant configuration according to each register information from control plate extracted, and be stored in the local pinning memory of FPGA corresponding on master control borad, by the SPI interface on master control borad configuration information to be sent to the data communication that each correspondence realizes between plate from control plate plate, the described CPU from control plate is configured rear information based on what read from FPGA special register its respective panels, further exchanges data is carried out with the external world, have can implementation result good, the favourable part of good stability.Further, this mode is a kind of explanation of preferred embodiments, but is not limited thereto.
In another kind of example, the CPU processor of described master control borad and the mainboard (not shown) of external unit communicate to connect, and then carry out online upgrading configuration by spi bus to each FPGA from control plate.Adopt this scheme to make respectively to be strengthened from the expansibility of control plate, decrease the probability of upgrading, have and extend its serviceable life, the favourable part that product stability is good.
Here the number of devices illustrated and treatment scale are used to simplify explanation of the present utility model.To of the present utility modelly realizing the systematic difference of communication between plates based on SPI serial peripheral interface protocol, modifications and variations will be readily apparent to persons skilled in the art.
As mentioned above, according to the utility model, one, signal wiring is carried out by spi bus due to its master control borad and from controlling between plate, its communication between plates is made to become duplex from traditional single work, only allow a communication link to carry out data communication relative to traditional synchronization, its data communication efficiency is significantly improved.
They are two years old, its master control borad and from the break-make controlling the two-way communication data link set up by spi bus between plate, is realized by snoop logic controller, controls break-make relative to traditional by the I/O interface of CPU, it is high that it has accuracy, the effect of good stability.
Although embodiment of the present utility model is open as above, it is not restricted to listed in instructions and embodiment utilization.It can be applied to various applicable field of the present utility model completely.For those skilled in the art, can easily realize other amendment.Therefore do not deviating under the universal that claim and equivalency range limit, the utility model is not limited to specific details and illustrates here and the legend described.
Claims (7)
1. realize a system for communication between plates based on SPI serial peripheral interface protocol, comprise master control borad and with master control borad communicate to connect multiple from controlling plate, and described master control borad, from control plate be provided with CPU processor, it is characterized in that, also comprise:
Described master control borad described is also provided with the logic controller and SPI Serial Peripheral Interface (SPI) that are connected with respective CPU processor with each from control plate;
Wherein, described master control borad described is undertaken being connected to set up bidirectional data communication link from controlling plate by the spi bus be connected between respective SPI Serial Peripheral Interface (SPI) with each, and the logic controller being in described bidirectional data communication link receiving end carries out break-make control to the bidirectional data communication link through spi bus, and then realize master control borad and each described from the bidirectional data communication controlled between plate by the CPU processor of making a start.
2. the as claimed in claim 1 system realizing communication between plates based on SPI serial peripheral interface protocol, is characterized in that, described logic controller is any one in FPGA field programmable gate array or CPLD CPLD.
3. the system realizing communication between plates based on SPI serial peripheral interface protocol as claimed in claim 2, it is characterized in that, described master control borad, from control plate SPI interface in, its clock signal CCLK, input data signal CI, outputting data signals CO and chip selection signal CS share, and
CPU or logical control device on master control borad as the holotype of SPI serial peripheral data communication, the CPU or logical control device on each daughter board as data communication from pattern.
4. the system realizing communication between plates based on SPI serial peripheral interface protocol as claimed in claim 3, it is characterized in that, described master control borad, from the CPU andlogic control device of control plate all by AD bus and then realize communicating to connect, and be connected with the external interrupt of at least one CPU.
5. the system realizing communication between plates based on SPI serial peripheral interface protocol as claimed in claim 4, it is characterized in that, be provided with storer from control plate described in each, each described storer includes and is respectively used to store the multiple special registers from the type and concrete business controlling plate.
6. the system realizing communication between plates based on SPI serial peripheral interface protocol as claimed in claim 1, it is characterized in that, described master control borad is provided with each from controlling board type and respectively carrying out mapping the local register stored from controlling special register number information plate to what inquire.
7. the system realizing communication between plates based on SPI serial peripheral interface protocol as claimed in claim 1, it is characterized in that, the CPU processor of described master control borad and the mainboard of external unit communicate to connect, and then carry out online upgrading configuration by spi bus to each FPGA from control plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520537432.6U CN204808315U (en) | 2015-07-23 | 2015-07-23 | System based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520537432.6U CN204808315U (en) | 2015-07-23 | 2015-07-23 | System based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204808315U true CN204808315U (en) | 2015-11-25 |
Family
ID=54593102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520537432.6U Expired - Fee Related CN204808315U (en) | 2015-07-23 | 2015-07-23 | System based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204808315U (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719469A (en) * | 2016-01-26 | 2016-06-29 | 苏州迈瑞微电子有限公司 | SPI (serial peripheral interface) protocol based network relay system and operation method thereof |
| CN106294253A (en) * | 2016-07-22 | 2017-01-04 | 安徽皖通邮电股份有限公司 | A kind of interrupt signal processing system |
| CN106598888A (en) * | 2016-12-22 | 2017-04-26 | 广东威创视讯科技股份有限公司 | Multi-board card communication system and method adopting RS485 protocol |
| CN107301138A (en) * | 2017-06-01 | 2017-10-27 | 深圳震有科技股份有限公司 | A kind of universal serial bus bridging method and serial bus system |
| CN107677869A (en) * | 2017-09-25 | 2018-02-09 | 优利德科技(中国)有限公司 | A kind of apparatus and method for improving message transmission rate between SPI interface ADC and MCU |
| CN108268413A (en) * | 2018-02-28 | 2018-07-10 | 郑州云海信息技术有限公司 | Extend system, method, server and the machine system of PCIE interface quantities |
| CN109766291A (en) * | 2018-12-06 | 2019-05-17 | 珠海格力电器股份有限公司 | A kind of method of automatic configuration and system of the port I/O |
| CN112416832A (en) * | 2020-11-06 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | Communication system based on MIPS framework processor |
| CN112835840A (en) * | 2021-02-07 | 2021-05-25 | 深圳市英威腾交通技术有限公司 | Serial communication system |
| CN113126479A (en) * | 2021-03-23 | 2021-07-16 | 广东芬尼克兹节能设备有限公司 | Coordination control method of double-master-control-board circuit |
-
2015
- 2015-07-23 CN CN201520537432.6U patent/CN204808315U/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719469A (en) * | 2016-01-26 | 2016-06-29 | 苏州迈瑞微电子有限公司 | SPI (serial peripheral interface) protocol based network relay system and operation method thereof |
| CN106294253A (en) * | 2016-07-22 | 2017-01-04 | 安徽皖通邮电股份有限公司 | A kind of interrupt signal processing system |
| WO2018113217A1 (en) * | 2016-12-22 | 2018-06-28 | 威创集团股份有限公司 | Multi-board communication system and method using rs485 protocol |
| CN106598888A (en) * | 2016-12-22 | 2017-04-26 | 广东威创视讯科技股份有限公司 | Multi-board card communication system and method adopting RS485 protocol |
| CN106598888B (en) * | 2016-12-22 | 2019-07-12 | 广东威创视讯科技股份有限公司 | A kind of more board communication systems and method using RS485 agreement |
| CN107301138A (en) * | 2017-06-01 | 2017-10-27 | 深圳震有科技股份有限公司 | A kind of universal serial bus bridging method and serial bus system |
| CN107301138B (en) * | 2017-06-01 | 2019-05-17 | 深圳震有科技股份有限公司 | A kind of universal serial bus bridging method and serial bus system |
| CN107677869A (en) * | 2017-09-25 | 2018-02-09 | 优利德科技(中国)有限公司 | A kind of apparatus and method for improving message transmission rate between SPI interface ADC and MCU |
| CN108268413A (en) * | 2018-02-28 | 2018-07-10 | 郑州云海信息技术有限公司 | Extend system, method, server and the machine system of PCIE interface quantities |
| CN109766291A (en) * | 2018-12-06 | 2019-05-17 | 珠海格力电器股份有限公司 | A kind of method of automatic configuration and system of the port I/O |
| CN109766291B (en) * | 2018-12-06 | 2020-10-23 | 珠海格力电器股份有限公司 | Automatic configuration method and system of I/O port |
| CN112416832A (en) * | 2020-11-06 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | Communication system based on MIPS framework processor |
| CN112835840A (en) * | 2021-02-07 | 2021-05-25 | 深圳市英威腾交通技术有限公司 | Serial communication system |
| CN112835840B (en) * | 2021-02-07 | 2024-06-04 | 深圳市英威腾交通技术有限公司 | Serial communication system |
| CN113126479A (en) * | 2021-03-23 | 2021-07-16 | 广东芬尼克兹节能设备有限公司 | Coordination control method of double-master-control-board circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204808315U (en) | System based on inter -plate communication is realized to SPI serial peripheral hardware interface protocol | |
| CN103248526A (en) | Communication equipment and method for achieving out-of-band monitoring and management, and master-slave switching method | |
| CN104899170A (en) | Distributed intelligent platform management bus (IPMB) connection method and ATCA (Advanced Telecom Computing Architecture) machine frame | |
| CN110635982B (en) | Double-host communication method and system on communication bus, industrial control gateway and storage medium | |
| CN103729333A (en) | Backplane bus structure sharing multiple channel time slots and implementation method thereof | |
| CN1964285A (en) | A master control device with double CPU and realization method | |
| CN109783416A (en) | SPI shares method, circuit and the electronic equipment of GPIO from equipment and I2C from equipment | |
| CN108600017A (en) | Multi-protocols serial ports expansion method | |
| CN106873541A (en) | A kind of EtherCAT Distributed Servo kinetic control systems based on DSP | |
| CN105993148B (en) | Network interface | |
| CN101082896A (en) | Control method and device between master-salve module | |
| CN1489727A (en) | Method and apparatus for re-configurable processor | |
| CN103914427B (en) | The means of communication and device on integrated circuit chips based on three physical interconnections lines | |
| CN106874228A (en) | Based on I2Communication means between the controller and communication means, multi-controller of C buses | |
| CN104486256B (en) | The multi plane switching fabric equipment of oriented integration network IA frame serverPC | |
| CN103561116A (en) | Reconfigurable PXI serial communication card and method for achieving remote reconfiguration through reconfigurable PXI serial communication card | |
| CN108959157A (en) | A kind of control system and method for programmable logic device | |
| CN110096114B (en) | System and method for managing multiple ARM server nodes | |
| CN105577752B (en) | A kind of management system for fusion architecture server | |
| CN105550157A (en) | Fractal tree structure commutation structure and method, control device and intelligent chip | |
| CN104932837A (en) | Storage pool framework | |
| CN101902436A (en) | Interplate communication method, device and system | |
| CN209765401U (en) | System for managing multiple ARM server nodes | |
| CN102346503B (en) | Cabinet and cabinet system | |
| CN104346310A (en) | Data exchange circuit and method of high-performance I2C slave equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 621000 Sichuan city of Mianyang province high tech Zone Puming South East No. 111 Patentee after: Sichuan Lingtong Telecommunications Co., Ltd. Address before: 621000 Sichuan city of Mianyang province high tech Zone Puming South East No. 111 Patentee before: Mianyang Netop Telecom Equipment Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151125 Termination date: 20160723 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |