CN112835840A

CN112835840A - Serial communication system

Info

Publication number: CN112835840A
Application number: CN202110174443.2A
Authority: CN
Inventors: 王辉华; 邓知先; 谭成午
Original assignee: Shenzhen Invt Transportation Technology Co ltd
Current assignee: Shenzhen Invt Transportation Technology Co ltd
Priority date: 2021-02-07
Filing date: 2021-02-07
Publication date: 2021-05-25
Anticipated expiration: 2041-02-07
Also published as: CN112835840B

Abstract

The application discloses a serial communication system, which comprises a master device and a slave device; the master device and the slave device both adopt a CPU + FPGA structure, wherein the FPGA is connected with the corresponding CPU in an analog RAM interface mode to realize the communication in the device; the FPGA of the master device and the FPGA of the slave device are connected with each other in an analog SPI serial interface mode to realize master-slave communication between the devices. According to the method, the CPU is used for operating and controlling in a bus access RAM mode, the effect of sharing the dual-port RAM is achieved based on the FPGA of the master device and the slave device, wiring is simple and suitable for remote communication, the communication speed is high, the efficiency is high, the protocol is simple, the CPU occupancy rate is effectively reduced, and the communication real-time performance, the bandwidth utilization rate and the anti-interference capability are improved.

Description

Serial communication system

Technical Field

The present application relates to the field of data communication technologies, and in particular, to a serial communication system.

Background

The devices need to communicate when working cooperatively. For example, between the host controller and the execution units, control commands need to be communicated to the execution units in real time, and status information needs to be fed back to the host controller quickly. The mutual communication between devices is usually realized by using a bus, such as 232, 485, CAN, Ethernet, etc., and the interfaces thereof generally utilize the hardware resources of the CPU in the devices. Therefore, the CPU needs to spend a large amount of running time to manage, and the implementation process of the whole communication protocol is complicated, so that the real-time performance of the communication data and the utilization rate of the bus bandwidth are difficult to control.

In view of the above, it is an important need for those skilled in the art to provide a solution to the above technical problems.

Disclosure of Invention

The application aims to provide a serial communication system so as to effectively improve the real-time performance and the bandwidth utilization rate of data communication.

In order to solve the above technical problem, the present application discloses a serial communication system, including a master device and a slave device:

the master device and the slave device both adopt a CPU + FPGA structure, wherein the FPGA is connected with the corresponding CPU in an analog RAM interface mode to realize the communication in the device; and the FPGA of the master device and the FPGA of the slave device are mutually connected in an analog SPI serial interface mode to realize master-slave communication between the devices.

Optionally, a communication data frame sent by the master device to the slave device includes a frame type definition word, where the frame type definition word is used to specify an information type of the current communication data frame;

and the different information types correspond to different cache regions, so that the slave device can read and write data aiming at the cache region corresponding to the frame type definition word when responding to the master device.

Optionally, different information types correspond to different priorities, so that when the master device sends a communication data frame to the slave device, the master device specifically sends the communication data frame to be sent with the highest current priority to the slave device.

Optionally, the information type includes at least one of:

real-time control frame, periodic control information refresh frame, designated address information read frame, parameter read-write frame, fast state information read-back frame, slow state information read-back frame, slave request response frame, other appointment information read-back frame.

Optionally, when sending the communication data frame to the slave device, the FPGA of the master device is specifically configured to:

regularly sending corresponding communication data frames according to a preset sending period; and after writing the sending request mark into the RAM specific address of the FPGA by the CPU of the main device, sending the communication data frame appointed by the CPU.

Optionally, the SPI serial interface between the master device and the slave device is connected by an optical fiber.

Optionally, in the master device and the slave device, the data connection line between the CPU and the FPGA includes an address line, a data line, and a control line; and the data connecting line between the FPGA of the master device and the FPGA of the slave device comprises a clock signal line, a master device sending line and a slave device sending line.

Optionally, when the master device and the slave device perform SPI serial communication, the master device reads data on a rising edge of a clock signal and writes data on a falling edge of the clock signal.

Optionally, a communication data frame between the master device and the slave device includes a start bit and an end bit;

the start bit is 2 low levels and 1 high level which continuously appear in the clock signal; the end bit is 1 high level which is 2 high levels continuously appearing in the clock signal.

Optionally, a frame format of a communication data frame sent by the master device to the slave device is:

start bit + frame type definition word + key control command word + classification information packet + check word + end bit;

the frame format of the communication data frame sent by the slave device to the master device is as follows:

start bit + request return frame length + key state information word + classification information response packet + check word + end bit.

The serial communication system provided by the application has the beneficial effects that: according to the method, the CPU is used for operating and controlling in a bus access RAM mode, the effect of sharing the dual-port RAM is achieved based on the FPGA of the master device and the slave device, wiring is simple and suitable for remote communication, the communication speed is high, the efficiency is high, the protocol is simple, the CPU occupancy rate is effectively reduced, and the communication real-time performance, the bandwidth utilization rate and the anti-interference capability are improved.

Drawings

In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.

Fig. 1 is a block diagram of a serial communication system according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a format of a communication data frame disclosed in an embodiment of the present application;

fig. 3 is a schematic diagram of a data transceiving process of a master device according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a data transceiving process of a slave device according to an embodiment of the present disclosure;

fig. 5 is a flowchart illustrating a master device generating a frame type definition word according to an embodiment of the present disclosure.

Detailed Description

The core of the application is to provide a serial communication system so as to effectively improve the real-time performance and the bandwidth utilization rate of data communication.

In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, an embodiment of the present application discloses a serial communication system, which includes a master device and a slave device;

the master device and the slave device both adopt a CPU + FPGA structure, wherein the FPGA is connected with the corresponding CPU in an analog RAM interface mode to realize the communication in the device; the FPGA of the master device and the FPGA of the slave device are connected with each other in an analog SPI serial interface mode to realize master-slave communication between the devices.

Specifically, CPUs (Central Processing units) in the master device and the slave device may be implemented based on control chips such as an ARM single chip microcomputer or a DSP (Digital Signal Processing), and are used in combination with an FPGA (Field Programmable Gate Array) to complete serial communication between the master device and the slave device.

In the master device and the slave device, a RAM space is created inside the FPGA and is connected with the CPU in a RAM interface mode, and the CPU can access the RAM through an address data bus. In addition, the FPGA also simulates an SPI interface, and the two FPGAs realize the exchange and synchronization of RAM data between the two devices through the communication of the SPI serial interface.

Therefore, data reading and writing are carried out between the FPGA and the CPUs in an analog RAM interface mode, the master device and the slave device are communicated through the FPGA analog SPI serial interface, and after communication data are processed and managed through the FPGA, the effect of sharing the dual-port RAM is achieved between the two CPUs.

It should be noted that sharing a dual-port RAM can directly perform data exchange, which is the fastest and effective communication mode between two CPUs. In the conventional technology, the number of address lines, data lines, control lines and the like between two CPUs and a double-port RAM chip are required to be respectively connected, so that the two CPUs are required to be physically connected on the same board or through a backboard bus, the cost is high, and the application limitation is large. The effect of sharing the dual-port RAM is achieved through the two FPGAs, complex wiring is avoided, a wiring structure is simplified, and meanwhile anti-interference performance is improved. And more importantly, the problems of high CPU occupancy rate and low communication efficiency in the traditional communication can be solved.

Specifically, in an embodiment, in the serial communication system provided in the embodiment of the present application, on the basis of the foregoing, in the master device and the slave device, the data connection line between the CPU and the FPGA includes an address line, a data line, and a control line; the data connecting line between the FPGA of the master device and the FPGA of the slave device comprises a clock signal line, a master device sending line and a slave device sending line.

Further, in one embodiment, the SPI serial interface between the master device and the slave device may be connected, in particular, by an optical fiber. By adopting the optical fiber communication, the influence of the environmental distance can be avoided, the problem that the transmission distance is limited in the traditional double-port RAM communication mode is solved, and the applicability and the anti-interference capability of the communication are further improved.

Therefore, the serial communication system provided by the application has the advantages that the CPU accesses the RAM through the bus for operation control, the effect of sharing the dual-port RAM is achieved based on the FPGA of the master device and the slave device, wiring is simple, the serial communication system is suitable for remote communication, the communication speed is high, the efficiency is high, the protocol is simple, the CPU occupancy rate is effectively reduced, and the communication real-time performance, the bandwidth utilization rate and the anti-jamming capability are improved.

As a specific embodiment, in the serial communication system provided in the embodiment of the present application, on the basis of the above content, a communication data frame sent by a master device to a slave device includes a frame type definition word, where the frame type definition word is used to specify an information type of a current communication data frame;

the different information types correspond to different buffer areas, so that when the slave device responds to the master device, data reading and writing are carried out on the buffer area corresponding to the frame type definition word.

Specifically, in this embodiment, a frame type definition word for indicating the type of information classification is introduced into a communication data frame, according to a protocol of a pre-agreed command word, an FPGA of the master device locates a data transmission address according to the frame type definition word, and the slave device immediately performs parsing after receiving the frame type definition word, and sets a data transceiver address pointer. Therefore, the method and the device can ensure that different types of information are stored in the established storage area, and effectively improve the communication efficiency by processing the different types of information in a partitioning manner.

For example, as a specific embodiment, in the serial communication system provided in the embodiment of the present application, on the basis of the foregoing, the information type may specifically include at least one of the following:

As a specific embodiment, based on the above content, the serial communication system provided in the embodiment of the present application corresponds to different priority levels for the master device to specifically send the communication data frame to be sent with the highest current priority level to the slave device when sending the communication data frame to the slave device.

Specifically, in order to perform scientific and orderly processing on different types of information, the present embodiment sets different processing priorities for different types of communication data frames. After one frame of information is sent out, the FPGA inquires the priority of each communication data frame to be sent again so as to arrange the sending according to the data priority. Wherein a communication data frame to be transmitted may be identified by setting a corresponding transmit request flag. Based on the setting and the use of the priority, the real-time performance and the bandwidth utilization rate of the communication can be further improved.

As a specific embodiment, in the serial communication system provided in the embodiment of the present application, on the basis of the foregoing content, when the FPGA of the master device sends a communication data frame to the slave device, the FPGA is specifically configured to:

Specifically, the present embodiment sets two initiation manners of communication data frames. The information which needs to be periodically sent is fixed and can be automatically and periodically sent by the FPGA; for some temporary or urgent information, the CPU can write a corresponding transmission request flag at a specific address in the RAM so that the FPGA initiates an information transmission operation after reading.

Referring to fig. 2, fig. 2 is a schematic diagram of a format of a communication data frame according to an embodiment of the present application. Where CLK is a clock signal, MOSI is a master (master) transmission signal, and MISO is a slave (slave) transmission signal.

Specifically, the clock signal may be generated by the host device, the baud rate is determined according to the hardware capability, and the communication speed is usually 5Mbps, taking ordinary optical fiber communication as an example. The clock signal outputs a fixed certain level in the non-communication period, and the clock signal is output in the communication stage.

As a specific embodiment, in the serial communication system provided in the embodiment of the present application, on the basis of the above contents, when the master device and the slave device perform SPI serial communication, the number is read on a rising edge of the clock signal and written on a falling edge of the clock signal. The data byte is sent with the upper bits before and the lower bits after.

As a specific embodiment, in the serial communication system provided in the embodiment of the present application, on the basis of the foregoing content, the communication data frames between the master device and the slave device each include a start bit and an end bit; the start bit is 2 low levels and 1 high level which continuously appear in the clock signal; the end bit is 1 high level for 2 high levels that occur consecutively in the clock signal. The end bit may also be referred to as a stop bit. Of course, other types of start and end bits can be designed and used by those skilled in the art, and the present application is not limited thereto.

As a specific embodiment, in the serial communication system provided in the embodiment of the present application, based on the above contents, a frame format of a communication data frame sent by a master device to a slave device is as follows:

the frame format of the communication data frame sent from the slave device to the master device is:

The check word is used for checking whether the received data is correct or not, if the received data is correct, a new data valid flag is set, and the CPU processes the data after receiving the valid flag.

In this embodiment, the data transceiving process of the master device may specifically refer to fig. 3. Specifically, once there is a need for sending a task, the master device first sets a sending/receiving address according to the information type, and automatically generates a check word during sending, and for a returned communication data frame, the data receiving flag bit is effectively set only when the check is passed. The process specifically comprises the following steps:

s101: judging whether a communication data frame needing to be sent currently exists according to the request sending mark; if yes, entering S102; if not, the process returns to S101.

S102: the transmission buffer address and the reception storage address are set based on a frame type definition word in the communication data frame.

S103: a start bit is sent.

S104: and sending a frame type definition word and receiving the length of a request return frame sent by the slave equipment.

S105: and transmitting a key control command word and receiving a key state information word transmitted from the equipment.

S106: sending a classification information packet, and receiving a classification information response packet sent by slave equipment; and calculates the check word.

S107: and transmitting the check word calculated by the self, and receiving the check word transmitted by the slave equipment.

S108: judging whether the checking result is normal or not; if yes, entering S109; if not, the process proceeds to S110.

S109: carrying out effective setting on the corresponding data receiving zone bit; the process proceeds to S110.

S110: a stop bit is sent.

Correspondingly, the data transceiving process of the slave device can specifically refer to fig. 4. Specifically, the request return frame length refers to a data length required to be read by the master device when the slave device has a new data packet, the data processing request flag of the request return frame length is placed in the key state information word, and the slave device effectively sets the data processing request flag only after the received communication data frame passes verification. The process may specifically include:

s201: judging whether the clock signal has a start bit; if yes, entering S202; if not, the process returns to S201.

S202: sending a request for a frame length; the process proceeds to S203.

S203: judging whether the frame type definition word is received completely; if yes, entering S204; if not, the process returns to S202.

S204: and setting a sending buffer address and a receiving storage address according to the frame type definition word.

S205: and receiving the control command word and returning a key state information word.

S206: and receiving the classification information packet and returning a classification information response packet.

S207: and receiving the check word sent by the master device.

S208: judging whether the verification passes; if yes, go to S209; if not, the process proceeds to S210.

S209: and setting the corresponding data processing request mark effectively.

S210: and finishing data transmission.

In one particular embodiment, the serial communication system disclosed herein may be particularly applicable in subway traction inverters. The main equipment can be a System Controller Unit (SCU) which is composed of an ARM single chip microcomputer and an FPGA; and the slave device may be embodied as a motor controller (PCU) and is composed of a DSP and an FPGA. The SCU is responsible for vehicle control logic, outputs control instructions required by operation to the PCU in real time, receives PCU state feedback, reads and writes PCU parameters, periodically reads PCU key signals (a fast change signal is defined as 2ms, and a slow change signal is defined as 10ms), and monitors waveforms (sends a monitoring signal offset address selected by a user, and then receives a selected signal feedback value at a frequency of 4000 times per second and outputs oscillography).

In one embodiment, the processing priorities corresponding to the information of several common functions may be, in order from high to low: sending control commands, reading and writing parameters, returning parameters, reading waveforms and reading information for faults (fault related information). When the information of a certain function needs to be sent, the corresponding flag bit is effectively set.

Thus, the process of the master device generating the frame type definition word can be seen in fig. 5, which includes:

s301: the master device judges whether data is currently transmitted or not; if yes, returning to S301 for waiting; if not, the process proceeds to S302.

S302: judging whether the control command sending zone bit is effectively set; if not, entering S303; if yes, the process proceeds to S308.

S303: judging whether the parameter reading and writing flag bit is effectively set; if not, entering S304; if yes, the process proceeds to S308.

S304: judging whether the parameter returning flag bit is set effectively; if not, the process goes to S305; if yes, the process proceeds to S308.

S305: judging whether the waveform reading flag bit is effectively set; if not, the step S307 is entered; if yes, the process proceeds to S306.

S306: judging whether a waveform signal reading period is reached; if not, the step S307 is entered; if yes, the process proceeds to S308.

S307: judging whether the information flag bit for the fault is effectively set; if yes, the process proceeds to S308.

S308: and generating and transmitting a corresponding frame type definition word.

The information for failure is the relevant information for failure analysis, and may be received and displayed at 1000 times of frequency, and the priority is lower than that of the waveform signal received at 4000 times of frequency.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.

It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.

Claims

1. A serial communication system comprising a master device and a slave device;

2. The serial communication system according to claim 1, wherein a communication data frame sent by the master device to the slave device includes a frame type definition word, the frame type definition word being used to specify an information type of the communication data frame at present;

3. The serial communication system according to claim 2, wherein different information types correspond to different priorities, so that when the master device sends a communication data frame to the slave device, the master device specifically sends the communication data frame to be sent with the highest current priority to the slave device.

4. The serial communication system of claim 2, wherein the type of information comprises at least one of:

5. The serial communication system according to claim 1, wherein the FPGA of the master device, when sending the communication data frame to the slave device, is specifically configured to:

6. The serial communication system according to claim 1, wherein the SPI serial interface between the master device and the slave device is connected by an optical fiber.

7. The serial communication system according to claim 2, wherein in the master device and the slave device, the data connection line between the CPU and the FPGA comprises an address line, a data line, a control line; and the data connecting line between the FPGA of the master device and the FPGA of the slave device comprises a clock signal line, a master device sending line and a slave device sending line.

8. The serial communication system according to claim 7, wherein the master device and the slave device read on a rising edge of a clock signal and write on a falling edge of the clock signal when performing SPI serial communication.

9. The serial communication system according to claim 8, wherein the communication data frames between the master device and the slave device each include a start bit and an end bit;

10. The serial communication system according to claim 9, wherein the frame format of the communication data frame transmitted by the master device to the slave device is: