CN204596773U - A kind of structure preventing chip cutting layering - Google Patents
A kind of structure preventing chip cutting layering Download PDFInfo
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- CN204596773U CN204596773U CN201520334592.0U CN201520334592U CN204596773U CN 204596773 U CN204596773 U CN 204596773U CN 201520334592 U CN201520334592 U CN 201520334592U CN 204596773 U CN204596773 U CN 204596773U
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Abstract
The utility model provides a kind of structure preventing chip cutting layering, and the periphery of described chip is provided with sealing ring, is provided with Cutting Road between chip and chip, is also provided with an empty passage between described Cutting Road and sealing ring.The utility model by arranging an empty passage between described Cutting Road and sealing ring, when cut crystal, utilize empty passage can prevent the TK weld pad on Cutting Road from producing stress at chip internal due to thermal expansion, and then lower the risk of chip internal generation layering.The utility model prevents the structure of chip cutting layering simple, is applicable to suitability for industrialized production.
Description
Technical field
The utility model relates to technical field of semiconductors, particularly relates to a kind of structure preventing chip cutting layering.
Background technology
The cutting of chip (Die) is the very important technique of semiconductor industry always.Semiconductor wafer (wafer), after having gone through complicated manufacturing process, needs to be divided into several circuit small pieces, namely chip.Chip is generally rectangular, is arranged in wafer surface, and wafer surface is provided with cancellate Cutting Road along chip grain surrounding, in order to separate each chip.Existing chip cutting method mainly contains cutter (as diamond cutter) cutting and emittance (as laser) cutting.Cutter cutting is the Cutting Road utilizing mechanical force to act directly on wafer, realizes the separation of chip.Laser cutting is contactless cutting method, it be laser energy by obtaining high-energy-density after optical focus, directly wafer is gasified along Cutting Road, thus separating chips.
If Fig. 1 is laser cutting chip architecture schematic diagram.In Fig. 1, the Cutting Road between chip 1 and chip 1 is wide 80 μm, and the width of laser beam 5 is 8 μm, and generally, customer requirement laser beam 5 will have the surplus of 7.5 μm to the distance of chip 1.But the chip cut down finds that after test chip produces the defects such as layering tilting, causes chip cannot be applied in the middle of side circuit.Find after further research, chip internal layering only occurs over just near the weld pad of Cutting Road test structure (Test key, TK), and other positions are all normal.Why layering can occur near TK weld pad, because laser cutting wafer utilizes is the hot melt principle of laser, when the high-energy-density of laser concentrates on Cutting Road TK weld pad, the horizontal thermal expansion of weld pad easily produces stress at chip internal, and then in chip internal generation layering.
Therefore, a kind of structure of chip cutting layering that prevents is provided to be necessary.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of structure preventing chip cutting layering, during for solving laser cutting wafer in prior art, on Cutting Road, the thermal expansion of TK weld pad produces stress at chip internal, causes the problem of chip internal generation layering.
For achieving the above object and other relevant objects, the utility model provides a kind of structure preventing chip cutting layering, the periphery of described chip is provided with sealing ring, is provided with Cutting Road between chip and chip, and also arranging between described Cutting Road and sealing ring is free passage.
Prevent the scheme of a kind of optimization of the structure of chip cutting layering as the utility model, the width range of described empty passage is 5 ~ 20 μm.
Prevent the scheme of a kind of optimization of the structure of chip cutting layering as the utility model, the width range of described Cutting Road is 40 ~ 70 μm.
Prevent the scheme of a kind of optimization of the structure of chip cutting layering as the utility model, in described Cutting Road, be formed with test structure.
Prevent the scheme of a kind of optimization of the structure of chip cutting layering as the utility model, described test structure comprises detection welding pad.
Prevent the scheme of a kind of optimization of the structure of chip cutting layering as the utility model, described detection welding pad is metal.
Prevent the scheme of a kind of optimization of the structure of chip cutting layering as the utility model, described sealing ring is the structure that insulating material is formed.
As mentioned above, the structure preventing chip cutting layering of the present utility model, the periphery of described chip is provided with sealing ring, is provided with Cutting Road between chip and chip, is also provided with an empty passage between described Cutting Road and sealing ring.The utility model by arranging an empty passage between described Cutting Road and sealing ring, when cut crystal, utilize empty passage can prevent the TK weld pad on Cutting Road from producing stress at chip internal due to thermal expansion, and then lower the risk of chip internal generation layering.The utility model prevents the structure of chip cutting layering simple, is applicable to suitability for industrialized production.
Accompanying drawing explanation
Fig. 1 is chip cutting schematic diagram of the prior art.
Fig. 2 is the structural representation preventing chip cutting layering of the present utility model.
Element numbers explanation
1 chip
2 sealing rings
3 empty passages
4 Cutting Roads
5 laser beams
Embodiment
By particular specific embodiment, execution mode of the present utility model is described below, person skilled in the art scholar the content disclosed by this specification can understand other advantages of the present utility model and effect easily.
Refer to Fig. 2.Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only in order to coordinate specification to disclose, understand for person skilled in the art scholar and read, and be not used to limit the enforceable qualifications of the utility model, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the utility model can produce and the object that can reach, still all should drop on technology contents that the utility model discloses and obtain in the scope that can contain.Simultaneously, quote in this specification as " on ", D score, "left", "right", " centre " and " one " etc. term, also only for ease of understanding of describing, and be not used to limit the enforceable scope of the utility model, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the utility model.
The utility model provides a kind of structure preventing from cutting layering, and as shown in Figure 2, the periphery of described chip 1 is provided with sealing ring 2, is provided with Cutting Road 4 between chip 1 and chip 1, and also arranging between described Cutting Road 4 and sealing ring 2 is free passage 3.
It should be noted that, described empty passage 3 can adopt etching to wait common process to be formed, and certainly, other suitable technique also can be adopted to be formed.Without active area in described empty passage 3, without polysilicon, there is no the device architectures such as contact hole yet.
The width of described empty passage 3 is suitable, and width is too narrow, does not have the effect of isolation; The width of empty passage 3 is too wide, and the Cutting Road 4 between chip 1 and chip 1 can be made again too narrow, the too narrow size that can affect making detection welding pad thereon of Cutting Road 4, size does not meet the demands, and WAT monitoring will be comparatively difficult.
Exemplarily, the width range prioritizing selection of described empty passage 3 is at 5 ~ 20 μm.In the present embodiment, the width of described empty passage 3 elects 10 μm temporarily as.Certainly, in other embodiments, the width of described empty passage 3 can also elect 6 μm, 8 μm, 12 μm, 15 μm or 18 μm etc. as.
Generally, be spaced apart 80 μm between chip 1 and chip 1, if the width range of an empty passage 3 is 5 ~ 20 μm, then the width range remaining Cutting Road 3 is 40 ~ 70 μm.
In described Cutting Road 4, be formed with test structure (diagram), for monitoring the technique etc. of chip 1, described test structure 1 comprises detection welding pad.Usually, described detection welding pad is metal, such as copper or aluminium etc.Width range due to Cutting Road 4 is 40 ~ 70 μm, and the size so making TK weld pad on Cutting Road 4 also should within the scope of 40 ~ 70 μm, and this meets the size needed for WAT monitoring.Preferably, in the present embodiment, the width of described Cutting Road 4 is 60 μm.
The structure that described sealing ring 2 is formed for insulating material, material can be silica or silicon nitride etc., for the protection of the structure of inside chip.Described sealing ring 2 can be one deck, also can be multilayer.In order to illustrate conveniently, only illustrate part sealing ring 2 in accompanying drawing 2, should know, sealing ring 2 should be around chip surrounding.
When utilizing laser cutting wafer, the heat of laser can pass to the detection welding pad of metal on Cutting Road 4, weld pad produces thermal expansion, but owing to being provided with sky passage 3 between sealing ring 2 and Cutting Road 4, cause expansion weld pad cannot transverse shear stress to chip 1, can prevent chip 1 inside from producing layering owing to being extruded like this.
In sum, the utility model provides a kind of structure preventing chip cutting layering, and the periphery of described chip is provided with sealing ring, is provided with Cutting Road between chip and chip, is also provided with an empty passage between described Cutting Road and sealing ring.The utility model by arranging an empty passage between described Cutting Road and sealing ring, when cut crystal, utilize empty passage can prevent the TK weld pad on Cutting Road from producing stress at chip internal due to thermal expansion, and then lower the risk of chip internal generation layering.The utility model prevents the structure of chip cutting layering simple, is applicable to suitability for industrialized production.
So the utility model effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all without prejudice under spirit of the present utility model and category, can modify above-described embodiment or changes.Therefore, such as have in art and usually know that the knowledgeable modifies or changes not departing from all equivalences completed under the spirit and technological thought that the utility model discloses, must be contained by claim of the present utility model.
Claims (7)
1. prevent a structure for chip cutting layering, the periphery of described chip is provided with sealing ring, is provided with Cutting Road between chip and chip, it is characterized in that, also arranging between described Cutting Road and sealing ring is free passage.
2. the structure preventing chip cutting layering according to claim 1, is characterized in that: the width range of described empty passage is 5 ~ 20 μm.
3. the structure preventing chip cutting layering according to claim 1, is characterized in that: the width range of described Cutting Road is 40 ~ 70 μm.
4. the structure preventing chip cutting layering according to claim 1, is characterized in that: be formed with test structure in described Cutting Road.
5. the structure preventing chip cutting layering according to claim 4, is characterized in that: described test structure comprises detection welding pad.
6. the structure preventing chip cutting layering according to claim 5, is characterized in that: described detection welding pad is metal.
7. the structure preventing chip cutting layering according to claim 1, is characterized in that: described sealing ring is the structure that insulating material is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520334592.0U CN204596773U (en) | 2015-05-22 | 2015-05-22 | A kind of structure preventing chip cutting layering |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520334592.0U CN204596773U (en) | 2015-05-22 | 2015-05-22 | A kind of structure preventing chip cutting layering |
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| CN204596773U true CN204596773U (en) | 2015-08-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074824A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN110660815A (en) * | 2018-06-28 | 2020-01-07 | 格科微电子（上海）有限公司 | Design method of CMOS image sensor wafer |
-
2015
- 2015-05-22 CN CN201520334592.0U patent/CN204596773U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074824A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN108074824B (en) * | 2016-11-08 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN110660815A (en) * | 2018-06-28 | 2020-01-07 | 格科微电子（上海）有限公司 | Design method of CMOS image sensor wafer |
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